195 lines
7.9 KiB
Diff
195 lines
7.9 KiB
Diff
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From ceae51b1cc0e5a5b42999274657bd55606193661 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Jari=20H=C3=A4m=C3=A4l=C3=A4inen?= <nuumiofi@gmail.com>
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Date: Sun, 22 Nov 2020 15:24:49 +0200
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Subject: [PATCH] nuumio: pcie: Reimplement rockchip PCIe bus scan delay
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Reimplementation of my old Rockchip PCIe bus scan delay patch for
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kernels >= 5.9.
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Delay may fix panix with some PCIe devices, like LSI SAS 9201-8i with
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SAS2008 chipset in my case.
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Crash dump (customized Manjaro kernel before this patch):
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[ 1.229856] SError Interrupt on CPU4, code 0xbf000002 -- SError
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[ 1.229860] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 5.9.9-2.0-MANJARO-ARM #1
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[ 1.229862] Hardware name: Pine64 RockPro64 v2.1 (DT)
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[ 1.229864] pstate: 60000085 (nZCv daIf -PAN -UAO BTYPE=--)
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[ 1.229866] pc : rockchip_pcie_rd_conf+0xb4/0x270
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[ 1.229868] lr : rockchip_pcie_rd_conf+0x1b4/0x270
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[ 1.229870] sp : ffff80001004b850
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[ 1.229872] x29: ffff80001004b850 x28: 0000000000000001
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[ 1.229877] x27: 0000000000000000 x26: ffff00007a795000
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[ 1.229882] x25: ffff00007a7910b0 x24: 0000000000000000
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[ 1.229887] x23: 0000000000000000 x22: ffff00007b3a4380
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[ 1.229891] x21: ffff80001004b8c4 x20: 0000000000000004
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[ 1.229895] x19: 0000000000100000 x18: 0000000000000020
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[ 1.229900] x17: 0000000000000001 x16: 0000000000000019
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[ 1.229904] x15: ffff00007b222fd8 x14: ffffffffffffffff
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[ 1.229908] x13: ffff00007a79ba1c x12: ffff00007a79b290
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[ 1.229912] x11: 0101010101010101 x10: 7f7f7f7f7f7f7f7f
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[ 1.229917] x9 : ff72646268756463 x8 : 0000000000000391
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[ 1.229921] x7 : ffff80001004b880 x6 : 0000000000000001
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[ 1.229925] x5 : 0000000000000000 x4 : 0000000000000000
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[ 1.229930] x3 : 0000000000c00008 x2 : 000000000080000a
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[ 1.229934] x1 : 0000000000000000 x0 : ffff800014000000
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[ 1.229939] Kernel panic - not syncing: Asynchronous SError Interrupt
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[ 1.229942] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 5.9.9-2.0-MANJARO-ARM #1
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[ 1.229944] Hardware name: Pine64 RockPro64 v2.1 (DT)
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[ 1.229946] Call trace:
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[ 1.229948] dump_backtrace+0x0/0x1d0
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[ 1.229949] show_stack+0x18/0x24
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[ 1.229951] dump_stack+0xc0/0x118
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[ 1.229953] panic+0x148/0x320
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[ 1.229955] nmi_panic+0x8c/0x90
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[ 1.229956] arm64_serror_panic+0x78/0x84
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[ 1.229958] do_serror+0x15c/0x160
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[ 1.229960] el1_error+0x84/0x100
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[ 1.229962] rockchip_pcie_rd_conf+0xb4/0x270
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[ 1.229964] pci_bus_read_config_dword+0x6c/0xd0
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[ 1.229966] pci_bus_generic_read_dev_vendor_id+0x34/0x1b0
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[ 1.229968] pci_scan_single_device+0xa4/0x144
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[ 1.229970] pci_scan_slot+0x40/0x12c
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[ 1.229972] pci_scan_child_bus_extend+0x58/0x34c
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[ 1.229974] pci_scan_bridge_extend+0x310/0x590
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[ 1.229976] pci_scan_child_bus_extend+0x210/0x34c
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[ 1.229978] pci_scan_root_bus_bridge+0x68/0xdc
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[ 1.229980] pci_host_probe+0x18/0xc4
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[ 1.229981] rockchip_pcie_probe+0x204/0x330
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[ 1.229984] platform_drv_probe+0x54/0xb0
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[ 1.229985] really_probe+0xe8/0x500
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[ 1.229987] driver_probe_device+0xd8/0xf0
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[ 1.229989] device_driver_attach+0xc0/0xcc
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[ 1.229991] __driver_attach+0xa4/0x170
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[ 1.229993] bus_for_each_dev+0x70/0xc0
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[ 1.229994] driver_attach+0x24/0x30
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[ 1.229996] bus_add_driver+0x140/0x234
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[ 1.229998] driver_register+0x78/0x130
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[ 1.230000] __platform_driver_register+0x4c/0x60
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[ 1.230002] rockchip_pcie_driver_init+0x1c/0x28
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[ 1.230004] do_one_initcall+0x54/0x1c0
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[ 1.230005] do_initcalls+0xf4/0x130
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[ 1.230007] kernel_init_freeable+0x144/0x19c
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[ 1.230009] kernel_init+0x14/0x11c
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[ 1.230011] ret_from_fork+0x10/0x34
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[ 1.230035] SMP: stopping secondary CPUs
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[ 1.230037] Kernel Offset: disabled
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[ 1.230039] CPU features: 0x0240022,2100200c
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[ 1.230041] Memory Limit: none
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---
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.../admin-guide/kernel-parameters.txt | 8 ++++++
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.../boot/dts/rockchip/rk3399-rockpro64.dtsi | 1 +
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drivers/pci/controller/pcie-rockchip-host.c | 25 +++++++++++++++++++
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drivers/pci/controller/pcie-rockchip.c | 6 +++++
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drivers/pci/controller/pcie-rockchip.h | 2 ++
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5 files changed, 42 insertions(+)
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diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
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index 44fde25bb221..941dc943eb84 100644
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--- a/Documentation/admin-guide/kernel-parameters.txt
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+++ b/Documentation/admin-guide/kernel-parameters.txt
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@@ -3816,6 +3816,14 @@
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nomsi Do not use MSI for native PCIe PME signaling (this makes
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all PCIe root ports use INTx for all services).
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+ pcie_rockchip_host.bus_scan_delay= [PCIE] Delay in ms before
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+ scanning PCIe bus in Rockchip PCIe host driver. Some PCIe
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+ cards seem to need delays that can be several hundred ms.
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+ If set to greater than or equal to 0 this parameter will
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+ override delay that can be set in device tree.
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+ Values less than 0 mean that this parameter is ignored.
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+ default=-1
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+
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pcmv= [HW,PCMCIA] BadgePAD 4
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pd_ignore_unused
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diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
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index 9705059523a6..632dac43a037 100644
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--- a/drivers/pci/controller/pcie-rockchip-host.c
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+++ b/drivers/pci/controller/pcie-rockchip-host.c
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@@ -24,6 +24,7 @@
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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+#include <linux/moduleparam.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_pci.h>
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@@ -39,6 +40,9 @@
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#include "../pci.h"
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#include "pcie-rockchip.h"
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+static int bus_scan_delay = -1;
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+module_param_named(bus_scan_delay, bus_scan_delay, int, S_IRUGO);
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+
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static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
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{
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u32 status;
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@@ -942,6 +946,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
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struct device *dev = &pdev->dev;
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struct pci_host_bridge *bridge;
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int err;
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+ u32 delay = 0;
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if (!dev->of_node)
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return -ENODEV;
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@@ -993,6 +998,26 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
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bridge->sysdata = rockchip;
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bridge->ops = &rockchip_pcie_ops;
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+ /* Checking if bus scan delay was given from command line and prefer
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+ * that over the value in device tree (which defaults to 0 if not set).
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+ */
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+ if (bus_scan_delay >= 0) {
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+ delay = bus_scan_delay;
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+ dev_info(dev, "wait %u ms (from command-line) before bus scan\n", delay);
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+ } else {
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+ delay = rockchip->bus_scan_delay;
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+ dev_info(dev, "wait %u ms (from device tree) before bus scan\n", delay);
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+ }
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+ /* Workaround for some devices crashing on pci_host_probe / pci_scan_root_bus_bridge
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+ * calls: sleep a bit before bus scan. Call trace gets to rockchip_pcie_rd_conf when
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+ * trying to read vendor id (pci_bus_generic_read_dev_vendor_id is in call stack)
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+ * before panicing. I have no idea why this works or what causes the panic. I just
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+ * found this hack by luck when trying to "make it break differently if possible".
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+ */
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+ if (delay > 0) {
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+ msleep(delay);
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+ }
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+
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err = pci_host_probe(bridge);
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if (err < 0)
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goto err_remove_irq_domain;
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diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
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index 904dec0d3a88..e6c97f9944ba 100644
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--- a/drivers/pci/controller/pcie-rockchip.c
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+++ b/drivers/pci/controller/pcie-rockchip.c
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@@ -149,6 +149,12 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
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return PTR_ERR(rockchip->clk_pcie_pm);
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}
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+ err = of_property_read_u32(node, "bus-scan-delay-ms", &rockchip->bus_scan_delay);
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+ if (err) {
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+ dev_info(dev, "no bus scan delay, default to 0 ms\n");
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+ rockchip->bus_scan_delay = 0;
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+ }
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+
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return 0;
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}
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EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt);
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diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
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index c7d0178fc8c2..52fd2108b704 100644
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--- a/drivers/pci/controller/pcie-rockchip.h
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+++ b/drivers/pci/controller/pcie-rockchip.h
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@@ -306,6 +306,8 @@ struct rockchip_pcie {
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phys_addr_t msg_bus_addr;
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bool is_rc;
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struct resource *mem_res;
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+ /* Bus scan delay is a workaround for some pcie devices causing crashes */
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+ u32 bus_scan_delay;
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};
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static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
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--
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2.29.2
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