2024-04-22 21:27:34 +00:00
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From 281ec38a96739db6a9282fa0c13cabd6cef258e1 Mon Sep 17 00:00:00 2001
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2024-03-04 19:01:07 +00:00
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From: Gabriel Krisman Bertazi <krisman@collabora.com>
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Date: Wed, 5 May 2021 22:12:17 -0400
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Subject: [PATCH 20/21] pinctrl-amd: Add quirk to timeout irq pin
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reconfiguration
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Since commit 37b635b47124 ("Add support for AMD SPI controller-1 (v2)"),
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which enabled the SPI bus on jupiter, the probe of cs35l41 hangs the
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entire kernel, because pinctrl-amd spins forever when attempting to
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reconfigure the cs35l41 irq pin with interrupts disabled and holding the
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spinlock of the irq controller. The infinite loop happens because of a
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board design issue (according to AMD), that tries to use a pin that
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can't even trigger the interruption that would otherwise signal the
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reconfiguratiion completion.
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This patch detects the condition and aborts the reconfiguration when the
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problem occurs, failing the probe of the device, but allowing the kernel
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to recover.
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With this patch, it should be safe to reenable CONFIG_SPI_AMD.
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Signed-off-by: Gabriel Krisman Bertazi <krisman@collabora.com>
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[Fwd-ported to v6.5]
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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---
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drivers/pinctrl/pinctrl-amd.c | 11 +++++++++--
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1 file changed, 9 insertions(+), 2 deletions(-)
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diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
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2024-04-22 21:27:34 +00:00
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index 7f66ec73199a..5763c37e5204 100644
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2024-03-04 19:01:07 +00:00
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--- a/drivers/pinctrl/pinctrl-amd.c
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+++ b/drivers/pinctrl/pinctrl-amd.c
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@@ -31,6 +31,7 @@
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/suspend.h>
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+#include <linux/delay.h>
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#include "core.h"
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#include "pinctrl-utils.h"
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@@ -484,6 +485,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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unsigned long flags;
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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+ int timeout = 100;
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raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
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@@ -553,11 +555,16 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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pin_reg_irq_en |= mask;
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pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
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writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
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- while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
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- continue;
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+ while (((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) && timeout--)
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+ udelay(100);
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+
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writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ if (timeout <= 0)
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+ printk("%s: applying Cirrus quirk after timeout when setting irq pin\n",
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+ __func__);
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+
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return ret;
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}
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--
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2.44.0
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