Instead of forcing bridges to implement empty callbacks make them all
optional.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
(cherry picked from commit c8a3b2ae07)
Change-Id: Id37cbb6114e69957dfd6b72c8bd7b66dcc6f0590
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Current drm bind/unbind sequence would cause some memory issues.
For example we should not cleanup iommu before cleanup mode config.
Reorder bind/unbind sequence, follow exynos drm.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
[seanpaul fixed spelling typo in commit subject]
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: http://patchwork.freedesktop.org/patch/msgid/1491481885-13775-11-git-send-email-jeffy.chen@rock-chips.com
(cherry picked from commit ccea91998c)
Change-Id: I8571a34419735f8b8a51666b31b91cbdb18250bd
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Fixes:
error: redefinition of 'rockchip_drm_backlight_update'
error: redefinition of 'of_rockchip_drm_sub_backlight_register'
Change-Id: I4eeebc6075387f720acec597cee765e2a1a83b7c
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
When begin connecting to PC in device mode, the driver will hold a
wake lock to prevent system from entering deep sleep. If it fails
to connect to PC or doesn't detect the vbus, the driver will suspend
usb phy and disable usb clk, and release the wake lock.
If unlock the wake lock first, system may enter deep sleep before
suspend usb phy and disable usb clk. Then wake up system by pull
out the usb cable, it may cause usb interrupt abnormal.
TEST=rk3126c connect the usb charger into the charging interface,
after the system entered deep sleep, pull out the usb cable with
the following log:
irq 42: nobody cared (try booting with the "irqpoll" option)
CPU: 0 PID: 146 Comm: charger Not tainted 3.10.104 #133
[<c0014088>] unwind_backtrace+0x0/0xe0
[<c00118cc>] show_stack+0x10/0x14
[<c00b0be0>] __report_bad_irq+0x28/0xb8
[<c00b0e68>] note_interrupt+0x138/0x1cc
[<c00aef88>] handle_irq_event_percpu+0x2c0/0x2f4
[<c00aeff8>] handle_irq_event+0x3c/0x5c
[<c00b1a20>] handle_fasteoi_irq+0xbc/0x124
[<c00ae764>] generic_handle_irq+0x20/0x30
[<c000e4cc>] handle_IRQ+0x64/0x8c
[<c000853c>] gic_handle_irq+0x38/0x5c
handlers:
[<c042b3ec>] dwc_otg_common_irq
[<c0438704>] dwc_otg_pcd_irq
[<c03fab48>] usb_hcd_irq
Disabling IRQ #42
Change-Id: Id36717ae68e02226255c1207aeded0bd6fb356cd
Signed-off-by: Feng Mingli <fml@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
PMIC should set "system-power-controller" in dts, otherwise
it couldn't be closed when system shutdown.
Change-Id: I3efd7efb1b1911621f21e8a741e2f6c2eebb60dc
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
dclk_ddr is supported on rk3368 vop, it would effect the
display quality on YUV420 mode.
Change-Id: Ia624a1f397e732d80d3908b8e712ae79d3ad7948
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Reported-by: Huacong Yang <will.yang@rock-chips.com>
From Rockchips fractional divider description:
3.1.9 Fractional divider usage
To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
fractional divider. Generally you must set that denominator is 20 times
larger than numerator to generate precise clock frequency. So the
fractional divider applies only to generate low frequency clock like
I2S, UART.
Therefore add a special approximation function that handles this
special requirement.
Change-Id: I80260392539da9d8cab79a5f6e37534d003bdbd1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Fractional dividers may have special requirements concerning numerator
and denominator selection that differ from just getting the best
approximation.
For example on Rockchip socs the denominator must be at least 20 times
larger than the numerator to generate precise clock frequencies.
Therefore add the ability to provide custom approximation functions.
Change-Id: I656a5851a3e2581b7f1b44bd67681ac00172873d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
to_clk_*(_hw) macros have been repeatedly defined in many places.
This patch moves all the to_clk_*(_hw) definitions in the common
clock framework to public header clk-provider.h, and drop the local
definitions.
Signed-off-by: Geliang Tang <geliangtang@163.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit 5fd9c05c84)
Change-Id: Ib0f9de8b9aeb30302b9d21e6668a35d18764517e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
So we can define reg offset according to TRM, otherwise it will make
us confused.
Change-Id: I1687542fcaf7ac4e6e78d863e8940f6604794407
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This reverts commit 9a9259a78c.
It seems schedtune_init_cgroups and schedtune_boostgroup_init
all call raw_spin_lock_init(&bg->lock), it is wrong.
Change-Id: Icbdfeaf81f4fb59fdcc02623ac5e26d41bd1e496
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
As gpu clock sources had been changed, the gpu frequencies also
should modifiy.
1. 297MHz is not support and replace it with 300MHz.
2. If enable tow vops, 500MHz is not support,
so remove it from the default table.
Change-Id: If2a653571f0222e895f7df825eeb8ae43ce99332
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add efuse_id for cpuinfo to get system serial number.
Change-Id: If197c2961611364a2cb94972c33171bea105c61b
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Fixes: 7f1f1ef ("drm/rockchip: vop: don't force enable post scale")
Change-Id: I57b44e7fe00bce7615ecde2e1f23837c74532c68
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Rockchip RGA is a separate 2D raster graphic acceleration unit. It
accelerates 2D graphics operations, such as point/line drawing, image
scaling, rotation, BitBLT, alpha blending and image blur/sharpness
The drvier is mostly based on s5p-g2d v4l2 m2m driver
And supports various operations from the rendering pipeline.
- copy
- fast solid color fill
- rotation
- flip
- alpha blending
The code in rga-hw.c is used to configure regs accroding to operations
The code in rga-buf.c is used to create (1-Level)mmu table for RGA
The tables is stored in a list, and be removed when buffer is cleanup
(am form https://patchwork.linuxtv.org/patch/42846/)
Change-Id: I3ddd885beb2388be2ef23fe75806719d1fda8695
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
At peresent, we don't have a control for Compositing and Blend.
All drivers are just doing copies while actually many hardwares
supports more functions.
So Adding V4L2 controls for Compositing and Blend, used for for
composting streams.
(am from https://patchwork.linuxtv.org/patch/42848/)
The values are based on porter duff operations.
Defined in below links.
https://developer.xamarin.com/api/type/Android.Graphics.PorterDuff+Mode/
Change-Id: I16245fc8389a433ebdcb228081a80daa48e8c539
Suggested-by: Nicolas Dufresne <nicolas@ndufresne.ca>
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
At present no component in linux depend on drm RGA, i'd like to remove it
Change-Id: I92e12e716e881463985fdf7c1430d47e34ba4155
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
At present no component in linux depend on drm RGA, i'd like to remove it
Change-Id: Ibf531641d3dd30bd87f83dbfe1fd06af2d3dffcb
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
we have to many rga drivers.. let's remove it to avoid misunderstanding
Change-Id: I807c9ff7dc967a00d30ccba5adc5d234e27b9d6a
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
