When I tested DP function on excavator, I found that commit 1bf7191033de
("BACKPORT: FROMLIST: phy: rockchip-typec: support variable phy config value"),
which change pll settings, but it does not work as expected on excavator board.
With this patch series, DP works well on excavator and roc.
Change-Id: I48fe0c51e322369d1aff352f4ebaf1096f264834
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
The innoslicon GF22FDX MIPI D-PHY integrates a MIPI 1.2
compatible PHY that supports up to 2.5Gbps high speed data
transmitter, plus a MIPI low-power low speed transceiver
that support data transfer in the bi-directional mode.
The IP supports the full specifications described in the
D-PHY spec 1.2. The D-PHY is built in with a standard
digital interface to talk to any third party host controller.
Change-Id: Iad7b9dc8fedaa1a5741830e9c02a593f544c2423
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
(am from https://patchwork.kernel.org/patch/10420473/)
Conflicts:
drivers/phy/phy-rockchip-typec.c
[phy-rockchip-typec.c is different path in upstream code]
BUG=b:72006974
TEST=DP can display on Dru
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1032713
Change-Id: I8a63307ad5cb690d819779662d70ae1c232842a5
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
we may use rockchip_phy_typec struct in other driver, so split
it to separate header.
Signed-off-by: Lin Huang <hl@rock-chips.com>
(am from https://patchwork.kernel.org/patch/10420467/)
Conflicts:
drivers/phy/phy-rockchip-typec.c
[phy-rockchip-typec.c is different path in upstream code]
BUG=b:72006974
TEST=DP display on Dru
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1069958
Change-Id: I709331d1577923be662660eb606f92b743903ba7
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This patch adds rk3368 otg-port phy configurations.
But actually, we don't use the otg phy configurations
for the time being, because we use dwc_otg_310 driver
for rk3368 otg controller, and this driver doesn't use
generic phy. This patch is useful if we switch to dwc2
driver for rk3368 otg in the feature.
Change-Id: Ibed3fde4ef64ad25e933ac4560f956b7c9f5c476
Signed-off-by: William Wu <william.wu@rock-chips.com>
If the usb otg work as host mode or work as peripheral mode
with vbus always on, the otg_sm_work won't be initialized,
so flush the otg_sm_work in rockchip_usb2phy_exit() will
casuse the following lock warning:
[<ffffff800808b1e0>] dump_backtrace+0x0/0x1ec
[<ffffff800808b3e0>] show_stack+0x14/0x1c
[<ffffff8008403f3c>] dump_stack+0xb8/0xf4
[<ffffff8008107f40>] __lock_acquire+0x670/0x1984
[<ffffff8008109a60>] lock_acquire+0x1a4/0x264
[<ffffff8008129d2c>] del_timer_sync+0x48/0xb8
[<ffffff80080c3c94>] flush_delayed_work+0x20/0x50
[<ffffff80084344ac>] rockchip_usb2phy_exit+0x48/0x58
[<ffffff8008432bc4>] phy_exit+0x64/0xb4
[<ffffff80086733b8>] dwc3_core_exit+0x44/0x98
[<ffffff80086736c4>] dwc3_remove+0x90/0xe4
[<ffffff80085a5a5c>] platform_drv_remove+0x28/0x48
[<ffffff80085a3d14>] __device_release_driver+0xac/0x114
[<ffffff80085a3da4>] device_release_driver+0x28/0x3c
[<ffffff80085a2f38>] bus_remove_device+0x110/0x128
[<ffffff80085a0404>] device_del+0x160/0x1f8
[<ffffff80085a5954>] platform_device_del+0x20/0x88
[<ffffff80085a59d0>] platform_device_unregister+0x14/0x28
[<ffffff80088820f4>] of_platform_device_destroy+0x54/0xa8
[<ffffff800859f790>] device_for_each_child+0x68/0x98
[<ffffff8008882084>] of_platform_depopulate+0x30/0x4c
[<ffffff8008680030>] dwc3_rockchip_probe+0x4d4/0x574
[<ffffff80085a5ad4>] platform_drv_probe+0x58/0xa4
[<ffffff80085a396c>] driver_probe_device+0x118/0x2b0
[<ffffff80085a3b70>] __driver_attach+0x6c/0x98
[<ffffff80085a29d0>] bus_for_each_dev+0x80/0xb0
[<ffffff80085a34a0>] driver_attach+0x20/0x28
[<ffffff80085a3038>] bus_add_driver+0xe8/0x1e4
[<ffffff80085a4ad4>] driver_register+0x94/0xe0
[<ffffff80085a5a2c>] __platform_driver_register+0x48/0x50
[<ffffff8009222224>] dwc3_rockchip_driver_init+0x18/0x20
[<ffffff80080839f4>] do_one_initcall+0x17c/0x198
[<ffffff80091f0e48>] kernel_init_freeable+0x1f8/0x2b0
[<ffffff8008c61810>] kernel_init+0x10/0xf8
[<ffffff80080832c0>] ret_from_fork+0x10/0x50
This patch only allows to flush the otg_sm_work when the usb
bvalid irq is valid.
Fixes: f6fac8b68a ("phy: rockchip: rockchip-inno-usb2: flush otg work when exit")
Change-Id: I4dbe34fa9a330f22abb24ccd625da33425a9f753
Signed-off-by: William Wu <william.wu@rock-chips.com>
Because USB OTG id irq is disabled during system suspend
and enabled after resume, so the usb2 phy doesn't notice
any id status change upon resume. It may cause two issues:
1. Plug in OTG cable and USB device when system enter
suspend, it will fail to detect the OTG cable and
USB device after resume.
2. Plug out OTG cable and USB device when system enter
suspend, and then connect USB to PC or USB charger
after resume, it will fail to detect USB charge type.
This patch restores the OTG id status before enter suspend，
and check the id status upon resume, and set the extcon
state and vbus if id status has changed.
Change-Id: Iaca14841cc287e7d82e1cffd64ff18bba86d3ba4
Signed-off-by: William Wu <william.wu@rock-chips.com>
The controller will be reinit when suspend and resume in device
mode if not connect to PC. And the U2PHY must be keep in power
on state during the init process. But The 'otg_sm_work' may be
schedule immediately and power off the U2PHY if system suspend
and resume between the delay time of schedule 'otg_sm_work', so
it will result in the error when init controller as below:
dwc2_core_reset() HANG! Soft Reset GRSTCTL=80000001
So flush the otg work in exit function to finish power control
of U2PHY.
Change-Id: I79c4b6a877196abd2f2201b2f984c9ea22e48fec
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Adding the following freq cfg in 8-bit and 10-bit color depth:
{
40000000, 65000000, 71000000, 83500000, 85750000,
88750000, 108000000, 119000000, 162000000
}
New freq has been validated by quantumdata 980.
For some freq which can't be got by only using integer freq div,
frac freq div is needed, Such as 88.75Mhz 10-bit. But The actual
freq is different from the target freq, We must try to narrow
the gap between them. RK322X only support integer freq div.
The VCO of pre-PLL must be more than 2Ghz, otherwise PLL may be
unlocked.
Change-Id: Icc978a31a51e330e12c6372c68f4e6b94e26cbda
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
For pixel clock is rounded by 1000Hz, the recalcated clock rate
of fractional frame rate mode, such 59.94/29.97/23.97Hz, is need
to take the 1000Hz rounding. Otherwise it will not find the pre-pll
settings when powering up phy.
Change-Id: I0f02bbede9314d57d97c539cd995eb0f67295cfd
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This patches fixes comparison between signed and unsigned values.
Change-Id: Ie417fdb8092463890a67bce7efa11f3ef20d5871
Signed-off-by: William Wu <william.wu@rock-chips.com>
When CONFIG_PM_SLEEP is disabled, we get a warning about
unused functions:
drivers/phy/rockchip/phy-rockchip-inno-usb2.c:1828:12: warning:
'rockchip_usb2phy_low_power_enable' defined but not used
Marking it as __maybe_unused avoids the warning without introducing
an ugly #ifdef.
Change-Id: I644b00eb2b30d9e4b63da46b7f387a7571b0f103
Signed-off-by: William Wu <william.wu@rock-chips.com>
On rockchip devices vbus is supplied by a separate power supply,
often through a regulator. Add support for describing the regulator
in device-tree following the same convention as several other usb phy's.
Change-Id: Ib13fa5d9c50cab3dd6711f2e7dd8489a4f06840b
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
(cherry picked from commit 9d685ed77b)
Most newer Rockchip SoCs provide the possibility to use a usb-phy
as passthrough for the debug uart (uart2), making it possible to
for example get console output without needing to open the device.
This patch adds an early_initcall to enable this functionality
conditionally via the commandline and also disables the corresponding
usb controller in the devicetree.
Currently only data for the rk3288 is provided, but at least the
rk3188 and arm64 rk3368 also provide this functionality and will be
enabled later.
On a spliced usb cable the signals are tx on white wire(D+) and
rx on green wire(D-).
The one caveat is that currently the reconfiguration of the phy
happens as early_initcall, as the code depends on the unflattened
devicetree being available. Everything is fine if only a regular
console is active as the console-replay will happen after the
reconfiguation. But with earlycon active output up to smp-init
currently will get lost.
The phy is an optional property for the connected dwc2 controller,
so we still provide the phy device but fail all phy-ops with -EBUSY
to make sure the dwc2 does not try to transmit anything on the
repurposed phy.
Change-Id: Ia9eed5b2b83d88fbeb7aabced689b21f4ea0ca69
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
(cherry picked from commit 605df8af33)
Deleted phy operations for rk336x and rk3399, because they
use Inno USB2.0 PHY, and we have added a new phy driver for
them. This can make our phy driver to stay closer to upstream.
Change-Id: I3b70cd78564c6a9873be88fc19954a8c2f95dd98
Signed-off-by: William Wu <william.wu@rock-chips.com>
instead of defining all functions as static inlines,
let's move them to udc-core and export them with
EXPORT_SYMBOL_GPL, that way we can make sure that
only GPL drivers will use them.
As a side effect, it'll be nicer to add tracepoints
to the gadget API.
While at that, also fix Kconfig dependencies to
avoid randconfig build failures.
Change-Id: I3fcc99c0730608076cfa8624908e58b7ee6f1bef
Acked-By: Sebastian Reichel <sre@kernel.org>
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
(cherry-picked from commit 5a8d651a2b)
Setting inno phy config table in dts. According to tmds clock range, phy
config data can be chosen. We can also filter some video modes which
tmds clock out of range we set.
Change-Id: I666c825921877fe2cdf45c2ccd1415815a4b7715
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Pre PLL pclk_dividera value range is from 1 to 31, but the default
value of register 0xe0 on 3229 is zero. To avoid div zero error,
we take the divider value as one.
[<c0110070>] (unwind_backtrace) from [<c010bcbc>] (show_stack+0x20/0x24)
[<c010bcbc>] (show_stack) from [<c040f56c>] (dump_stack+0x80/0xa0)
[<c040f56c>] (dump_stack) from [<c010bbf4>] (__div0+0x20/0x28)
[<c010bbf4>] (__div0) from [<c040d62c>] (Ldiv0_64+0x8/0x18)
[<c040d62c>] (Ldiv0_64) from [<c043f310>] (inno_hdmi_rk3228_phy_pll_recalc_rate+0x104/0x114)
[<c043f310>] (inno_hdmi_rk3228_phy_pll_recalc_rate) from [<c043efac>] (inno_hdmi_phy_clk_recalc_rate+0x30/0x3c)
[<c043efac>] (inno_hdmi_phy_clk_recalc_rate) from [<c0980c00>] (clk_register+0x438/0x64c)
[<c0980c00>] (clk_register) from [<c0980e68>] (devm_clk_register+0x54/0x94)
[<c0980e68>] (devm_clk_register) from [<c0440028>] (inno_hdmi_phy_probe+0x24c/0x378)
[<c0440028>] (inno_hdmi_phy_probe) from [<c0566424>] (platform_drv_probe+0x60/0xac)
[<c0566424>] (platform_drv_probe) from [<c05645bc>] (driver_probe_device+0x120/0x2a8)
[<c05645bc>] (driver_probe_device) from [<c05647bc>] (__driver_attach+0x78/0x9c)
[<c05647bc>] (__driver_attach) from [<c0562a28>] (bus_for_each_dev+0x84/0x98)
[<c0562a28>] (bus_for_each_dev) from [<c05640d0>] (driver_attach+0x28/0x30)
[<c05640d0>] (driver_attach) from [<c0563c5c>] (bus_add_driver+0xdc/0x1f8)
[<c0563c5c>] (bus_add_driver) from [<c056533c>] (driver_register+0xac/0xf0)
[<c056533c>] (driver_register) from [<c0566364>] (__platform_driver_register+0x40/0x54)
[<c0566364>] (__platform_driver_register) from [<c122af4c>] (inno_hdmi_phy_driver_init+0x18/0x20)
[<c122af4c>] (inno_hdmi_phy_driver_init) from [<c0101ad4>] (do_one_initcall+0x114/0x1c8)
[<c0101ad4>] (do_one_initcall) from [<c1200ef0>] (kernel_init_freeable+0x1ac/0x280)
[<c1200ef0>] (kernel_init_freeable) from [<c0c5e4c8>] (kernel_init+0x18/0x11c)
[<c0c5e4c8>] (kernel_init) from [<c0107550>] (ret_from_fork+0x14/0x24)
Change-Id: Ib61fbd87547d3316e9ed5b564e291b6c15d93cdd
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This patch fix the following clang warning:
[clang]drivers/phy/rockchip/phy-rockchip-inno-usb2.c:1255:3:
warning: Value stored to 'delay' is never read
Change-Id: I8c70975e1bc2b24a78d0934ccefc9d67fe3a5da9
Signed-off-by: William Wu <william.wu@rock-chips.com>
Reduce the otg schedule delay time from 6s to 1s to do
the first time usb charger detection earlier when power
on system with usb cable connect to PC USB. Because the
usb connection willed be disconnectted during usb charger
detection.
And the patch also makes the phy detect the usb disconnetion
more quickly after usb cable plug out.
Change-Id: I9b55317ab3592f517fdf590fea85c4ed403bbd8d
Signed-off-by: William Wu <william.wu@rock-chips.com>
Open pre-emphasize in non-chirp state for rk322x USB
PHY0 otg port to increase HS slew rate.
Change-Id: Ia565746286a750a251619a83cbbead99c0ddecbd
Signed-off-by: William Wu <william.wu@rock-chips.com>
RK3328 hdmi phy introduces an irq to detect ESD status
of TMDS link. If irq is triggered, it is need to reset
pdata_en signal.
Change-Id: I6190d57d3b4f7c4f6791e1204cb9d8a99da988e2
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Make u2phy enter low power mode when suspend. If config the DT of
u2phy port with "rockchip,low-power-mode" property, the port will
be config to lower power state when suspend.
Bvalid irq and linestate irq will be disabled in this mode.
Change-Id: Ie7d40a9a181b0622b1f8d062a741661548cabd59
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
This patch fix the following clang warning:
[clang] drivers/phy/rockchip/phy-rockchip-inno-usb2.c:1458:2:
warning: 3rd function call argument is an uninitialized value
Change-Id: Ia4a556da346323e5bc081ff1bbf267911fcdc645
Signed-off-by: William Wu <william.wu@rock-chips.com>
Open pre-emphasize in non-chirp state for rk3308 and
rk3328 usb otg and host ports to increase HS slew rate.
Change-Id: I16435d67b9994cef0fd5e6edbae00c41cc02c48b
Signed-off-by: William Wu <william.wu@rock-chips.com>
The phy flag shift offset is defined in dts file, there is
no need to or the shift in the phy driver.
Change-Id: I13a33a536dabea68adf07a73cc2d13439719c589
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
On 32bit platform, vco may be out of range. The variable type
of vco needs to be set to u64.
Change-Id: I2f6b967278986bb77bf74c7a11794fc4d73645db
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
On some chip, HDMI post PLL is not stable when it's vco is 1080M,
but it work ok when vco is 270M. We use a efuse bit to distinguish
these chip.
Change-Id: I143363d67e60747ee52d405edace3ec611de3e6e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Inno hdmi phy post pll is enabled by default on rk3228, it's need to
manual power down post pll if uboot logo is not shown.
Change-Id: I7ed4de2eae2d723f390dae44281281b9e81f4e1d
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
we can power off the bandgap to reduce power consumption.
Change-Id: I7959e6f1d38a6abca70d6d904264668a19ace920
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This change adds usb-phy support for rk3308 SoC and amend related
phy Documentation.
Change-Id: I953af94fb4d55d79ae1cba624a04fb4b84e019f6
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
for rk322x power down post-PLL must to both set rege0[5]=0 and set
pre pll pre-PLL unlock. So power down pre-PLL before post-PLL power
down
Change-Id: If0eb325b10bb6eb117b0a61d5852e9aae9d92ba6
Signed-off-by: Huicong Xu <xhc@rock-chips.com>
Turn off differential receiver in suspend mode for RK3328 and
PX30 to save power.
The effect of turn off differential receiver on electricity:
USB20_AVDD_1V8: 0.73mA (turn on)
USB20_AVDD_1V8: 0.03mA (tunn off)
Change-Id: I0650d6d4b712a3692eed2564dda36d41b7956bb9
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
we can power off the da_pwrok to reduce power consumption.
Change-Id: Ie08af149e74408e57750a186cf16d5adf4b3cfb7
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
The RK3328 HDMI PHY adds a method to detect the TMDS Data sync
enable status. The counter length is defined as:
Fref * 495 * 4 / Ftmdsclk
If sync enable counter match the counter length, the sync status
defined in reg0xdd will be set to true.
Change-Id: Ib6a58cb50127e84399011cb398e7fa36f72b3a45
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map, since
it does not depend on device tree despite the current name. This
will enforce a consistent naming in pinctr-utils.c and will make
it clear it can be called from outside device tree (e.g. from
ACPI handling code).
Change-Id: I442cea04967997ed29d6e7a3cfe35f2ec2e9c95f
Signed-off-by: Irina Tirdea <irina.tirdea@intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit d32f7fd3bb)
This patch uses a fixed-regulator instead of GPIO pin for
usb vbus power. It doesn't fix any issue, but it makes more
sense to convert the GPIO code into a fixed-regulator.
Change-Id: I76fb8dc5c8cfdba24ccb3fc24f14850defb83b2e
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch uses a fixed-regulator instead of GPIO pin for
usb vbus power. It doesn't fix any issue, but it makes more
sense to convert the GPIO code into a fixed-regulator.
Change-Id: I7196a9cd592dbb3fab3ef8b9e99babc613a42869
Signed-off-by: William Wu <william.wu@rock-chips.com>
For 3328, inno hdmi phy post pll is enabled by default, it's need to
manual power down post pll if uboot logo is not shown.
Change-Id: Ia175ff0aad006be950b8bc13e1cf2ecb4f00e04c
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
If we power off the SoC LOGIC rail in S3, we can find that the
Type-C PHY can't initialize correctly after system resume with
error log looked like this:
phy phy-ff800000.phy.9: phy poweron failed --> -110
dwc3 fe900000.dwc3: failed to initialize core
dwc3: probe of fe900000.dwc3 failed with error -110
It's because that the field of usb3tousb2 in GRF_USB3PHY0/1_CON0
is reset to 1 after power off the SoC LOGIC, which means that the
pipe interface is blocked between Tpye-C PHY and usb3 controller.
And after system resume, the rockchip_usb3_phy_power_on() will call
the tcphy_cfg_usb3_to_usb2_only() to clear the usb3tousb2 bit and
enable the usb3 host again. If we clear the usb3tousb2 bit before
pipe ready, it may cause waiting for pipe ready timeout.
Note that the RK3399 TRM suggests that we should keep the whole usb3
controller in reset for the duration of the Type-C PHY initialization.
However, it's hard to assert the reset in the current framework of
reset. And according to the TRM, it doesn't require that we should
clear the usb3tousb2 bit before pipe ready. So let's enable the usb3
host after pipe ready to avoid the Type-C PHY initialization failure.
BUG=b:62644399, chromium:783464
TEST=run suspend_stess_test on Scarlet, usb device can work after resume
Change-Id: Ie597cbe35568c390460aa2fdbad0e66c6104c8d2
Reviewed-on: https://chromium-review.googlesource.com/896908
Commit-Ready: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: William Wu <william.wu@rock-chips.com>
If hdmi phy had been set in uboot, it's need to set power_count
to 1 to match actutal phy status.
This patch use regc8 bit[7:6] to detect phy is set in uboot or not.
After phy power up, value will be zero which is different to its
default value(2'b11).
Change-Id: I6e5deea1d5a0973788c39a200d5c5a0f6a14bdd2
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
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Merge tag 'lsk-v4.4-18.02-android' of git://git.linaro.org/kernel/linux-linaro-stable.git
LSK 18.02 v4.4-android
* tag 'lsk-v4.4-18.02-android': (131 commits)
Linux 4.4.114
nfsd: auth: Fix gid sorting when rootsquash enabled
net: tcp: close sock if net namespace is exiting
flow_dissector: properly cap thoff field
ipv4: Make neigh lookup keys for loopback/point-to-point devices be INADDR_ANY
net: Allow neigh contructor functions ability to modify the primary_key
vmxnet3: repair memory leak
sctp: return error if the asoc has been peeled off in sctp_wait_for_sndbuf
sctp: do not allow the v4 socket to bind a v4mapped v6 address
r8169: fix memory corruption on retrieval of hardware statistics.
pppoe: take ->needed_headroom of lower device into account on xmit
net: qdisc_pkt_len_init() should be more robust
tcp: __tcp_hdrlen() helper
net: igmp: fix source address check for IGMPv3 reports
lan78xx: Fix failure in USB Full Speed
ipv6: ip6_make_skb() needs to clear cork.base.dst
ipv6: fix udpv6 sendmsg crash caused by too small MTU
ipv6: Fix getsockopt() for sockets with default IPV6_AUTOFLOWLABEL
dccp: don't restart ccid2_hc_tx_rto_expire() if sk in closed state
hrtimer: Reset hrtimer cpu base proper on CPU hotplug
...
In current code, the pre-emphasize in eop state and chirp state are
disabled only if we add “rockchip,u2phy-tuning” property in RK3399 dts,
But we find that if we enable the pre-emphasize of sop/eop/chirp state
for rk3399 by default, it will cause usb2 compliance test item - EL_8
and EL_9 failure, so disable the pre-emphasize of sop/eop/chirp state
by default. And this can also help to avoid mis-trigger the disconnect
detection or high-speed handshake failure.
Change-Id: I5ceac9c88de4cdae5af904e973124c194f7718f6
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
avoid out of value range calculate catmdsclk when 4k10bit and set
scdc high tmds clock ratio when mtmdsclock is more than 340000000
Change-Id: I8aed4c99813e43c69526f3918d5e7024879d3288
Signed-off-by: Huicong Xu <xhc@rock-chips.com>
