forge/linux-uconsole
1
0
Fork 0
Code Issues 1 Pull requests Projects Releases Packages Wiki Activity Actions

ARM: dts: rk312x: add power node to support power domain

Browse source 
add power and qos node to support power domain on/off.

Change-Id: I35088bfa7be407d7c627e32a84f2aafd1853e2df
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2017-10-19 11:08:23 +08:00 • committed by Tao Huang
commit d1d6ca3c94
1 changed files with 86 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

86
arch/arm/boot/dts/rk312x.dtsi
View file

@ -42,6 +42,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rk3128-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/clock/rk3128-cru.h>
#include <dt-bindings/display/media-bus-format.h>
@ -242,6 +243,7 @@
clocks = <&cru ACLK_GPU>;
#cooling-cells = <2>; /* min followed by max */
clock-names = "clk_mali";
power-domains = <&power RK3128_PD_GPU>;
operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
@ -279,6 +281,55 @@
#address-cells = <1>;
#size-cells = <1>;
power: power-controller {
compatible = "rockchip,rk3128-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pd_vio@RK3128_PD_VIO {
reg = <RK3128_PD_VIO>;
clocks = <&cru ACLK_RGA>,
<&cru ACLK_LCDC0>,
<&cru ACLK_IEP>,
<&cru ACLK_CIF>,
<&cru ACLK_VIO0>,
<&cru ACLK_VIO1>,
<&cru DCLK_VOP>,
<&cru DCLK_EBC>,
<&cru HCLK_RGA>,
<&cru HCLK_VIO>,
<&cru HCLK_EBC>,
<&cru HCLK_LCDC0>,
<&cru HCLK_IEP>,
<&cru HCLK_CIF>,
<&cru HCLK_VIO_H2P>,
<&cru PCLK_MIPI>,
<&cru PCLK_MIPIPHY>,
<&cru SCLK_VOP>;
pm_qos = <&qos_rga>,
<&qos_ebc>,
<&qos_iep>,
<&qos_lcdc0>,
<&qos_vip0>;
};
pd_video@RK3128_PD_VIDEO {
reg = <RK3128_PD_VIDEO>;
clocks = <&cru ACLK_VEPU>,
<&cru ACLK_VDPU>,
<&cru HCLK_VEPU>,
<&cru HCLK_VDPU>,
<&cru SCLK_HEVC_CORE>;
pm_qos = <&qos_vpu>;
};
pd_gpu@RK3128_PD_GPU {
reg = <RK3128_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
};
};
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x38>;
@ -365,6 +416,41 @@
};
};
qos_gpu: qos@1012d000 {
compatible = "syscon";
reg = <0x1012d000 0x20>;
};
qos_vpu: qos@1012e000 {
compatible = "syscon";
reg = <0x1012e000 0x20>;
};
qos_rga: qos@1012f000 {
compatible = "syscon";
reg = <0x1012f000 0x20>;
};
qos_ebc: qos@1012f080 {
compatible = "syscon";
reg = <0x1012f080 0x20>;
};
qos_iep: qos@1012f100 {
compatible = "syscon";
reg = <0x1012f100 0x20>;
};
qos_lcdc0: qos@1012f180 {
compatible = "syscon";
reg = <0x1012f180 0x20>;
};
qos_vip0: qos@1012f200 {
compatible = "syscon";
reg = <0x1012f200 0x20>;
};
gic: interrupt-controller@10139000 {
compatible = "arm,cortex-a7-gic";
interrupt-controller;