diff --git a/arch/arm/boot/dts/rk312x.dtsi b/arch/arm/boot/dts/rk312x.dtsi index dcc1f1453c58..f2daf87e5ef6 100644 --- a/arch/arm/boot/dts/rk312x.dtsi +++ b/arch/arm/boot/dts/rk312x.dtsi @@ -42,6 +42,7 @@ #include #include #include +#include #include #include #include @@ -242,6 +243,7 @@ clocks = <&cru ACLK_GPU>; #cooling-cells = <2>; /* min followed by max */ clock-names = "clk_mali"; + power-domains = <&power RK3128_PD_GPU>; operating-points-v2 = <&gpu_opp_table>; status = "disabled"; @@ -279,6 +281,55 @@ #address-cells = <1>; #size-cells = <1>; + power: power-controller { + compatible = "rockchip,rk3128-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pd_vio@RK3128_PD_VIO { + reg = ; + clocks = <&cru ACLK_RGA>, + <&cru ACLK_LCDC0>, + <&cru ACLK_IEP>, + <&cru ACLK_CIF>, + <&cru ACLK_VIO0>, + <&cru ACLK_VIO1>, + <&cru DCLK_VOP>, + <&cru DCLK_EBC>, + <&cru HCLK_RGA>, + <&cru HCLK_VIO>, + <&cru HCLK_EBC>, + <&cru HCLK_LCDC0>, + <&cru HCLK_IEP>, + <&cru HCLK_CIF>, + <&cru HCLK_VIO_H2P>, + <&cru PCLK_MIPI>, + <&cru PCLK_MIPIPHY>, + <&cru SCLK_VOP>; + pm_qos = <&qos_rga>, + <&qos_ebc>, + <&qos_iep>, + <&qos_lcdc0>, + <&qos_vip0>; + }; + pd_video@RK3128_PD_VIDEO { + reg = ; + clocks = <&cru ACLK_VEPU>, + <&cru ACLK_VDPU>, + <&cru HCLK_VEPU>, + <&cru HCLK_VDPU>, + <&cru SCLK_HEVC_CORE>; + pm_qos = <&qos_vpu>; + }; + pd_gpu@RK3128_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + }; + }; + reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x38>; @@ -365,6 +416,41 @@ }; }; + qos_gpu: qos@1012d000 { + compatible = "syscon"; + reg = <0x1012d000 0x20>; + }; + + qos_vpu: qos@1012e000 { + compatible = "syscon"; + reg = <0x1012e000 0x20>; + }; + + qos_rga: qos@1012f000 { + compatible = "syscon"; + reg = <0x1012f000 0x20>; + }; + + qos_ebc: qos@1012f080 { + compatible = "syscon"; + reg = <0x1012f080 0x20>; + }; + + qos_iep: qos@1012f100 { + compatible = "syscon"; + reg = <0x1012f100 0x20>; + }; + + qos_lcdc0: qos@1012f180 { + compatible = "syscon"; + reg = <0x1012f180 0x20>; + }; + + qos_vip0: qos@1012f200 { + compatible = "syscon"; + reg = <0x1012f200 0x20>; + }; + gic: interrupt-controller@10139000 { compatible = "arm,cortex-a7-gic"; interrupt-controller;