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PCI: rockchip: dw: Validate phy mode in suspend

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Some PCIe root port uses combophy but combo phy can be used by
other type of controllers. If someone enable phy for both of two
controllers, it should break the s2r and hard to debug. Validate
this kind of bug and cast an error like this:

[   10.698225] naneng-combphy fee20000.phy: expected mode is PCIe, but current mode is USB3
[   10.698232] rk-pcie fe180000.pcie: PHY is reused by other controller, check the dts!
[   10.698244] PM: dpm_run_callback(): rockchip_dw_pcie_suspend+0x0/0x410 returns -22
[   10.698266] PM: Device fe180000.pcie failed to suspend async: error -22
[   10.902134] PM: pm_system_irq_wakeup: 166 triggered fsc_interrupt_int_n

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Icc65c9d19ef2bcb54bfb3665d4c012f8ac0e710e
This commit is contained in:
Shawn Lin 2023-11-22 10:40:14 +08:00 • committed by Tao Huang
commit 5dc8f0d04b
1 changed files with 7 additions and 0 deletions
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7
drivers/pci/controller/dwc/pcie-dw-rockchip.c
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@ -8,6 +8,7 @@
* Author: Simon Xue <xxm@rock-chips.com>
*/
#include <dt-bindings/phy/phy.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/fs.h>
@ -2335,6 +2336,12 @@ static int __maybe_unused rockchip_dw_pcie_suspend(struct device *dev)
no_l2:
rk_pcie_disable_ltssm(rk_pcie);
ret = phy_validate(rk_pcie->phy, PHY_TYPE_PCIE, 0, NULL);
if (ret && ret != -EOPNOTSUPP) {
dev_err(dev, "PHY is reused by other controller, check the dts!\n");
return ret;
}
/* make sure assert phy success */
usleep_range(200, 300);