 f63fcc90a3
			
		
	
	
	f63fcc90a3
	
	
	
		
			
			cppcheck detected following error [clk-master.c:245]: (error) Memory leak: characteristics The original code forgot to free characteristics when irq_of_parse_and_map() failed. Signed-off-by: Masanari Iida <standby24x7@gmail.com> Acked-by Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
		
			
				
	
	
		
			270 lines
		
	
	
	
		
			6.6 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			270 lines
		
	
	
	
		
			6.6 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License as published by
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|  * the Free Software Foundation; either version 2 of the License, or
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|  * (at your option) any later version.
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|  *
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|  */
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| 
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| #include <linux/clk-provider.h>
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| #include <linux/clkdev.h>
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| #include <linux/clk/at91_pmc.h>
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| #include <linux/of.h>
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| #include <linux/of_address.h>
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| #include <linux/of_irq.h>
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| #include <linux/io.h>
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| #include <linux/wait.h>
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| #include <linux/sched.h>
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| #include <linux/interrupt.h>
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| #include <linux/irq.h>
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| 
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| #include "pmc.h"
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| 
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| #define MASTER_SOURCE_MAX	4
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| 
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| #define MASTER_PRES_MASK	0x7
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| #define MASTER_PRES_MAX		MASTER_PRES_MASK
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| #define MASTER_DIV_SHIFT	8
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| #define MASTER_DIV_MASK		0x3
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| 
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| struct clk_master_characteristics {
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| 	struct clk_range output;
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| 	u32 divisors[4];
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| 	u8 have_div3_pres;
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| };
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| 
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| struct clk_master_layout {
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| 	u32 mask;
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| 	u8 pres_shift;
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| };
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| 
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| #define to_clk_master(hw) container_of(hw, struct clk_master, hw)
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| 
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| struct clk_master {
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| 	struct clk_hw hw;
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| 	struct at91_pmc *pmc;
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| 	unsigned int irq;
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| 	wait_queue_head_t wait;
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| 	const struct clk_master_layout *layout;
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| 	const struct clk_master_characteristics *characteristics;
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| };
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| 
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| static irqreturn_t clk_master_irq_handler(int irq, void *dev_id)
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| {
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| 	struct clk_master *master = (struct clk_master *)dev_id;
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| 
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| 	wake_up(&master->wait);
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| 	disable_irq_nosync(master->irq);
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| 
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| 	return IRQ_HANDLED;
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| }
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| static int clk_master_prepare(struct clk_hw *hw)
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| {
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| 	struct clk_master *master = to_clk_master(hw);
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| 	struct at91_pmc *pmc = master->pmc;
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| 
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| 	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY)) {
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| 		enable_irq(master->irq);
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| 		wait_event(master->wait,
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| 			   pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY);
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| 	}
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| 
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| 	return 0;
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| }
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| 
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| static int clk_master_is_prepared(struct clk_hw *hw)
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| {
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| 	struct clk_master *master = to_clk_master(hw);
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| 
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| 	return !!(pmc_read(master->pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY);
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| }
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| 
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| static unsigned long clk_master_recalc_rate(struct clk_hw *hw,
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| 					    unsigned long parent_rate)
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| {
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| 	u8 pres;
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| 	u8 div;
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| 	unsigned long rate = parent_rate;
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| 	struct clk_master *master = to_clk_master(hw);
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| 	struct at91_pmc *pmc = master->pmc;
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| 	const struct clk_master_layout *layout = master->layout;
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| 	const struct clk_master_characteristics *characteristics =
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| 						master->characteristics;
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| 	u32 tmp;
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| 
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| 	pmc_lock(pmc);
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| 	tmp = pmc_read(pmc, AT91_PMC_MCKR) & layout->mask;
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| 	pmc_unlock(pmc);
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| 
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| 	pres = (tmp >> layout->pres_shift) & MASTER_PRES_MASK;
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| 	div = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
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| 
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| 	if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX)
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| 		rate /= 3;
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| 	else
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| 		rate >>= pres;
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| 
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| 	rate /= characteristics->divisors[div];
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| 
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| 	if (rate < characteristics->output.min)
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| 		pr_warn("master clk is underclocked");
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| 	else if (rate > characteristics->output.max)
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| 		pr_warn("master clk is overclocked");
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| 
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| 	return rate;
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| }
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| 
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| static u8 clk_master_get_parent(struct clk_hw *hw)
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| {
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| 	struct clk_master *master = to_clk_master(hw);
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| 	struct at91_pmc *pmc = master->pmc;
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| 
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| 	return pmc_read(pmc, AT91_PMC_MCKR) & AT91_PMC_CSS;
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| }
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| 
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| static const struct clk_ops master_ops = {
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| 	.prepare = clk_master_prepare,
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| 	.is_prepared = clk_master_is_prepared,
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| 	.recalc_rate = clk_master_recalc_rate,
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| 	.get_parent = clk_master_get_parent,
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| };
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| 
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| static struct clk * __init
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| at91_clk_register_master(struct at91_pmc *pmc, unsigned int irq,
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| 		const char *name, int num_parents,
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| 		const char **parent_names,
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| 		const struct clk_master_layout *layout,
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| 		const struct clk_master_characteristics *characteristics)
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| {
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| 	int ret;
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| 	struct clk_master *master;
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| 	struct clk *clk = NULL;
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| 	struct clk_init_data init;
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| 
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| 	if (!pmc || !irq || !name || !num_parents || !parent_names)
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| 		return ERR_PTR(-EINVAL);
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| 
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| 	master = kzalloc(sizeof(*master), GFP_KERNEL);
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| 	if (!master)
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| 		return ERR_PTR(-ENOMEM);
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| 
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| 	init.name = name;
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| 	init.ops = &master_ops;
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| 	init.parent_names = parent_names;
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| 	init.num_parents = num_parents;
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| 	init.flags = 0;
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| 
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| 	master->hw.init = &init;
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| 	master->layout = layout;
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| 	master->characteristics = characteristics;
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| 	master->pmc = pmc;
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| 	master->irq = irq;
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| 	init_waitqueue_head(&master->wait);
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| 	irq_set_status_flags(master->irq, IRQ_NOAUTOEN);
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| 	ret = request_irq(master->irq, clk_master_irq_handler,
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| 			  IRQF_TRIGGER_HIGH, "clk-master", master);
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| 	if (ret)
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| 		return ERR_PTR(ret);
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| 
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| 	clk = clk_register(NULL, &master->hw);
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| 	if (IS_ERR(clk))
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| 		kfree(master);
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| 
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| 	return clk;
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| }
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| 
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| 
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| static const struct clk_master_layout at91rm9200_master_layout = {
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| 	.mask = 0x31F,
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| 	.pres_shift = 2,
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| };
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| 
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| static const struct clk_master_layout at91sam9x5_master_layout = {
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| 	.mask = 0x373,
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| 	.pres_shift = 4,
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| };
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| 
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| 
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| static struct clk_master_characteristics * __init
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| of_at91_clk_master_get_characteristics(struct device_node *np)
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| {
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| 	struct clk_master_characteristics *characteristics;
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| 
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| 	characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
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| 	if (!characteristics)
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| 		return NULL;
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| 
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| 	if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output))
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| 		goto out_free_characteristics;
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| 
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| 	of_property_read_u32_array(np, "atmel,clk-divisors",
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| 				   characteristics->divisors, 4);
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| 
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| 	characteristics->have_div3_pres =
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| 		of_property_read_bool(np, "atmel,master-clk-have-div3-pres");
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| 
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| 	return characteristics;
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| 
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| out_free_characteristics:
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| 	kfree(characteristics);
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| 	return NULL;
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| }
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| 
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| static void __init
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| of_at91_clk_master_setup(struct device_node *np, struct at91_pmc *pmc,
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| 			 const struct clk_master_layout *layout)
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| {
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| 	struct clk *clk;
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| 	int num_parents;
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| 	int i;
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| 	unsigned int irq;
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| 	const char *parent_names[MASTER_SOURCE_MAX];
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| 	const char *name = np->name;
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| 	struct clk_master_characteristics *characteristics;
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| 
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| 	num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
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| 	if (num_parents <= 0 || num_parents > MASTER_SOURCE_MAX)
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| 		return;
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| 
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| 	for (i = 0; i < num_parents; ++i) {
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| 		parent_names[i] = of_clk_get_parent_name(np, i);
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| 		if (!parent_names[i])
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| 			return;
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| 	}
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| 
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| 	of_property_read_string(np, "clock-output-names", &name);
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| 
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| 	characteristics = of_at91_clk_master_get_characteristics(np);
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| 	if (!characteristics)
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| 		return;
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| 
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| 	irq = irq_of_parse_and_map(np, 0);
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| 	if (!irq)
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| 		goto out_free_characteristics;
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| 
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| 	clk = at91_clk_register_master(pmc, irq, name, num_parents,
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| 				       parent_names, layout,
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| 				       characteristics);
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| 	if (IS_ERR(clk))
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| 		goto out_free_characteristics;
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| 
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| 	of_clk_add_provider(np, of_clk_src_simple_get, clk);
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| 	return;
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| 
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| out_free_characteristics:
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| 	kfree(characteristics);
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| }
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| 
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| void __init of_at91rm9200_clk_master_setup(struct device_node *np,
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| 					   struct at91_pmc *pmc)
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| {
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| 	of_at91_clk_master_setup(np, pmc, &at91rm9200_master_layout);
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| }
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| 
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| void __init of_at91sam9x5_clk_master_setup(struct device_node *np,
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| 					   struct at91_pmc *pmc)
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| {
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| 	of_at91_clk_master_setup(np, pmc, &at91sam9x5_master_layout);
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| }
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