 8c47eaa766
			
		
	
	
	8c47eaa766
	
	
	
		
			
			Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
		
			
				
	
	
		
			74 lines
		
	
	
	
		
			2.2 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			74 lines
		
	
	
	
		
			2.2 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*******************************************************************************
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| 
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|   Intel 10 Gigabit PCI Express Linux driver
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|   Copyright(c) 1999 - 2010 Intel Corporation.
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| 
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|   This program is free software; you can redistribute it and/or modify it
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|   under the terms and conditions of the GNU General Public License,
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|   version 2, as published by the Free Software Foundation.
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| 
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|   This program is distributed in the hope it will be useful, but WITHOUT
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|   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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|   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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|   more details.
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| 
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|   You should have received a copy of the GNU General Public License along with
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|   this program; if not, write to the Free Software Foundation, Inc.,
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|   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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| 
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|   The full GNU General Public License is included in this distribution in
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|   the file called "COPYING".
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| 
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|   Contact Information:
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|   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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|   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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| 
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| *******************************************************************************/
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| 
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| #ifndef _IXGBE_FCOE_H
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| #define _IXGBE_FCOE_H
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| 
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| #include <scsi/fc/fc_fs.h>
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| #include <scsi/fc/fc_fcoe.h>
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| 
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| /* shift bits within STAT fo FCSTAT */
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| #define IXGBE_RXDADV_FCSTAT_SHIFT	4
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| 
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| /* ddp user buffer */
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| #define IXGBE_BUFFCNT_MAX	256	/* 8 bits bufcnt */
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| #define IXGBE_FCPTR_ALIGN	16
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| #define IXGBE_FCPTR_MAX	(IXGBE_BUFFCNT_MAX * sizeof(dma_addr_t))
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| #define IXGBE_FCBUFF_4KB	0x0
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| #define IXGBE_FCBUFF_8KB	0x1
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| #define IXGBE_FCBUFF_16KB	0x2
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| #define IXGBE_FCBUFF_64KB	0x3
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| #define IXGBE_FCBUFF_MAX	65536	/* 64KB max */
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| #define IXGBE_FCBUFF_MIN	4096	/* 4KB min */
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| #define IXGBE_FCOE_DDP_MAX	512	/* 9 bits xid */
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| 
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| /* Default traffic class to use for FCoE */
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| #define IXGBE_FCOE_DEFTC	3
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| 
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| /* fcerr */
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| #define IXGBE_FCERR_BADCRC       0x00100000
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| 
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| struct ixgbe_fcoe_ddp {
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| 	int len;
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| 	u32 err;
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| 	unsigned int sgc;
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| 	struct scatterlist *sgl;
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| 	dma_addr_t udp;
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| 	u64 *udl;
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| };
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| 
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| struct ixgbe_fcoe {
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| #ifdef CONFIG_IXGBE_DCB
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| 	u8 tc;
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| 	u8 up;
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| #endif
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| 	spinlock_t lock;
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| 	struct pci_pool *pool;
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| 	struct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX];
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| };
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| 
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| #endif /* _IXGBE_FCOE_H */
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