Current code doesn't really enable the usb clocks so if they're disabled
when booting linux, the kernel/machine will hang as soon as someone is trying
to read a usb register
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch is fixing some issues :
- MXC_OTG_UCTRL_OPM_BIT is for USBCTRL register and not PHYCTRL register.
- the MXC_EHCI_WAKEUP_ENABLED check was only clearing the bits so never allows
to set them.
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch fixes below build error by adding the missing asm/memory.h,
which is needed for arch_is_coherent().
$ make pxa3xx_defconfig; make
CC init/do_mounts_rd.o
In file included from include/linux/list_bl.h:5,
from include/linux/rculist_bl.h:7,
from include/linux/dcache.h:7,
from include/linux/fs.h:381,
from init/do_mounts_rd.c:3:
include/linux/bit_spinlock.h: In function 'bit_spin_unlock':
include/linux/bit_spinlock.h:61: error: implicit declaration of function 'arch_is_coherent'
make[1]: *** [init/do_mounts_rd.o] Error 1
make: *** [init] Error 2
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Peter Huewe <peterhuewe@gmx.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add basic function and uart device support.
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
mx5 SoCs have different GPIO port count.
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Allow one shot timer mode to be used with the TWD. This allows
NOHZ mode to be used on SMP systems using the TWD localtimer.
Tested on Versatile Express and U8500.
Tested-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
There may be up to two MIPI CSI slave interfaces depending on the SoC version.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add IRQ and register base address definitions for MIPI CSI slave devices.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Naming changed for consistency with s5pv310 where there are two instances
of the device.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds DM9000 Ethernet Controller device support for SMDKV210.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds the SROM controller clock to the list of clocks to be enabled at
boot time. It is required to be enabled at boot time since the modules connected
over the SROM interface such as the Ethernet controller need an operational SROM.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch modifies the following.
1. Moves the SROM controller mapping from S5PV210 specific code to
S5P common code. The SROM controller mapping can be used for all
S5P SoCs.
2. Define the SROM controller physical address for S5P64X0, S5P6442,
S5PC100, S5PV210 and S5PV310.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Some of the S5P platforms like S5PC100 and S5PV210 include SROM banks
4 and 5 in addition to SROM banks 0 to 3. This patch adds register
offsets for SROM bank 4 and 5.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds shift macros for the SROM Bus width and control
register to represent the shift count for the 5th and 6th SROM
banks. Some of the S5P SOCs have them.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The SROM register difinitions of S5PV310/S5PC210 (mach/regs-srom.h)
can be used to other S5P SoCs such as S5PV210/S5PC110. So moved into
plat/regs-srom.h of plat-s5p directory.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Change the name of mmc spcial clock from mmc_bus to sclk_mmc to be
in line with the naming across the S5P SoCs
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
[kgene.kim@samsung.com: minor edit of title]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch changes the gpiolib initialization from arch_initcall
to core_initcall will allow us to make use of gpio functions in
smdk64x0_machine_init function.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds RTC clock for S5P6450.
Signed-off-by: Atul Dahiya <atul.dahiya@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Already can support S5P6440 GPIOlib but S5P6450. This patch changes regarding
S5P6440 GPIO definitions so that can be used it from S5P6450 and adds S5P6450
GPIO chips.
Tested-by: Atul Dahiya <atul.dahiya@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Enable frame buffer display support for SMDKV210 board.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Jonghun Han <jonghun.han@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Universal (C210) board has 3 SDHCI devices.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: minor edit of title]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds support Power Domain for S5PV310 and S5PC210.
Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch is applied according to the commit 1a8e41cd67
(ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register).
Actually, S5PV310 has same cache controller(PL310).
Following is from Catalin Marinas' commit.
Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Cc: <stable@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch implements Power Domain control based on Runtime PM framework.
Each Power Domain is represented by a Power Domain device and the devices
belong to these Power Domains should be set as a child device of the Power
Domain devices. The corresponding drivers of the devices should implement
Runtime PM to control the Power Domains.
Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Conver the VIC timer interrupts to use the irq_ versions of the IRQ
operatiosn introduced in 2.6.37, storing the mask for the timer
interrupt in the chip_data of the irq_data in order to save having to
do a substraction and a shift on every operation.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Convert to the new irq_ versions of the IRQ operations. As well as
the textual substituion of irq_data for the raw IRQ number we also
convert the register base lookup to in s3c_irq_uart_base() to pick
the irq_data up directly.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This makes all the functions that use the shift slightly smaller, one
instruction in most cases but more for ack() and maskack().
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Kernel 2.6.37 adds new interrupt methods which take a struct irq_data
rather than an irq number. Conver S3C64xx irq-eint to use this with a
simple textual substitution.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Kernel 2.6.37 adds new interrupt methods which take a struct irq_data
rather than an irq number. Begin converting Samsung platforms over to
these methods by converting s3c_irqext_wake() with a simple textual
substitution.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
