We use space #18 for floating point regs.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
The Cache Size Selection Register (CSSELR) selects the current Cache
Size ID Register (CCSIDR). You write which cache you are interested
in to CSSELR, and read the information out of CCSIDR.
Which cache numbers are valid is known by reading the Cache Level ID
Register (CLIDR).
To export this state to userspace, we add a KVM_REG_ARM_DEMUX
numberspace (17), which uses 8 bits to represent which register is
being demultiplexed (0 for CCSIDR), and the lower 8 bits to represent
this demultiplexing (in our case, the CSSELR value, which is 4 bits).
Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
The following three ioctls are implemented:
- KVM_GET_REG_LIST
- KVM_GET_ONE_REG
- KVM_SET_ONE_REG
Now we have a table for all the cp15 registers, we can drive a generic
API.
The register IDs carry the following encoding:
ARM registers are mapped using the lower 32 bits. The upper 16 of that
is the register group type, or coprocessor number:
ARM 32-bit CP15 registers have the following id bit patterns:
0x4002 0000 000F <zero:1> <crn:4> <crm:4> <opc1:4> <opc2:3>
ARM 64-bit CP15 registers have the following id bit patterns:
0x4003 0000 000F <zero:1> <zero:4> <crm:4> <opc1:4> <zero:3>
For futureproofing, we need to tell QEMU about the CP15 registers the
host lets the guest access.
It will need this information to restore a current guest on a future
CPU or perhaps a future KVM which allow some of these to be changed.
We use a separate table for these, as they're only for the userspace API.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
Adds a new important function in the main KVM/ARM code called
handle_exit() which is called from kvm_arch_vcpu_ioctl_run() on returns
from guest execution. This function examines the Hyp-Syndrome-Register
(HSR), which contains information telling KVM what caused the exit from
the guest.
Some of the reasons for an exit are CP15 accesses, which are
not allowed from the guest and this commit handles these exits by
emulating the intended operation in software and skipping the guest
instruction.
Minor notes about the coproc register reset:
1) We reserve a value of 0 as an invalid cp15 offset, to catch bugs in our
table, at cost of 4 bytes per vcpu.
2) Added comments on the table indicating how we handle each register, for
simplicity of understanding.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
Provides complete world-switch implementation to switch to other guests
running in non-secure modes. Includes Hyp exception handlers that
capture necessary exception information and stores the information on
the VCPU and KVM structures.
The following Hyp-ABI is also documented in the code:
Hyp-ABI: Calling HYP-mode functions from host (in SVC mode):
Switching to Hyp mode is done through a simple HVC #0 instruction. The
exception vector code will check that the HVC comes from VMID==0 and if
so will push the necessary state (SPSR, lr_usr) on the Hyp stack.
- r0 contains a pointer to a HYP function
- r1, r2, and r3 contain arguments to the above function.
- The HYP function will be called with its arguments in r0, r1 and r2.
On HYP function return, we return directly to SVC.
A call to a function executing in Hyp mode is performed like the following:
<svc code>
ldr r0, =BSYM(my_hyp_fn)
ldr r1, =my_param
hvc #0 ; Call my_hyp_fn(my_param) from HYP mode
<svc code>
Otherwise, the world-switch is pretty straight-forward. All state that
can be modified by the guest is first backed up on the Hyp stack and the
VCPU values is loaded onto the hardware. State, which is not loaded, but
theoretically modifiable by the guest is protected through the
virtualiation features to generate a trap and cause software emulation.
Upon guest returns, all state is restored from hardware onto the VCPU
struct and the original state is restored from the Hyp-stack onto the
hardware.
SMP support using the VMPIDR calculated on the basis of the host MPIDR
and overriding the low bits with KVM vcpu_id contributed by Marc Zyngier.
Reuse of VMIDs has been implemented by Antonios Motakis and adapated from
a separate patch into the appropriate patches introducing the
functionality. Note that the VMIDs are stored per VM as required by the ARM
architecture reference manual.
To support VFP/NEON we trap those instructions using the HPCTR. When
we trap, we switch the FPU. After a guest exit, the VFP state is
returned to the host. When disabling access to floating point
instructions, we also mask FPEXC_EN in order to avoid the guest
receiving Undefined instruction exceptions before we have a chance to
switch back the floating point state. We are reusing vfp_hard_struct,
so we depend on VFPv3 being enabled in the host kernel, if not, we still
trap cp10 and cp11 in order to inject an undefined instruction exception
whenever the guest tries to use VFP/NEON. VFP/NEON developed by
Antionios Motakis and Rusty Russell.
Aborts that are permission faults, and not stage-1 page table walk, do
not report the faulting address in the HPFAR. We have to resolve the
IPA, and store it just like the HPFAR register on the VCPU struct. If
the IPA cannot be resolved, it means another CPU is playing with the
page tables, and we simply restart the guest. This quirk was fixed by
Marc Zyngier.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Antonios Motakis <a.motakis@virtualopensystems.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
All interrupt injection is now based on the VM ioctl KVM_IRQ_LINE. This
works semantically well for the GIC as we in fact raise/lower a line on
a machine component (the gic). The IOCTL uses the follwing struct.
struct kvm_irq_level {
union {
__u32 irq; /* GSI */
__s32 status; /* not used for KVM_IRQ_LEVEL */
};
__u32 level; /* 0 or 1 */
};
ARM can signal an interrupt either at the CPU level, or at the in-kernel irqchip
(GIC), and for in-kernel irqchip can tell the GIC to use PPIs designated for
specific cpus. The irq field is interpreted like this:
bits: | 31 ... 24 | 23 ... 16 | 15 ... 0 |
field: | irq_type | vcpu_index | irq_number |
The irq_type field has the following values:
- irq_type[0]: out-of-kernel GIC: irq_number 0 is IRQ, irq_number 1 is FIQ
- irq_type[1]: in-kernel GIC: SPI, irq_number between 32 and 1019 (incl.)
(the vcpu_index field is ignored)
- irq_type[2]: in-kernel GIC: PPI, irq_number between 16 and 31 (incl.)
The irq_number thus corresponds to the irq ID in as in the GICv2 specs.
This is documented in Documentation/kvm/api.txt.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
This commit introduces the framework for guest memory management
through the use of 2nd stage translation. Each VM has a pointer
to a level-1 table (the pgd field in struct kvm_arch) which is
used for the 2nd stage translations. Entries are added when handling
guest faults (later patch) and the table itself can be allocated and
freed through the following functions implemented in
arch/arm/kvm/arm_mmu.c:
- kvm_alloc_stage2_pgd(struct kvm *kvm);
- kvm_free_stage2_pgd(struct kvm *kvm);
Each entry in TLBs and caches are tagged with a VMID identifier in
addition to ASIDs. The VMIDs are assigned consecutively to VMs in the
order that VMs are executed, and caches and tlbs are invalidated when
the VMID space has been used to allow for more than 255 simultaenously
running guests.
The 2nd stage pgd is allocated in kvm_arch_init_vm(). The table is
freed in kvm_arch_destroy_vm(). Both functions are called from the main
KVM code.
We pre-allocate page table memory to be able to synchronize using a
spinlock and be called under rcu_read_lock from the MMU notifiers. We
steal the mmu_memory_cache implementation from x86 and adapt for our
specific usage.
We support MMU notifiers (thanks to Marc Zyngier) through
kvm_unmap_hva and kvm_set_spte_hva.
Finally, define kvm_phys_addr_ioremap() to map a device at a guest IPA,
which is used by VGIC support to map the virtual CPU interface registers
to the guest. This support is added by Marc Zyngier.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
Sets up KVM code to handle all exceptions taken to Hyp mode.
When the kernel is booted in Hyp mode, calling an hvc instruction with r0
pointing to the new vectors, the HVBAR is changed to the the vector pointers.
This allows subsystems (like KVM here) to execute code in Hyp-mode with the
MMU disabled.
We initialize other Hyp-mode registers and enables the MMU for Hyp-mode from
the id-mapped hyp initialization code. Afterwards, the HVBAR is changed to
point to KVM Hyp vectors used to catch guest faults and to switch to Hyp mode
to perform a world-switch into a KVM guest.
Also provides memory mapping code to map required code pages, data structures,
and I/O regions accessed in Hyp mode at the same virtual address as the host
kernel virtual addresses, but which conforms to the architectural requirements
for translations in Hyp mode. This interface is added in arch/arm/kvm/arm_mmu.c
and comprises:
- create_hyp_mappings(from, to);
- create_hyp_io_mappings(from, to, phys_addr);
- free_hyp_pmds();
Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
Targets KVM support for Cortex A-15 processors.
Contains all the framework components, make files, header files, some
tracing functionality, and basic user space API.
Only supported core is Cortex-A15 for now.
Most functionality is in arch/arm/kvm/* or arch/arm/include/asm/kvm_*.h.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
Add a method (hyp_idmap_setup) to populate a hyp pgd with an
identity mapping of the code contained in the .hyp.idmap.text
section.
Offer a method to drop this identity mapping through
hyp_idmap_teardown.
Make all the above depend on CONFIG_ARM_VIRT_EXT and CONFIG_ARM_LPAE.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
KVM uses the stage-2 page tables and the Hyp page table format,
so we define the fields and page protection flags needed by KVM.
The nomenclature is this:
- page_hyp: PL2 code/data mappings
- page_hyp_device: PL2 device mappings (vgic access)
- page_s2: Stage-2 code/data page mappings
- page_s2_device: Stage-2 device mappings (vgic access)
Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
Christoffer Dall <c.dall@virtualopensystems.com>
When the patch "arm: mvebu: Use dw-apb-uart instead of ns16650 as UART
driver" was applied to a git tree and became the commit b24212fbfb
it wrongly removed the i2c support. This patch reintroduce it.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
refactored printing of the kernel warning:
"orion_mpp_conf: requested MPP%u config unavailable on this hardware\n"
which is not to be printed in case of variant_mask = 0 (unknown variant).
This check should be performed using a logical AND (&&) as opposed
to a bitwise AND (&).
Otherwise, test would fail (and message would not be printed) if
variant_mask != 1
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Olof Johansson <olof@lixom.net>
Cc: Nicolas Pitre <nico@linaro.org>
Cc: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In a DT, the interrupts of an interrupt-controller are not usable when
#interrupt-cells is missing.
This patch activates the interrupts of the GPIOs 0 and 1 for the Marvell
Dove SoC.
Signed-off-by: Jean-François Moine <moinejf@free.fr>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Add the missing spin_unlock statement to unlock
master_lock when prcmu_gic_decouple() return TRUE
Signed-off-by: steve zhan <zhanzhenbo@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The AB8500 Battery Management collection of drivers are more than a
little bit broken. There is lots of work still on-going in that area
and it's improving day by day; however, it's not ready to be enabled
by default just yet.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Concerning pinctrl_macb0_rmii_mii, values were okay, but not comments.
Signed-off-by: Douglas Gilbert <dgilbert@interlog.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
No need for this cmdline option as we are using DT.
Moreover this defconfig is targeted to multiple SoC/boards: this option
was nonsense.
Reported-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This patch overrides default macb pinctrl config defined in
at91sam9260.dtsi (pinctrl_macb_rmii) with kizbox board config
(pinctrl_macb_rmii + pinctrl_macb_rmii_mii_alt).
Signed-off-by: Boris BREZILLON <linux-arm@overkiz.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Make BGA as the default version as we are supposed to just have
to specify when we use the PQFP version.
Issue was existing since commit:
3e90772 (ARM: at91: fix at91rm9200 soc subtype handling).
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: stable <stable@vger.kernel.org> [v3.3]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The SCK pins where missing in usarts pinctrl.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The PIN_BANK 3 is for PDxx pins, not PCxx pins.
And PIN_BANK 1 is for PBxx, not PIN_BANK 0.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The NAND init section was erroneously named "Framebuffer".
Gpio expander section should really be called "I2C devices"
since it contains all i2c init code.
Signed-off-by: Marko Katic <dromede@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Using pxa27x you could now build both RTC_DRV_PXA and RTC_DRV_SA1100.
Make sure you don't use both together: link /dev/rtc0 or /dev/rtc1
to /dev/rtc according to your requirement.
Signed-off-by: Andrea Adami <andrea.adami@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
The Chip Select Configuration Register must be programmed to 0x2 in
order to achieve the correct behavior of the Static Memory Controller.
Without this patch devices wired to DFI and accessed through SMC cannot
be accessed after resume from S2.
Do not rely on the boot loader to program the CSMSADRCFG register by
programming it in the kernel smemc module.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Cc: stable@vger.kernel.org
Acked-by: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
The #ifdefs around the leds-gpio device platform data are erroneous. Currently
the device is not instantiated on the centro unless CONFIG_MACH_TREO680 is
defined. This patch eliminates the #ifdefs, and uses the machine_is_* macros to
initialize the data based on which machine the code is running on and the
build-time configuration. Unused data is optimized out by the build tools if
build configuration does not enable support for both machines.
Tested on my palm treo 680, and compile-tested for all three combinations of
treo680/centro build configurations.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Acked-by: Tomas Cech <sleep_walker@suse.cz>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
This patch gets the LCD working on my Palm Treo680 by adding some code that
manages the three gpios interfaced to the lcd on the Treo 680. The precise role
of each gpio in the hardware architecture is not entirely clear to me; this
patch is the result of trial-and-error and observing how the PalmOS code
initializes the lcd.
The need for this patch is not evident when Linux is loaded from PalmOS, because
at that point the lcd-related gpios have already been configured. But when
booting the kernel by other means, this patch is required unless the bootloader
has performed the necessary initialializations.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Acked-by: Tomas Cech <sleep_walker@suse.cz>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Use IF_ENABLED macro from kconfig.h. Thanks Sergei.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Acked-by: Tomas Cech <sleep_walker@suse.cz>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
This patch adds initialization of the docg4 nand flash device to the treo680.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Tomas Cech <sleep_walker@suse.cz>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
CONFIG_VFP appears to be required to use the
Debian armhf userspace. Enabling this is consistent
with many other shmobile boards.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Update the defconfig to enable the CEU camera.
It appears that it was previously enabled but an
update is required for Kconfig changes.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The gpio controller on kirkwood can provide interrupts but is missing
the #interrupt-cells property. This patch just adds it to both gpio
controllers.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The cam_mclk clock is generated through the following clocks chain:
dpll4 -> dpll4_m5 -> dpll4_m5x2 -> cam_mclk
As dpll4_m5 and dpll4_m5x2 do not driver any clock other than cam_mclk,
back-propagate the cam_clk rate changes up to dpll4_m5.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Sakari Ailus <sakari.ailus@iki.fi>
Tested-by: Sakari Ailus <sakari.ailus@iki.fi>
- A build fix for recently merged omap DRM changes
- Regression fixes from the common clock framework conversion
for omap4 audio and omap2 reboot
- Regression fix for pandaboard WLAN control UART muxing caused by
u-boot only muxing essential pins nowadays
- Timer iteration fix for CONFIG_OF_DYNAMIC
- A section mismatch fix for ocp2scp init
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Merge tag 'omap-for-v3.8-rc4/fixes-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
From Tony Lindgren:
Minimal omap fixes for the -rc series:
- A build fix for recently merged omap DRM changes
- Regression fixes from the common clock framework conversion
for omap4 audio and omap2 reboot
- Regression fix for pandaboard WLAN control UART muxing caused by
u-boot only muxing essential pins nowadays
- Timer iteration fix for CONFIG_OF_DYNAMIC
- A section mismatch fix for ocp2scp init
* tag 'omap-for-v3.8-rc4/fixes-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (306 commits)
ARM: OMAP2+: omap4-panda: add UART2 muxing for WiLink shared transport
ARM: OMAP2+: DT node Timer iteration fix
ARM: OMAP2+: Fix section warning for omap_init_ocp2scp()
ARM: OMAP2+: fix build break for omapdrm
ARM: OMAP2: Fix missing omap2xxx_clkt_vps_late_init function calls
ARM: OMAP4: hwmod_data: Correct IDLEMODE for McPDM
ARM: OMAP4: clock data: Lock ABE DPLL on all revisions
+ Linux 3.8-rc4
Signed-off-by: Olof Johansson <olof@lixom.net>
The Allwinner SoCs have an IP module that handle both the muxing and the
GPIOs.
This IP has 8 banks of 32 bits, with a number of pins actually useful
for each of these banks varying from one to another, and depending on
the SoC used on the board.
This driver only implements the pinctrl part, the gpio part will come
eventually.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Introduce an IP reset API for use on DaVinci SoC.
There is no existing "reset" framework support for SoC devices.
The remoteproc driver needs explicit control of the DSP's reset line.
To support this, a new DaVinci specific API is added.
This private API will disappear with DT migration. Some discussion
regarding a proposed DT "reset" binding is here:
https://patchwork.kernel.org/patch/1635051/
Modify davinci_clk_init() to set clk "reset" function for clocks
that indicate PSC_LRST support. Also fix indentation issue with
function opening curly brace.
Signed-off-by: Robert Tivy <rtivy@ti.com>
[nsekhar@ti.com: rename davinci_psc_config_reset() to davinci_psc_reset()]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
prima2 and marco has different memory base, the old code will
fail if we enable DEBUG_LL in marco.
this patch adds two debuf port, while debugging, we select one
of PRIMA2 and MARCO debug ports, in the products, we disable
DEBUG_LL.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
this patch adds tick timer, smp entries and generic DT machine
for SiRFmarco dual-core SMP chips.
with the added marco, we change the defconfig, using the same
defconfig, we get a zImage which can work on both prima2 and
marco.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Cc: Mark Rutland <mark.rutland@arm.com>
in Marco, we will use GIC. this patch prepares the handle_irq for prima2
to avoid the compiling errors since we want only one defconfig and zImage
for both prima2 and marco that means we will need handle_irq for both.
Signed-off-by: Baohua Song <Baohua.Song@csr.com>
marco has SET/CLEAR registers pair for rstc to avoid read-modify-write,
this patch detects the mach typer and access registers based on SoC.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Marco timer has different timer IP with prima2, so rename the current timer
to timer-prima2 so that we can add timer-marco.
at the same time, if we don't find prima2 timer node in dt, don't panic the
system as we will make prima2 and marco use same kernel image.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
prima2 and marco have diffetent l2 cache configuration, so
we initialize l2x0 cache based on dtb given to kernel.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
prima2 and marco have different memory base address. prima2
begins from 0 and marco begins from 0x40000000.
This patch enables AUTO_ZRELADDR so that kernel can detect
the physical address automatically.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
CC: Mark Rutland <mark.rutland@arm.com>
SiRFmarco is a dual-core cortex-a9 SMP SoC from CSR. this patch
adds the .dtsi and a basic evb board .dts for it.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
