2012-07-06 07:36:43 +10:00
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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2015-01-14 15:35:00 +10:00
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#include "priv.h"
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2012-07-06 07:36:43 +10:00
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2012-07-10 10:49:22 +10:00
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#include <subdev/bios.h>
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2012-11-04 01:01:53 +01:00
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#include <subdev/bus.h>
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2012-07-10 12:20:17 +10:00
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#include <subdev/gpio.h>
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2012-07-10 14:36:38 +10:00
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#include <subdev/i2c.h>
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2014-08-26 00:26:38 +02:00
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#include <subdev/fuse.h>
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2015-01-13 23:37:38 +10:00
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#include <subdev/clk.h>
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2012-09-02 02:55:58 +02:00
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#include <subdev/therm.h>
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2012-07-22 16:41:26 +10:00
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#include <subdev/mxm.h>
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2012-07-11 10:44:20 +10:00
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#include <subdev/devinit.h>
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2012-07-11 15:58:56 +10:00
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#include <subdev/mc.h>
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2012-07-11 16:08:25 +10:00
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#include <subdev/timer.h>
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2012-07-11 19:05:01 +10:00
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#include <subdev/fb.h>
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2012-07-14 19:09:17 +10:00
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#include <subdev/instmem.h>
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2015-01-14 09:57:36 +10:00
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#include <subdev/mmu.h>
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2012-07-14 19:09:17 +10:00
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#include <subdev/bar.h>
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2015-01-14 00:04:21 +10:00
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#include <subdev/pmu.h>
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2013-02-08 09:34:56 +10:00
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#include <subdev/volt.h>
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2012-07-06 07:36:43 +10:00
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2012-07-20 08:17:34 +10:00
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#include <engine/dmaobj.h>
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#include <engine/fifo.h>
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2015-01-14 12:34:00 +10:00
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#include <engine/sw.h>
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2015-01-14 12:02:28 +10:00
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#include <engine/gr.h>
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2012-07-20 08:17:34 +10:00
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#include <engine/mpeg.h>
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#include <engine/vp.h>
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2015-01-14 10:46:55 +10:00
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#include <engine/cipher.h>
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#include <engine/sec.h>
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2012-07-20 08:17:34 +10:00
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#include <engine/bsp.h>
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2015-01-14 10:09:24 +10:00
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#include <engine/msvld.h>
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2015-01-14 12:50:04 +10:00
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#include <engine/mspdec.h>
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2015-01-14 12:26:28 +10:00
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#include <engine/msppp.h>
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2015-01-14 11:50:20 +10:00
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#include <engine/ce.h>
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2012-07-20 08:17:34 +10:00
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#include <engine/disp.h>
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2015-01-14 12:11:28 +10:00
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#include <engine/pm.h>
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2012-07-20 08:17:34 +10:00
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2012-07-06 07:36:43 +10:00
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int
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2015-01-14 15:35:00 +10:00
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nv50_identify(struct nvkm_device *device)
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2012-07-06 07:36:43 +10:00
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{
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switch (device->chipset) {
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case 0x50:
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2012-07-27 08:28:20 +10:00
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device->cname = "G80";
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2015-01-14 15:35:00 +10:00
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
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2014-05-12 14:18:06 +10:00
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device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
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2014-05-13 13:59:26 +10:00
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device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
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2015-01-14 14:53:51 +10:00
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device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
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2015-01-13 23:37:38 +10:00
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device->oclass[NVDEV_SUBDEV_CLK ] = nv50_clk_oclass;
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2012-09-02 02:55:58 +02:00
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device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
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2012-07-22 16:41:26 +10:00
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device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
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2014-01-14 15:55:38 +10:00
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device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
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2013-10-11 15:34:08 +10:00
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device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
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2013-10-24 09:39:05 +10:00
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device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
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2012-07-11 16:08:25 +10:00
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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2013-10-18 14:18:04 +10:00
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device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass;
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2013-12-23 00:39:47 +10:00
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
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2015-01-14 09:57:36 +10:00
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device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
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2012-07-14 19:09:17 +10:00
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device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
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2013-02-08 09:34:56 +10:00
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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2014-08-10 04:10:24 +10:00
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
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2013-11-05 14:26:58 +10:00
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device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
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2015-01-14 12:34:00 +10:00
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device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
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2015-01-14 12:02:28 +10:00
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device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
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2012-07-20 08:17:34 +10:00
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
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2014-02-20 21:33:34 +10:00
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device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass;
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2015-01-14 12:11:28 +10:00
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device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
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2012-07-06 07:36:43 +10:00
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break;
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case 0x84:
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2012-07-27 08:28:20 +10:00
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device->cname = "G84";
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2015-01-14 15:35:00 +10:00
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
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2014-05-12 14:18:06 +10:00
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device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
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2014-05-13 13:59:26 +10:00
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device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
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2015-01-14 14:53:51 +10:00
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device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
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2015-01-14 14:47:24 +10:00
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device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
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2015-01-14 15:11:48 +10:00
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device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
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2012-07-22 16:41:26 +10:00
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device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
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2015-01-14 14:48:16 +10:00
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device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
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2013-10-11 15:34:08 +10:00
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device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
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2013-10-24 09:39:05 +10:00
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device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
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2012-07-11 16:08:25 +10:00
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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2015-01-14 14:52:58 +10:00
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device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
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2013-12-23 00:39:47 +10:00
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
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2015-01-14 09:57:36 +10:00
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device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
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2012-07-14 19:09:17 +10:00
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device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
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2013-02-08 09:34:56 +10:00
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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2014-08-10 04:10:24 +10:00
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
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2015-01-14 15:28:47 +10:00
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device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
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2015-01-14 12:34:00 +10:00
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device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
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2015-01-14 12:02:28 +10:00
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device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
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2015-01-14 15:29:56 +10:00
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device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
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2015-01-14 15:32:28 +10:00
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device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
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2015-01-14 15:22:43 +10:00
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device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
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2015-01-14 15:22:20 +10:00
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device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
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2015-01-14 15:24:57 +10:00
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device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
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2015-01-14 15:31:13 +10:00
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device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
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2012-07-06 07:36:43 +10:00
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break;
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case 0x86:
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2012-07-27 08:28:20 +10:00
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device->cname = "G86";
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2015-01-14 15:35:00 +10:00
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
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2014-05-12 14:18:06 +10:00
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device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
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2014-05-13 13:59:26 +10:00
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device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
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2015-01-14 14:53:51 +10:00
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device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
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2015-01-14 14:47:24 +10:00
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device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
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2015-01-14 15:11:48 +10:00
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device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
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2012-07-22 16:41:26 +10:00
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device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
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2015-01-14 14:48:16 +10:00
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device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
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2013-10-11 15:34:08 +10:00
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device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
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2013-10-24 09:39:05 +10:00
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device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
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2012-07-11 16:08:25 +10:00
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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2015-01-14 14:52:58 +10:00
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device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
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2013-12-23 00:39:47 +10:00
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
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2015-01-14 09:57:36 +10:00
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device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
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2012-07-14 19:09:17 +10:00
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device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
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2013-02-08 09:34:56 +10:00
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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2014-08-10 04:10:24 +10:00
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
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2015-01-14 15:28:47 +10:00
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device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
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2015-01-14 12:34:00 +10:00
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device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
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2015-01-14 12:02:28 +10:00
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device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
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2015-01-14 15:29:56 +10:00
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device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
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2015-01-14 15:32:28 +10:00
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device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
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2015-01-14 15:22:43 +10:00
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device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
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2015-01-14 15:22:20 +10:00
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device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
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2015-01-14 15:24:57 +10:00
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device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
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2015-01-14 15:31:13 +10:00
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device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
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2012-07-06 07:36:43 +10:00
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break;
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case 0x92:
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2012-07-27 08:28:20 +10:00
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device->cname = "G92";
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2015-01-14 15:35:00 +10:00
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
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2014-09-08 20:27:57 +01:00
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device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
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2014-05-13 13:59:26 +10:00
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device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
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2015-01-14 14:53:51 +10:00
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device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
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2015-01-14 14:47:24 +10:00
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device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
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2015-01-14 15:11:48 +10:00
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device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
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2012-07-22 16:41:26 +10:00
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device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
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2015-01-14 14:48:16 +10:00
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device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
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2013-10-11 15:34:08 +10:00
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device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
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2013-10-24 09:39:05 +10:00
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device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
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2012-07-11 16:08:25 +10:00
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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2015-01-14 14:52:58 +10:00
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device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
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2013-12-23 00:39:47 +10:00
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
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2015-01-14 09:57:36 +10:00
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device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
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2012-07-14 19:09:17 +10:00
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device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
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2013-02-08 09:34:56 +10:00
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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2014-08-10 04:10:24 +10:00
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
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2015-01-14 15:28:47 +10:00
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device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
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2015-01-14 12:34:00 +10:00
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device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
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2015-01-14 12:02:28 +10:00
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device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
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2015-01-14 15:29:56 +10:00
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device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
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2015-01-14 15:32:28 +10:00
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device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
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2015-01-14 15:22:43 +10:00
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device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
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2015-01-14 15:22:20 +10:00
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device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
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2015-01-14 15:24:57 +10:00
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device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
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2015-01-14 15:31:13 +10:00
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device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
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2012-07-06 07:36:43 +10:00
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break;
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case 0x94:
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2012-07-27 08:28:20 +10:00
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device->cname = "G94";
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2015-01-14 15:35:00 +10:00
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
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2015-01-14 15:02:59 +10:00
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device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
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2015-01-14 15:04:16 +10:00
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device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
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2015-01-14 14:53:51 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
|
2015-01-14 14:47:24 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
|
2015-01-14 15:11:48 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
|
2012-07-22 16:41:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 14:48:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
|
2015-01-14 15:08:21 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
|
2015-01-14 14:40:22 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
|
2012-07-11 16:08:25 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 14:52:58 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
|
2013-12-23 00:39:47 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 09:57:36 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
2012-07-14 19:09:17 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
2013-02-08 09:34:56 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2014-08-10 04:10:24 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
2015-01-14 15:28:47 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
2015-01-14 12:34:00 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
|
2015-01-14 12:02:28 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
|
2015-01-14 15:29:56 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
|
2015-01-14 15:32:28 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
|
2015-01-14 15:22:43 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
|
2015-01-14 15:22:20 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
|
2015-01-14 15:24:57 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
|
2015-01-14 15:31:13 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
|
2012-07-06 07:36:43 +10:00
|
|
|
break;
|
|
|
|
|
case 0x96:
|
2012-07-27 08:28:20 +10:00
|
|
|
device->cname = "G96";
|
2015-01-14 15:35:00 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
|
2015-01-14 15:02:59 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
|
2015-01-14 15:04:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
|
2015-01-14 14:53:51 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
|
2015-01-14 14:47:24 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
|
2015-01-14 15:11:48 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
|
2012-07-22 16:41:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 14:48:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
|
2015-01-14 15:08:21 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
|
2015-01-14 14:40:22 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
|
2012-07-11 16:08:25 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 14:52:58 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
|
2013-12-23 00:39:47 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 09:57:36 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
2012-07-14 19:09:17 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
2013-02-08 09:34:56 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2014-08-10 04:10:24 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
2015-01-14 15:28:47 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
2015-01-14 12:34:00 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
|
2015-01-14 12:02:28 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
|
2015-01-14 15:29:56 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
|
2015-01-14 15:32:28 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
|
2015-01-14 15:22:43 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
|
2015-01-14 15:22:20 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
|
2015-01-14 15:24:57 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
|
2015-01-14 15:31:13 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
|
2012-07-06 07:36:43 +10:00
|
|
|
break;
|
|
|
|
|
case 0x98:
|
2012-07-27 08:28:20 +10:00
|
|
|
device->cname = "G98";
|
2015-01-14 15:35:00 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
|
2015-01-14 15:02:59 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
|
2015-01-14 15:04:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
|
2015-01-14 14:53:51 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
|
2015-01-14 14:47:24 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
|
2015-01-14 15:11:48 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
|
2012-07-22 16:41:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 14:48:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
|
2015-01-14 15:08:21 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
|
2015-01-14 14:40:22 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
|
2012-07-11 16:08:25 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 14:52:58 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
|
2013-12-23 00:39:47 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 09:57:36 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
2012-07-14 19:09:17 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
2013-02-08 09:34:56 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2014-08-10 04:10:24 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
2015-01-14 15:28:47 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
2015-01-14 12:34:00 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
|
2015-01-14 12:02:28 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
|
2015-01-14 15:30:09 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
|
2015-01-14 15:31:24 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
|
2015-01-14 15:30:40 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
|
2015-01-14 15:30:22 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
|
2015-01-14 15:24:57 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
|
2015-01-14 15:31:13 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
|
2012-07-06 07:36:43 +10:00
|
|
|
break;
|
|
|
|
|
case 0xa0:
|
2012-07-27 08:28:20 +10:00
|
|
|
device->cname = "G200";
|
2015-01-14 15:35:00 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
|
2015-01-14 15:02:59 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
|
2014-05-13 13:59:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
|
2015-01-14 14:53:51 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
|
2015-01-14 14:47:24 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
|
2015-01-14 15:11:48 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
|
2012-07-22 16:41:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 14:48:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
|
2015-01-14 15:08:21 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
|
2015-01-14 14:40:22 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
|
2012-07-11 16:08:25 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 14:52:58 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
|
2013-12-23 00:39:47 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 09:57:36 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
2012-07-14 19:09:17 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
2013-02-08 09:34:56 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2014-08-10 04:10:24 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
2015-01-14 15:28:47 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
2015-01-14 12:34:00 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
|
2015-01-14 12:02:28 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
|
2015-01-14 15:29:56 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
|
2015-01-14 15:32:28 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
|
2015-01-14 15:22:43 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
|
2015-01-14 15:22:20 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
|
2015-01-14 15:24:57 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass;
|
2015-01-14 15:31:13 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
|
2012-07-06 07:36:43 +10:00
|
|
|
break;
|
|
|
|
|
case 0xaa:
|
2012-07-27 08:28:20 +10:00
|
|
|
device->cname = "MCP77/MCP78";
|
2015-01-14 15:35:00 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
|
2015-01-14 15:02:59 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
|
2015-01-14 15:04:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
|
2015-01-14 14:53:51 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
|
2015-01-14 14:47:24 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
|
2015-01-14 15:11:48 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
|
2012-07-22 16:41:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 14:48:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
|
2015-01-14 15:08:21 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
|
2015-01-14 14:40:22 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
|
2012-07-11 16:08:25 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 14:52:58 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
|
2013-12-23 00:39:47 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 09:57:36 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
2012-07-14 19:09:17 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
2013-02-08 09:34:56 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2014-08-10 04:10:24 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
2015-01-14 15:28:47 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
2015-01-14 12:34:00 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
|
2015-01-14 12:02:28 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
|
2015-01-14 15:30:09 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
|
2015-01-14 15:31:24 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
|
2015-01-14 15:30:40 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
|
2015-01-14 15:30:22 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
|
2015-01-14 15:24:57 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
|
2015-01-14 15:31:13 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
|
2012-07-06 07:36:43 +10:00
|
|
|
break;
|
|
|
|
|
case 0xac:
|
2012-07-27 08:28:20 +10:00
|
|
|
device->cname = "MCP79/MCP7A";
|
2015-01-14 15:35:00 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
|
2015-01-14 15:02:59 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
|
2015-01-14 15:04:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
|
2015-01-14 14:53:51 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
|
2015-01-14 14:47:24 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
|
2015-01-14 15:11:48 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
|
2012-07-22 16:41:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 14:48:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
|
2015-01-14 15:08:21 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
|
2015-01-14 14:40:22 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
|
2012-07-11 16:08:25 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 14:52:58 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
|
2013-12-23 00:39:47 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 09:57:36 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
2012-07-14 19:09:17 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
2013-02-08 09:34:56 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2014-08-10 04:10:24 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
2015-01-14 15:28:47 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
2015-01-14 12:34:00 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
|
2015-01-14 12:02:28 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
|
2015-01-14 15:30:09 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
|
2015-01-14 15:31:24 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
|
2015-01-14 15:30:40 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
|
2015-01-14 15:30:22 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
|
2015-01-14 15:24:57 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
|
2015-01-14 15:31:13 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
|
2012-07-06 07:36:43 +10:00
|
|
|
break;
|
|
|
|
|
case 0xa3:
|
2012-07-27 08:28:20 +10:00
|
|
|
device->cname = "GT215";
|
2015-01-14 15:35:00 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
|
2015-01-14 15:02:59 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
|
2015-01-14 15:04:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
|
2015-01-14 14:53:51 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
|
2015-01-14 14:47:24 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
|
2015-01-14 15:11:48 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
|
2012-07-22 16:41:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 14:48:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
|
2015-01-14 15:08:21 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
|
2015-01-14 14:40:22 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
|
2012-07-11 16:08:25 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 14:52:58 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
|
2013-12-23 00:39:47 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 09:57:36 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
2012-07-14 19:09:17 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
2015-01-14 15:10:40 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
|
2013-02-08 09:34:56 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2014-08-10 04:10:24 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
2015-01-14 15:28:47 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
2015-01-14 12:34:00 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
|
2015-01-14 12:02:28 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
|
2015-01-14 15:29:56 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
|
2015-01-14 15:30:09 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
|
2015-01-14 15:30:40 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
|
2015-01-14 15:30:22 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
|
2015-01-14 15:22:32 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
|
2015-01-14 15:24:57 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
|
2015-01-14 15:31:13 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
|
2012-07-06 07:36:43 +10:00
|
|
|
break;
|
|
|
|
|
case 0xa5:
|
2012-07-27 08:28:20 +10:00
|
|
|
device->cname = "GT216";
|
2015-01-14 15:35:00 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
|
2015-01-14 15:02:59 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
|
2015-01-14 15:04:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
|
2015-01-14 14:53:51 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
|
2015-01-14 14:47:24 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
|
2015-01-14 15:11:48 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
|
2012-07-22 16:41:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 14:48:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
|
2015-01-14 15:08:21 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
|
2015-01-14 14:40:22 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
|
2012-07-11 16:08:25 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 14:52:58 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
|
2013-12-23 00:39:47 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 09:57:36 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
2012-07-14 19:09:17 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
2015-01-14 15:10:40 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
|
2013-02-08 09:34:56 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2014-08-10 04:10:24 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
2015-01-14 15:28:47 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
2015-01-14 12:34:00 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
|
2015-01-14 12:02:28 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
|
2015-01-14 15:30:09 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
|
2015-01-14 15:30:40 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
|
2015-01-14 15:30:22 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
|
2015-01-14 15:22:32 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
|
2015-01-14 15:24:57 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
|
2015-01-14 15:31:13 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
|
2012-07-06 07:36:43 +10:00
|
|
|
break;
|
|
|
|
|
case 0xa8:
|
2012-07-27 08:28:20 +10:00
|
|
|
device->cname = "GT218";
|
2015-01-14 15:35:00 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
|
2015-01-14 15:02:59 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
|
2015-01-14 15:04:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
|
2015-01-14 14:53:51 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
|
2015-01-14 14:47:24 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
|
2015-01-14 15:11:48 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
|
2012-07-22 16:41:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 14:48:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
|
2015-01-14 15:08:21 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
|
2015-01-14 14:40:22 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
|
2012-07-11 16:08:25 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 14:52:58 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
|
2013-12-23 00:39:47 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 09:57:36 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
2012-07-14 19:09:17 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
2015-01-14 15:10:40 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
|
2013-02-08 09:34:56 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2014-08-10 04:10:24 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
2015-01-14 15:28:47 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
2015-01-14 12:34:00 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
|
2015-01-14 12:02:28 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
|
2015-01-14 15:30:09 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
|
2015-01-14 15:30:40 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
|
2015-01-14 15:30:22 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
|
2015-01-14 15:22:32 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
|
2015-01-14 15:24:57 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
|
2015-01-14 15:31:13 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
|
2012-07-06 07:36:43 +10:00
|
|
|
break;
|
|
|
|
|
case 0xaf:
|
2012-07-27 08:28:20 +10:00
|
|
|
device->cname = "MCP89";
|
2015-01-14 15:35:00 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
|
2015-01-14 15:02:59 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
|
2015-01-14 15:04:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
|
2015-01-14 14:53:51 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
|
2015-01-14 14:47:24 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
|
2015-01-14 15:11:48 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
|
2012-07-22 16:41:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 14:48:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = mcp89_devinit_oclass;
|
2015-01-14 15:08:21 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
|
2015-01-14 14:40:22 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
|
2012-07-11 16:08:25 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 14:52:58 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass;
|
2013-12-23 00:39:47 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 09:57:36 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
2012-07-14 19:09:17 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
2015-01-14 15:10:40 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
|
2013-02-08 09:34:56 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2014-08-10 04:10:24 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
2015-01-14 15:28:47 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
2015-01-14 12:34:00 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
|
2015-01-14 12:02:28 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
|
2015-01-14 15:30:09 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
|
2015-01-14 15:30:40 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
|
2015-01-14 15:30:22 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
|
2015-01-14 15:22:32 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
|
2015-01-14 15:24:57 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
|
2015-01-14 15:31:13 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
|
2012-07-06 07:36:43 +10:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
nv_fatal(device, "unknown Tesla chipset\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|