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drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
drm/nouveau/bios: pull in basic vbios subdev, more to come later v2: Ben Skeggs <bskeggs@redhat.com> - use unaligned macros to access vbios image - endianness fixes Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 10:49:22 +10:00
#include <subdev/bios.h>
drm/nouveau/pbus: add a PBUS subdev that hands IRQs to the right subdevs We are going to use PTHERM's IRQs for thermal monitoring but we need to route them first. On nv31-50, PBUS's IRQ line is shared with GPIOs IRQs. It seems like nv10-31 GPIO interruptions aren't well handled. I kept the original behaviour but it is wrong and may lead to an IRQ storm. Since we enable all PBUS IRQs, we need a way to avoid being stormed if we don't handle them. The solution I used was to mask the IRQs that have not been handled. This will also print one message in the logs to let us know. v2: drop the shared intr handler because of was racy v3: style fixes v4: drop a useless construct in the chipset-dependent INTR v5: add BUS to the disable mask v6 (Ben Skeggs): - general tidy to match the rest of the driver's style - nva3->nvc0, nva3 can be serviced just fine with nv50.c, rnndb even notes that the THERM_ALARM bit got left in the hw until fermi anyway.. so, it's not going to conflict - removed the peephole and user stuff, for the moment.. will handle them later if we find a good reason to actually care.. - limited INTR_EN to just what we can handle for now, mostly to prevent spam of unknown status bits (seen on at least nv4x) Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-11-04 01:01:53 +01:00
#include <subdev/bus.h>
drm/nouveau/gpio: port gpio to subdev interfaces v2: Ben Skeggs <bskeggs@redhat.com> - rebase on top of v3.6-rc6 with gpio reset patch integrated already Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 12:20:17 +10:00
#include <subdev/gpio.h>
drm/nouveau/i2c: port to subdev interfaces v2/v3: Ben Skeggs <bskeggs@redhat.com> - fix typo in default bus selection - fix accidental loss of destructor v4: Dmitry Eremin-Solenikov <dmitry_eremin@mentor.com> - fix typo causing incorrect default i2c port settings when no BMP data Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 14:36:38 +10:00
#include <subdev/i2c.h>
drm/nouveau/subdev: add a pfuse subdev v2 We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-26 00:26:38 +02:00
#include <subdev/fuse.h>
drm/nouveau/clk: rename from clock (no binary change) Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-13 23:37:38 +10:00
#include <subdev/clk.h>
drm/nouveau/therm: move thermal-related functions to the therm subdev It looks scary because of the size, but I tried to keep the differences minimal. Further patches will fix the actual "driver" code and add new features. v2: change filenames, split to submodules v3: add a missing include v4: Ben Skeggs <bskeggs@redhat.com> - fixed set_defaults() to allow min_duty < 30 (thermal table will override this if it's actually necessary) - fixed set_defaults() to not provide pwm_freq so nv4x (which only has pwm_div) can actually work. the boards using pwm_freq will have a thermal table entry to provide us the value. - removed unused files Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-09-02 02:55:58 +02:00
#include <subdev/therm.h>
drm/nouveau/mxm: split up into bios code and a subdev module Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-22 16:41:26 +10:00
#include <subdev/mxm.h>
drm/nouveau: implement devinit subdev, and new init table parser v2: - make sure not to execute display scripts unless resuming Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 10:44:20 +10:00
#include <subdev/devinit.h>
drm/nouveau/mc: port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 15:58:56 +10:00
#include <subdev/mc.h>
drm/nouveau/timer: port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 16:08:25 +10:00
#include <subdev/timer.h>
drm/nouveau/fb: merge fb/vram and port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 19:05:01 +10:00
#include <subdev/fb.h>
drm/nouveau/instmem: completely new implementation, as a subdev module v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-14 19:09:17 +10:00
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/bar.h>
drm/nouveau/pmu: rename from pwr (no binary change) Switch to NVIDIA's name for the device. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-14 00:04:21 +10:00
#include <subdev/pmu.h>
drm/nouveau/volt: implement voltage control in core Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-08 09:34:56 +10:00
#include <subdev/volt.h>
drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
drm/nouveau/device: convert to engine, rather than subdev Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-04-25 17:23:43 +10:00
#include <engine/device.h>
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/software.h>
#include <engine/graph.h>
#include <engine/mpeg.h>
#include <engine/vp.h>
#include <engine/crypt.h>
#include <engine/bsp.h>
#include <engine/ppp.h>
#include <engine/copy.h>
#include <engine/disp.h>
drm/nouveau/perfmon: initial infrastructure to expose performance counters Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-13 15:29:11 +10:00
#include <engine/perfmon.h>
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
int
nv50_identify(struct nouveau_device *device)
{
switch (device->chipset) {
case 0x50:
drm/nouveau/device: include the official chipset names Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-27 08:28:20 +10:00
device->cname = "G80";
drm/nouveau/bios: pull in basic vbios subdev, more to come later v2: Ben Skeggs <bskeggs@redhat.com> - use unaligned macros to access vbios image - endianness fixes Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 10:49:22 +10:00
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
drm/nouveau/gpio: use indirect pointer to base class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-12 14:18:06 +10:00
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
drm/nouveau/i2c: start hiding subdev-internal interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-13 13:59:26 +10:00
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
drm/nouveau/subdev: add a pfuse subdev v2 We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-26 00:26:38 +02:00
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
drm/nouveau/clk: rename from clock (no binary change) Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-13 23:37:38 +10:00
device->oclass[NVDEV_SUBDEV_CLK ] = nv50_clk_oclass;
drm/nouveau/therm: move thermal-related functions to the therm subdev It looks scary because of the size, but I tried to keep the differences minimal. Further patches will fix the actual "driver" code and add new features. v2: change filenames, split to submodules v3: add a missing include v4: Ben Skeggs <bskeggs@redhat.com> - fixed set_defaults() to allow min_duty < 30 (thermal table will override this if it's actually necessary) - fixed set_defaults() to not provide pwm_freq so nv4x (which only has pwm_div) can actually work. the boards using pwm_freq will have a thermal table entry to provide us the value. - removed unused files Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-09-02 02:55:58 +02:00
device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
drm/nouveau/mxm: split up into bios code and a subdev module Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-22 16:41:26 +10:00
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
drm/nouveau/devinit: tidy up the subdev class definition Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-14 15:55:38 +10:00
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
drm/nouveau/mc: store static data in nouveau_mc class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-11 15:34:08 +10:00
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
drm/nouveau/bus: make external class definitions pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-24 09:39:05 +10:00
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
drm/nouveau/timer: port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 16:08:25 +10:00
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
drm/nouveau/fb: make external class definitions pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-18 14:18:04 +10:00
device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass;
drm/nouveau/instmem: tidy up the subdev class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-12-23 00:39:47 +10:00
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
drm/nouveau/instmem: completely new implementation, as a subdev module v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-14 19:09:17 +10:00
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
drm/nouveau/volt: implement voltage control in core Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-08 09:34:56 +10:00
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
drm/nouveau/dmaobj: update to an improved style of class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-10 04:10:24 +10:00
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
drm/nouveau/fifo: make external class definitions into pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-05 14:26:58 +10:00
device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
drm/nouveau/sw: prepare for the sharing of constructors between implementations Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-03 07:30:11 +10:00
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
drm/nv50/disp: preparation for storing static class data Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-02-20 21:33:34 +10:00
device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass;
drm/nouveau/perfmon: initial infrastructure to expose performance counters Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-13 15:29:11 +10:00
device->oclass[NVDEV_ENGINE_PERFMON] = nv50_perfmon_oclass;
drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
break;
case 0x84:
drm/nouveau/device: include the official chipset names Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-27 08:28:20 +10:00
device->cname = "G84";
drm/nouveau/bios: pull in basic vbios subdev, more to come later v2: Ben Skeggs <bskeggs@redhat.com> - use unaligned macros to access vbios image - endianness fixes Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 10:49:22 +10:00
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
drm/nouveau/gpio: use indirect pointer to base class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-12 14:18:06 +10:00
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
drm/nouveau/i2c: start hiding subdev-internal interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-13 13:59:26 +10:00
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
drm/nouveau/subdev: add a pfuse subdev v2 We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-26 00:26:38 +02:00
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
drm/nouveau/clk: rename from clock (no binary change) Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-13 23:37:38 +10:00
device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
drm/nouveau/therm: split the nv50 and nv84 code This is needed because temperature management on nv50 can be enabled and it looks about the same as nv40. Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-23 16:45:51 +01:00
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
drm/nouveau/mxm: split up into bios code and a subdev module Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-22 16:41:26 +10:00
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
drm/nv50-/devinit: prevent use of engines marked as disabled by hw/vbios Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-14 16:29:06 +10:00
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
drm/nouveau/mc: store static data in nouveau_mc class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-11 15:34:08 +10:00
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
drm/nouveau/bus: make external class definitions pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-24 09:39:05 +10:00
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
drm/nouveau/timer: port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 16:08:25 +10:00
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
drm/nv50-nvaf/fb: split the class definitions up a bit These will diverge further in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-18 14:44:23 +10:00
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
drm/nouveau/instmem: tidy up the subdev class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-12-23 00:39:47 +10:00
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
drm/nouveau/instmem: completely new implementation, as a subdev module v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-14 19:09:17 +10:00
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
drm/nouveau/volt: implement voltage control in core Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-08 09:34:56 +10:00
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
drm/nouveau/dmaobj: update to an improved style of class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-10 04:10:24 +10:00
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
drm/nouveau/fifo: make external class definitions into pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-05 14:26:58 +10:00
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
drm/nouveau/sw: prepare for the sharing of constructors between implementations Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-03 07:30:11 +10:00
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
drm/nv50/disp: preparation for storing static class data Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-02-20 21:33:34 +10:00
device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
drm/nouveau/perfmon: initial infrastructure to expose performance counters Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-13 15:29:11 +10:00
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
break;
case 0x86:
drm/nouveau/device: include the official chipset names Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-27 08:28:20 +10:00
device->cname = "G86";
drm/nouveau/bios: pull in basic vbios subdev, more to come later v2: Ben Skeggs <bskeggs@redhat.com> - use unaligned macros to access vbios image - endianness fixes Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 10:49:22 +10:00
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
drm/nouveau/gpio: use indirect pointer to base class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-12 14:18:06 +10:00
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
drm/nouveau/i2c: start hiding subdev-internal interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-13 13:59:26 +10:00
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
drm/nouveau/subdev: add a pfuse subdev v2 We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-26 00:26:38 +02:00
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
drm/nouveau/clk: rename from clock (no binary change) Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-13 23:37:38 +10:00
device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
drm/nouveau/therm: split the nv50 and nv84 code This is needed because temperature management on nv50 can be enabled and it looks about the same as nv40. Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-23 16:45:51 +01:00
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
drm/nouveau/mxm: split up into bios code and a subdev module Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-22 16:41:26 +10:00
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
drm/nv50-/devinit: prevent use of engines marked as disabled by hw/vbios Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-14 16:29:06 +10:00
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
drm/nouveau/mc: store static data in nouveau_mc class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-11 15:34:08 +10:00
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
drm/nouveau/bus: make external class definitions pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-24 09:39:05 +10:00
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
drm/nouveau/timer: port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 16:08:25 +10:00
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
drm/nv50-nvaf/fb: split the class definitions up a bit These will diverge further in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-18 14:44:23 +10:00
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
drm/nouveau/instmem: tidy up the subdev class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-12-23 00:39:47 +10:00
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
drm/nouveau/instmem: completely new implementation, as a subdev module v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-14 19:09:17 +10:00
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
drm/nouveau/volt: implement voltage control in core Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-08 09:34:56 +10:00
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
drm/nouveau/dmaobj: update to an improved style of class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-10 04:10:24 +10:00
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
drm/nouveau/fifo: make external class definitions into pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-05 14:26:58 +10:00
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
drm/nouveau/sw: prepare for the sharing of constructors between implementations Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-03 07:30:11 +10:00
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
drm/nv50/disp: preparation for storing static class data Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-02-20 21:33:34 +10:00
device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
drm/nouveau/perfmon: initial infrastructure to expose performance counters Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-13 15:29:11 +10:00
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
break;
case 0x92:
drm/nouveau/device: include the official chipset names Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-27 08:28:20 +10:00
device->cname = "G92";
drm/nouveau/bios: pull in basic vbios subdev, more to come later v2: Ben Skeggs <bskeggs@redhat.com> - use unaligned macros to access vbios image - endianness fixes Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 10:49:22 +10:00
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
drm/nouveau/gpio: rename g92 class to g94 nv92 hardware has only 16 interrupt lines, while nv94 and later has 32. Accessing 0xe0c{0,4} registers on nv92 can lead to incorrect PDISP setup. This is a regression introduced with commit 9d0f5ec9ee0fd5dc5fc1cc2cf559286431e406e3 Author: Ben Skeggs <bskeggs@redhat.com> Date: Mon May 12 15:22:42 2014 +1000 gpio: split g92 class from nv50 Reported-by: estece on #nouveau Cc: stable@vger.kernel.org # 3.16+ Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-09-08 20:27:57 +01:00
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
drm/nouveau/i2c: start hiding subdev-internal interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-13 13:59:26 +10:00
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
drm/nouveau/subdev: add a pfuse subdev v2 We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-26 00:26:38 +02:00
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
drm/nouveau/clk: rename from clock (no binary change) Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-13 23:37:38 +10:00
device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
drm/nouveau/therm: split the nv50 and nv84 code This is needed because temperature management on nv50 can be enabled and it looks about the same as nv40. Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-23 16:45:51 +01:00
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
drm/nouveau/mxm: split up into bios code and a subdev module Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-22 16:41:26 +10:00
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
drm/nv50-/devinit: prevent use of engines marked as disabled by hw/vbios Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-14 16:29:06 +10:00
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
drm/nouveau/mc: store static data in nouveau_mc class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-11 15:34:08 +10:00
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
drm/nouveau/bus: make external class definitions pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-24 09:39:05 +10:00
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
drm/nouveau/timer: port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 16:08:25 +10:00
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
drm/nv50-nvaf/fb: split the class definitions up a bit These will diverge further in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-18 14:44:23 +10:00
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
drm/nouveau/instmem: tidy up the subdev class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-12-23 00:39:47 +10:00
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
drm/nouveau/instmem: completely new implementation, as a subdev module v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-14 19:09:17 +10:00
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
drm/nouveau/volt: implement voltage control in core Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-08 09:34:56 +10:00
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
drm/nouveau/dmaobj: update to an improved style of class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-10 04:10:24 +10:00
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
drm/nouveau/fifo: make external class definitions into pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-05 14:26:58 +10:00
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
drm/nouveau/sw: prepare for the sharing of constructors between implementations Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-03 07:30:11 +10:00
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
drm/nv50/disp: preparation for storing static class data Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-02-20 21:33:34 +10:00
device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
drm/nouveau/perfmon: initial infrastructure to expose performance counters Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-13 15:29:11 +10:00
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
break;
case 0x94:
drm/nouveau/device: include the official chipset names Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-27 08:28:20 +10:00
device->cname = "G94";
drm/nouveau/bios: pull in basic vbios subdev, more to come later v2: Ben Skeggs <bskeggs@redhat.com> - use unaligned macros to access vbios image - endianness fixes Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 10:49:22 +10:00
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
drm/nouveau/gpio: rename g92 class to g94 nv92 hardware has only 16 interrupt lines, while nv94 and later has 32. Accessing 0xe0c{0,4} registers on nv92 can lead to incorrect PDISP setup. This is a regression introduced with commit 9d0f5ec9ee0fd5dc5fc1cc2cf559286431e406e3 Author: Ben Skeggs <bskeggs@redhat.com> Date: Mon May 12 15:22:42 2014 +1000 gpio: split g92 class from nv50 Reported-by: estece on #nouveau Cc: stable@vger.kernel.org # 3.16+ Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-09-08 20:27:57 +01:00
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
drm/nouveau/i2c: start hiding subdev-internal interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-13 13:59:26 +10:00
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
drm/nouveau/subdev: add a pfuse subdev v2 We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-26 00:26:38 +02:00
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
drm/nouveau/clk: rename from clock (no binary change) Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-13 23:37:38 +10:00
device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
drm/nouveau/therm: split the nv50 and nv84 code This is needed because temperature management on nv50 can be enabled and it looks about the same as nv40. Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-23 16:45:51 +01:00
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
drm/nouveau/mxm: split up into bios code and a subdev module Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-22 16:41:26 +10:00
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
drm/nv50-/devinit: prevent use of engines marked as disabled by hw/vbios Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-14 16:29:06 +10:00
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
drm/nv50-nv86,nv92/mc: rearm msi via pci config space, rather than mmio mirror This is what NVIDIA do on these chipsets, let's hope it works around the reported MSI failures for us on NV86. v2: updated to include G92, as per information provided by NVIDIA. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-14 14:58:16 +10:00
device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
drm/nouveau/bus: add interfaces/helpers for sequencer Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-15 10:49:39 +10:00
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
drm/nouveau/timer: port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 16:08:25 +10:00
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
drm/nv50-nvaf/fb: split the class definitions up a bit These will diverge further in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-18 14:44:23 +10:00
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
drm/nouveau/instmem: tidy up the subdev class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-12-23 00:39:47 +10:00
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
drm/nouveau/instmem: completely new implementation, as a subdev module v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-14 19:09:17 +10:00
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
drm/nouveau/volt: implement voltage control in core Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-08 09:34:56 +10:00
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
drm/nouveau/dmaobj: update to an improved style of class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-10 04:10:24 +10:00
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
drm/nouveau/fifo: make external class definitions into pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-05 14:26:58 +10:00
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
drm/nouveau/sw: prepare for the sharing of constructors between implementations Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-03 07:30:11 +10:00
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
drm/nv50/disp: preparation for storing static class data Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-02-20 21:33:34 +10:00
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
drm/nouveau/perfmon: initial infrastructure to expose performance counters Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-13 15:29:11 +10:00
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
break;
case 0x96:
drm/nouveau/device: include the official chipset names Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-27 08:28:20 +10:00
device->cname = "G96";
drm/nouveau/bios: pull in basic vbios subdev, more to come later v2: Ben Skeggs <bskeggs@redhat.com> - use unaligned macros to access vbios image - endianness fixes Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 10:49:22 +10:00
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
drm/nouveau/gpio: rename g92 class to g94 nv92 hardware has only 16 interrupt lines, while nv94 and later has 32. Accessing 0xe0c{0,4} registers on nv92 can lead to incorrect PDISP setup. This is a regression introduced with commit 9d0f5ec9ee0fd5dc5fc1cc2cf559286431e406e3 Author: Ben Skeggs <bskeggs@redhat.com> Date: Mon May 12 15:22:42 2014 +1000 gpio: split g92 class from nv50 Reported-by: estece on #nouveau Cc: stable@vger.kernel.org # 3.16+ Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-09-08 20:27:57 +01:00
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
drm/nouveau/i2c: start hiding subdev-internal interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-13 13:59:26 +10:00
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
drm/nouveau/subdev: add a pfuse subdev v2 We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-26 00:26:38 +02:00
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
drm/nouveau/clk: rename from clock (no binary change) Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-13 23:37:38 +10:00
device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
drm/nouveau/therm: split the nv50 and nv84 code This is needed because temperature management on nv50 can be enabled and it looks about the same as nv40. Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-23 16:45:51 +01:00
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
drm/nouveau/mxm: split up into bios code and a subdev module Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-22 16:41:26 +10:00
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
drm/nv50-/devinit: prevent use of engines marked as disabled by hw/vbios Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-14 16:29:06 +10:00
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
drm/nv50-nv86,nv92/mc: rearm msi via pci config space, rather than mmio mirror This is what NVIDIA do on these chipsets, let's hope it works around the reported MSI failures for us on NV86. v2: updated to include G92, as per information provided by NVIDIA. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-14 14:58:16 +10:00
device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
drm/nouveau/bus: add interfaces/helpers for sequencer Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-15 10:49:39 +10:00
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
drm/nouveau/timer: port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 16:08:25 +10:00
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
drm/nv50-nvaf/fb: split the class definitions up a bit These will diverge further in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-18 14:44:23 +10:00
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
drm/nouveau/instmem: tidy up the subdev class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-12-23 00:39:47 +10:00
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
drm/nouveau/instmem: completely new implementation, as a subdev module v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-14 19:09:17 +10:00
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
drm/nouveau/volt: implement voltage control in core Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-08 09:34:56 +10:00
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
drm/nouveau/dmaobj: update to an improved style of class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-10 04:10:24 +10:00
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
drm/nouveau/fifo: make external class definitions into pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-05 14:26:58 +10:00
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
drm/nouveau/sw: prepare for the sharing of constructors between implementations Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-03 07:30:11 +10:00
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
drm/nv50/disp: preparation for storing static class data Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-02-20 21:33:34 +10:00
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
drm/nouveau/perfmon: initial infrastructure to expose performance counters Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-13 15:29:11 +10:00
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
break;
case 0x98:
drm/nouveau/device: include the official chipset names Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-27 08:28:20 +10:00
device->cname = "G98";
drm/nouveau/bios: pull in basic vbios subdev, more to come later v2: Ben Skeggs <bskeggs@redhat.com> - use unaligned macros to access vbios image - endianness fixes Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 10:49:22 +10:00
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
drm/nouveau/gpio: rename g92 class to g94 nv92 hardware has only 16 interrupt lines, while nv94 and later has 32. Accessing 0xe0c{0,4} registers on nv92 can lead to incorrect PDISP setup. This is a regression introduced with commit 9d0f5ec9ee0fd5dc5fc1cc2cf559286431e406e3 Author: Ben Skeggs <bskeggs@redhat.com> Date: Mon May 12 15:22:42 2014 +1000 gpio: split g92 class from nv50 Reported-by: estece on #nouveau Cc: stable@vger.kernel.org # 3.16+ Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-09-08 20:27:57 +01:00
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
drm/nouveau/i2c: start hiding subdev-internal interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-13 13:59:26 +10:00
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
drm/nouveau/subdev: add a pfuse subdev v2 We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-26 00:26:38 +02:00
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
drm/nouveau/clk: rename from clock (no binary change) Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-13 23:37:38 +10:00
device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
drm/nouveau/therm: split the nv50 and nv84 code This is needed because temperature management on nv50 can be enabled and it looks about the same as nv40. Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-23 16:45:51 +01:00
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
drm/nouveau/mxm: split up into bios code and a subdev module Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-22 16:41:26 +10:00
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
drm/nv50-/devinit: prevent use of engines marked as disabled by hw/vbios Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-14 16:29:06 +10:00
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
drm/nouveau/mc: store static data in nouveau_mc class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-11 15:34:08 +10:00
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
drm/nouveau/bus: add interfaces/helpers for sequencer Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-15 10:49:39 +10:00
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
drm/nouveau/timer: port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 16:08:25 +10:00
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
drm/nv50-nvaf/fb: split the class definitions up a bit These will diverge further in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-18 14:44:23 +10:00
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
drm/nouveau/instmem: tidy up the subdev class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-12-23 00:39:47 +10:00
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
drm/nouveau/instmem: completely new implementation, as a subdev module v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-14 19:09:17 +10:00
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
drm/nouveau/volt: implement voltage control in core Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-08 09:34:56 +10:00
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
drm/nouveau/dmaobj: update to an improved style of class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-10 04:10:24 +10:00
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
drm/nouveau/fifo: make external class definitions into pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-05 14:26:58 +10:00
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
drm/nouveau/sw: prepare for the sharing of constructors between implementations Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-03 07:30:11 +10:00
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
drm/nouveau/vdec: fork vp3 implementations from vp2 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-27 14:04:20 +10:00
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
drm/nouveau/vdec: fork vp3 implementations from vp2 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-27 14:04:20 +10:00
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
drm/nv50/disp: preparation for storing static class data Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-02-20 21:33:34 +10:00
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
drm/nouveau/perfmon: initial infrastructure to expose performance counters Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-13 15:29:11 +10:00
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
break;
case 0xa0:
drm/nouveau/device: include the official chipset names Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-27 08:28:20 +10:00
device->cname = "G200";
drm/nouveau/bios: pull in basic vbios subdev, more to come later v2: Ben Skeggs <bskeggs@redhat.com> - use unaligned macros to access vbios image - endianness fixes Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 10:49:22 +10:00
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
drm/nouveau/gpio: rename g92 class to g94 nv92 hardware has only 16 interrupt lines, while nv94 and later has 32. Accessing 0xe0c{0,4} registers on nv92 can lead to incorrect PDISP setup. This is a regression introduced with commit 9d0f5ec9ee0fd5dc5fc1cc2cf559286431e406e3 Author: Ben Skeggs <bskeggs@redhat.com> Date: Mon May 12 15:22:42 2014 +1000 gpio: split g92 class from nv50 Reported-by: estece on #nouveau Cc: stable@vger.kernel.org # 3.16+ Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-09-08 20:27:57 +01:00
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
drm/nouveau/i2c: start hiding subdev-internal interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-13 13:59:26 +10:00
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
drm/nouveau/subdev: add a pfuse subdev v2 We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-26 00:26:38 +02:00
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
drm/nouveau/clk: rename from clock (no binary change) Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-13 23:37:38 +10:00
device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
drm/nouveau/therm: split the nv50 and nv84 code This is needed because temperature management on nv50 can be enabled and it looks about the same as nv40. Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-23 16:45:51 +01:00
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
drm/nouveau/mxm: split up into bios code and a subdev module Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-22 16:41:26 +10:00
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
drm/nv50-/devinit: prevent use of engines marked as disabled by hw/vbios Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-14 16:29:06 +10:00
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
drm/nouveau/mc: store static data in nouveau_mc class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-11 15:34:08 +10:00
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
drm/nouveau/bus: add interfaces/helpers for sequencer Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-15 10:49:39 +10:00
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
drm/nouveau/timer: port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 16:08:25 +10:00
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
drm/nv50-nvaf/fb: split the class definitions up a bit These will diverge further in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-18 14:44:23 +10:00
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
drm/nouveau/instmem: tidy up the subdev class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-12-23 00:39:47 +10:00
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
drm/nouveau/instmem: completely new implementation, as a subdev module v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-14 19:09:17 +10:00
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
drm/nouveau/volt: implement voltage control in core Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-08 09:34:56 +10:00
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
drm/nouveau/dmaobj: update to an improved style of class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-10 04:10:24 +10:00
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
drm/nouveau/fifo: make external class definitions into pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-05 14:26:58 +10:00
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
drm/nouveau/sw: prepare for the sharing of constructors between implementations Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-03 07:30:11 +10:00
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
drm/nv50/disp: preparation for storing static class data Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-02-20 21:33:34 +10:00
device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass;
drm/nouveau/perfmon: initial infrastructure to expose performance counters Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-13 15:29:11 +10:00
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
break;
case 0xaa:
drm/nouveau/device: include the official chipset names Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-27 08:28:20 +10:00
device->cname = "MCP77/MCP78";
drm/nouveau/bios: pull in basic vbios subdev, more to come later v2: Ben Skeggs <bskeggs@redhat.com> - use unaligned macros to access vbios image - endianness fixes Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 10:49:22 +10:00
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
drm/nouveau/gpio: rename g92 class to g94 nv92 hardware has only 16 interrupt lines, while nv94 and later has 32. Accessing 0xe0c{0,4} registers on nv92 can lead to incorrect PDISP setup. This is a regression introduced with commit 9d0f5ec9ee0fd5dc5fc1cc2cf559286431e406e3 Author: Ben Skeggs <bskeggs@redhat.com> Date: Mon May 12 15:22:42 2014 +1000 gpio: split g92 class from nv50 Reported-by: estece on #nouveau Cc: stable@vger.kernel.org # 3.16+ Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-09-08 20:27:57 +01:00
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
drm/nouveau/i2c: start hiding subdev-internal interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-13 13:59:26 +10:00
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
drm/nouveau/subdev: add a pfuse subdev v2 We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-26 00:26:38 +02:00
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
drm/nouveau/clk: rename from clock (no binary change) Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-13 23:37:38 +10:00
device->oclass[NVDEV_SUBDEV_CLK ] = nvaa_clk_oclass;
drm/nouveau/therm: split the nv50 and nv84 code This is needed because temperature management on nv50 can be enabled and it looks about the same as nv40. Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-23 16:45:51 +01:00
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
drm/nouveau/mxm: split up into bios code and a subdev module Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-22 16:41:26 +10:00
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
drm/nv50-/devinit: prevent use of engines marked as disabled by hw/vbios Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-14 16:29:06 +10:00
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
drm/nouveau/mc: store static data in nouveau_mc class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-11 15:34:08 +10:00
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
drm/nouveau/bus: add interfaces/helpers for sequencer Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-15 10:49:39 +10:00
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
drm/nouveau/timer: port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 16:08:25 +10:00
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
drm/nv50-nvaf/fb: split the class definitions up a bit These will diverge further in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-18 14:44:23 +10:00
device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
drm/nouveau/instmem: tidy up the subdev class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-12-23 00:39:47 +10:00
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
drm/nouveau/instmem: completely new implementation, as a subdev module v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-14 19:09:17 +10:00
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
drm/nouveau/volt: implement voltage control in core Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-08 09:34:56 +10:00
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
drm/nouveau/dmaobj: update to an improved style of class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-10 04:10:24 +10:00
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
drm/nouveau/fifo: make external class definitions into pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-05 14:26:58 +10:00
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
drm/nouveau/sw: prepare for the sharing of constructors between implementations Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-03 07:30:11 +10:00
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
drm/nouveau/vdec: fork vp3 implementations from vp2 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-27 14:04:20 +10:00
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
drm/nouveau/vdec: fork vp3 implementations from vp2 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-27 14:04:20 +10:00
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
drm/nv50/disp: preparation for storing static class data Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-02-20 21:33:34 +10:00
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
drm/nouveau/perfmon: initial infrastructure to expose performance counters Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-13 15:29:11 +10:00
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
break;
case 0xac:
drm/nouveau/device: include the official chipset names Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-27 08:28:20 +10:00
device->cname = "MCP79/MCP7A";
drm/nouveau/bios: pull in basic vbios subdev, more to come later v2: Ben Skeggs <bskeggs@redhat.com> - use unaligned macros to access vbios image - endianness fixes Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 10:49:22 +10:00
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
drm/nouveau/gpio: rename g92 class to g94 nv92 hardware has only 16 interrupt lines, while nv94 and later has 32. Accessing 0xe0c{0,4} registers on nv92 can lead to incorrect PDISP setup. This is a regression introduced with commit 9d0f5ec9ee0fd5dc5fc1cc2cf559286431e406e3 Author: Ben Skeggs <bskeggs@redhat.com> Date: Mon May 12 15:22:42 2014 +1000 gpio: split g92 class from nv50 Reported-by: estece on #nouveau Cc: stable@vger.kernel.org # 3.16+ Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-09-08 20:27:57 +01:00
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
drm/nouveau/i2c: start hiding subdev-internal interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-13 13:59:26 +10:00
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
drm/nouveau/subdev: add a pfuse subdev v2 We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-26 00:26:38 +02:00
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
drm/nouveau/clk: rename from clock (no binary change) Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-13 23:37:38 +10:00
device->oclass[NVDEV_SUBDEV_CLK ] = nvaa_clk_oclass;
drm/nouveau/therm: split the nv50 and nv84 code This is needed because temperature management on nv50 can be enabled and it looks about the same as nv40. Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-23 16:45:51 +01:00
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
drm/nouveau/mxm: split up into bios code and a subdev module Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-22 16:41:26 +10:00
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
drm/nv50-/devinit: prevent use of engines marked as disabled by hw/vbios Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-14 16:29:06 +10:00
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
drm/nouveau/mc: store static data in nouveau_mc class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-11 15:34:08 +10:00
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
drm/nouveau/bus: add interfaces/helpers for sequencer Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-15 10:49:39 +10:00
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
drm/nouveau/timer: port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 16:08:25 +10:00
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
drm/nv50-nvaf/fb: split the class definitions up a bit These will diverge further in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-18 14:44:23 +10:00
device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
drm/nouveau/instmem: tidy up the subdev class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-12-23 00:39:47 +10:00
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
drm/nouveau/instmem: completely new implementation, as a subdev module v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-14 19:09:17 +10:00
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
drm/nouveau/volt: implement voltage control in core Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-08 09:34:56 +10:00
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
drm/nouveau/dmaobj: update to an improved style of class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-10 04:10:24 +10:00
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
drm/nouveau/fifo: make external class definitions into pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-05 14:26:58 +10:00
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
drm/nouveau/sw: prepare for the sharing of constructors between implementations Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-03 07:30:11 +10:00
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
drm/nouveau/vdec: fork vp3 implementations from vp2 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-27 14:04:20 +10:00
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
drm/nouveau/vdec: fork vp3 implementations from vp2 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-27 14:04:20 +10:00
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
drm/nv50/disp: preparation for storing static class data Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-02-20 21:33:34 +10:00
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
drm/nouveau/perfmon: initial infrastructure to expose performance counters Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-13 15:29:11 +10:00
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
break;
case 0xa3:
drm/nouveau/device: include the official chipset names Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-27 08:28:20 +10:00
device->cname = "GT215";
drm/nouveau/bios: pull in basic vbios subdev, more to come later v2: Ben Skeggs <bskeggs@redhat.com> - use unaligned macros to access vbios image - endianness fixes Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 10:49:22 +10:00
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
drm/nouveau/gpio: rename g92 class to g94 nv92 hardware has only 16 interrupt lines, while nv94 and later has 32. Accessing 0xe0c{0,4} registers on nv92 can lead to incorrect PDISP setup. This is a regression introduced with commit 9d0f5ec9ee0fd5dc5fc1cc2cf559286431e406e3 Author: Ben Skeggs <bskeggs@redhat.com> Date: Mon May 12 15:22:42 2014 +1000 gpio: split g92 class from nv50 Reported-by: estece on #nouveau Cc: stable@vger.kernel.org # 3.16+ Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-09-08 20:27:57 +01:00
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
drm/nouveau/i2c: start hiding subdev-internal interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-13 13:59:26 +10:00
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
drm/nouveau/subdev: add a pfuse subdev v2 We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-26 00:26:38 +02:00
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
drm/nouveau/clk: rename from clock (no binary change) Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-13 23:37:38 +10:00
device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
drm/nva3/therm: add support for hardware fan tachometer Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-12-04 12:18:59 +10:00
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
drm/nouveau/mxm: split up into bios code and a subdev module Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-22 16:41:26 +10:00
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
drm/nouveau/devinit: tidy up the subdev class definition Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-14 15:55:38 +10:00
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
drm/nouveau/mc: store static data in nouveau_mc class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-11 15:34:08 +10:00
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
drm/nouveau/bus: add interfaces/helpers for sequencer Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-15 10:49:39 +10:00
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
drm/nouveau/timer: port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 16:08:25 +10:00
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
drm/nv50-nvaf/fb: split the class definitions up a bit These will diverge further in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-18 14:44:23 +10:00
device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
drm/nouveau/instmem: tidy up the subdev class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-12-23 00:39:47 +10:00
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
drm/nouveau/instmem: completely new implementation, as a subdev module v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-14 19:09:17 +10:00
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
drm/nouveau/pmu: rename from pwr (no binary change) Switch to NVIDIA's name for the device. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-14 00:04:21 +10:00
device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
drm/nouveau/volt: implement voltage control in core Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-08 09:34:56 +10:00
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
drm/nouveau/dmaobj: update to an improved style of class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-10 04:10:24 +10:00
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
drm/nouveau/fifo: make external class definitions into pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-05 14:26:58 +10:00
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
drm/nouveau/sw: prepare for the sharing of constructors between implementations Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-03 07:30:11 +10:00
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
drm/nouveau/vdec: fork vp3 implementations from vp2 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-27 14:04:20 +10:00
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
drm/nv50/disp: preparation for storing static class data Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-02-20 21:33:34 +10:00
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
drm/nouveau/perfmon: initial infrastructure to expose performance counters Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-13 15:29:11 +10:00
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
break;
case 0xa5:
drm/nouveau/device: include the official chipset names Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-27 08:28:20 +10:00
device->cname = "GT216";
drm/nouveau/bios: pull in basic vbios subdev, more to come later v2: Ben Skeggs <bskeggs@redhat.com> - use unaligned macros to access vbios image - endianness fixes Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 10:49:22 +10:00
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
drm/nouveau/gpio: rename g92 class to g94 nv92 hardware has only 16 interrupt lines, while nv94 and later has 32. Accessing 0xe0c{0,4} registers on nv92 can lead to incorrect PDISP setup. This is a regression introduced with commit 9d0f5ec9ee0fd5dc5fc1cc2cf559286431e406e3 Author: Ben Skeggs <bskeggs@redhat.com> Date: Mon May 12 15:22:42 2014 +1000 gpio: split g92 class from nv50 Reported-by: estece on #nouveau Cc: stable@vger.kernel.org # 3.16+ Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-09-08 20:27:57 +01:00
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
drm/nouveau/i2c: start hiding subdev-internal interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-13 13:59:26 +10:00
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
drm/nouveau/subdev: add a pfuse subdev v2 We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-26 00:26:38 +02:00
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
drm/nouveau/clk: rename from clock (no binary change) Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-13 23:37:38 +10:00
device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
drm/nva3/therm: add support for hardware fan tachometer Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-12-04 12:18:59 +10:00
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
drm/nouveau/mxm: split up into bios code and a subdev module Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-22 16:41:26 +10:00
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
drm/nouveau/devinit: tidy up the subdev class definition Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-14 15:55:38 +10:00
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
drm/nouveau/mc: store static data in nouveau_mc class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-11 15:34:08 +10:00
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
drm/nouveau/bus: add interfaces/helpers for sequencer Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-15 10:49:39 +10:00
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
drm/nouveau/timer: port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 16:08:25 +10:00
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
drm/nv50-nvaf/fb: split the class definitions up a bit These will diverge further in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-18 14:44:23 +10:00
device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
drm/nouveau/instmem: tidy up the subdev class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-12-23 00:39:47 +10:00
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
drm/nouveau/instmem: completely new implementation, as a subdev module v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-14 19:09:17 +10:00
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
drm/nouveau/pmu: rename from pwr (no binary change) Switch to NVIDIA's name for the device. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-14 00:04:21 +10:00
device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
drm/nouveau/volt: implement voltage control in core Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-08 09:34:56 +10:00
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
drm/nouveau/dmaobj: update to an improved style of class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-10 04:10:24 +10:00
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
drm/nouveau/fifo: make external class definitions into pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-05 14:26:58 +10:00
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
drm/nouveau/sw: prepare for the sharing of constructors between implementations Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-03 07:30:11 +10:00
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
drm/nouveau/vdec: fork vp3 implementations from vp2 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-27 14:04:20 +10:00
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
drm/nv50/disp: preparation for storing static class data Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-02-20 21:33:34 +10:00
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
drm/nouveau/perfmon: initial infrastructure to expose performance counters Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-13 15:29:11 +10:00
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
break;
case 0xa8:
drm/nouveau/device: include the official chipset names Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-27 08:28:20 +10:00
device->cname = "GT218";
drm/nouveau/bios: pull in basic vbios subdev, more to come later v2: Ben Skeggs <bskeggs@redhat.com> - use unaligned macros to access vbios image - endianness fixes Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 10:49:22 +10:00
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
drm/nouveau/gpio: rename g92 class to g94 nv92 hardware has only 16 interrupt lines, while nv94 and later has 32. Accessing 0xe0c{0,4} registers on nv92 can lead to incorrect PDISP setup. This is a regression introduced with commit 9d0f5ec9ee0fd5dc5fc1cc2cf559286431e406e3 Author: Ben Skeggs <bskeggs@redhat.com> Date: Mon May 12 15:22:42 2014 +1000 gpio: split g92 class from nv50 Reported-by: estece on #nouveau Cc: stable@vger.kernel.org # 3.16+ Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-09-08 20:27:57 +01:00
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
drm/nouveau/i2c: start hiding subdev-internal interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-13 13:59:26 +10:00
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
drm/nouveau/subdev: add a pfuse subdev v2 We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-26 00:26:38 +02:00
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
drm/nouveau/clk: rename from clock (no binary change) Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-13 23:37:38 +10:00
device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
drm/nva3/therm: add support for hardware fan tachometer Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-12-04 12:18:59 +10:00
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
drm/nouveau/mxm: split up into bios code and a subdev module Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-22 16:41:26 +10:00
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
drm/nouveau/devinit: tidy up the subdev class definition Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-14 15:55:38 +10:00
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
drm/nouveau/mc: store static data in nouveau_mc class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-11 15:34:08 +10:00
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
drm/nouveau/bus: add interfaces/helpers for sequencer Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-15 10:49:39 +10:00
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
drm/nouveau/timer: port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 16:08:25 +10:00
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
drm/nv50-nvaf/fb: split the class definitions up a bit These will diverge further in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-18 14:44:23 +10:00
device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
drm/nouveau/instmem: tidy up the subdev class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-12-23 00:39:47 +10:00
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
drm/nouveau/instmem: completely new implementation, as a subdev module v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-14 19:09:17 +10:00
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
drm/nouveau/pmu: rename from pwr (no binary change) Switch to NVIDIA's name for the device. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-14 00:04:21 +10:00
device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
drm/nouveau/volt: implement voltage control in core Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-08 09:34:56 +10:00
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
drm/nouveau/dmaobj: update to an improved style of class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-10 04:10:24 +10:00
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
drm/nouveau/fifo: make external class definitions into pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-05 14:26:58 +10:00
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
drm/nouveau/sw: prepare for the sharing of constructors between implementations Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-03 07:30:11 +10:00
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
drm/nouveau/vdec: fork vp3 implementations from vp2 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-27 14:04:20 +10:00
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
drm/nv50/disp: preparation for storing static class data Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-02-20 21:33:34 +10:00
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
drm/nouveau/perfmon: initial infrastructure to expose performance counters Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-13 15:29:11 +10:00
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
break;
case 0xaf:
drm/nouveau/device: include the official chipset names Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-27 08:28:20 +10:00
device->cname = "MCP89";
drm/nouveau/bios: pull in basic vbios subdev, more to come later v2: Ben Skeggs <bskeggs@redhat.com> - use unaligned macros to access vbios image - endianness fixes Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-10 10:49:22 +10:00
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
drm/nouveau/gpio: rename g92 class to g94 nv92 hardware has only 16 interrupt lines, while nv94 and later has 32. Accessing 0xe0c{0,4} registers on nv92 can lead to incorrect PDISP setup. This is a regression introduced with commit 9d0f5ec9ee0fd5dc5fc1cc2cf559286431e406e3 Author: Ben Skeggs <bskeggs@redhat.com> Date: Mon May 12 15:22:42 2014 +1000 gpio: split g92 class from nv50 Reported-by: estece on #nouveau Cc: stable@vger.kernel.org # 3.16+ Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-09-08 20:27:57 +01:00
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
drm/nouveau/i2c: start hiding subdev-internal interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-13 13:59:26 +10:00
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
drm/nouveau/subdev: add a pfuse subdev v2 We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-26 00:26:38 +02:00
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
drm/nouveau/clk: rename from clock (no binary change) Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-13 23:37:38 +10:00
device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
drm/nva3/therm: add support for hardware fan tachometer Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-12-04 12:18:59 +10:00
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
drm/nouveau/mxm: split up into bios code and a subdev module Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-22 16:41:26 +10:00
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
drm/nv50-/devinit: prevent use of engines marked as disabled by hw/vbios Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-14 16:29:06 +10:00
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass;
drm/nouveau/mc: store static data in nouveau_mc class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-11 15:34:08 +10:00
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
drm/nouveau/bus: add interfaces/helpers for sequencer Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-15 10:49:39 +10:00
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
drm/nouveau/timer: port to subdev interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-11 16:08:25 +10:00
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
drm/nv50-nvaf/fb: split the class definitions up a bit These will diverge further in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-18 14:44:23 +10:00
device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass;
drm/nouveau/instmem: tidy up the subdev class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-12-23 00:39:47 +10:00
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
drm/nouveau/instmem: completely new implementation, as a subdev module v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-14 19:09:17 +10:00
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
drm/nouveau/pmu: rename from pwr (no binary change) Switch to NVIDIA's name for the device. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-14 00:04:21 +10:00
device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
drm/nouveau/volt: implement voltage control in core Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-08 09:34:56 +10:00
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
drm/nouveau/dmaobj: update to an improved style of class definition Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-08-10 04:10:24 +10:00
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
drm/nouveau/fifo: make external class definitions into pointers Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-05 14:26:58 +10:00
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
drm/nouveau/sw: prepare for the sharing of constructors between implementations Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-10-03 07:30:11 +10:00
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
drm/nouveau/vdec: fork vp3 implementations from vp2 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-27 14:04:20 +10:00
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-20 08:17:34 +10:00
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
drm/nv50/disp: preparation for storing static class data Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-02-20 21:33:34 +10:00
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
drm/nouveau/perfmon: initial infrastructure to expose performance counters Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-13 15:29:11 +10:00
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
drm/nouveau/core: pull in most of the new core infrastructure This commit provides most of the infrastructure to support a major overhaul of Nouveau's internals coming in the following commits. This work aims to take all the things we've learned over the last several years, and turn that into a cleaner architecture that's more maintainable going forward. RAMHT and MM bits of the new core have been left out for the moment, and will be pulled in as I go through the process of porting the code to become either subdev or engine modules. There are several main goals I wanted to achieve through this work: -- Reduce complexity The goal here was to make each component of the driver as independent as possible, which will ease maintainability and readability, and provide a good base for resetting locked up GPU units in the future. -- Better tracking of GPU units that are required at any given time This is for future PM work, we'll be able to tell exactly what parts of the GPU we need powered at any given point (etc). -- Expose all available NVIDIA GPUs to the client In order to support things such as multi-GPU channels, we want to be able to expose all the NVIDIA GPUs to the client over a single file descriptor so it can send a single push buffer to multiple GPUs. -- Untangle the core hardware support code from the DRM implementation This happened initially as an unexpected side-effect of developing the initial core infrastructure in userspace, but it turned into a goal of the whole project. Initial benefits will be the availablility of a number of userspace tools and tests using the same code as the driver itself, but will also be important as I look into some virtualisation ideas. v2: Ben Skeggs <bskeggs@redhat.com> - fix duplicate assignments noticed by clang - implement some forgotten yelling in error path - ensure 64-bit engine mask is used everywhere v3: Marcin Slusarz <marcin.slusarz@gmail.com> - sparse fixes - inline nv_printk into nv_assert to prevent recursive inlining issues v4: Ben Skeggs <bskeggs@redhat.com> - fixed minor memory leak on gpuobj destruction Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-07-06 07:36:43 +10:00
break;
default:
nv_fatal(device, "unknown Tesla chipset\n");
return -EINVAL;
}
return 0;
}
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