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										 |  |  | /*
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							|  |  |  |  * Copyright © 2008 Intel Corporation | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * Permission is hereby granted, free of charge, to any person obtaining a | 
					
						
							|  |  |  |  * copy of this software and associated documentation files (the "Software"), | 
					
						
							|  |  |  |  * to deal in the Software without restriction, including without limitation | 
					
						
							|  |  |  |  * the rights to use, copy, modify, merge, publish, distribute, sublicense, | 
					
						
							|  |  |  |  * and/or sell copies of the Software, and to permit persons to whom the | 
					
						
							|  |  |  |  * Software is furnished to do so, subject to the following conditions: | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * The above copyright notice and this permission notice (including the next | 
					
						
							|  |  |  |  * paragraph) shall be included in all copies or substantial portions of the | 
					
						
							|  |  |  |  * Software. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | 
					
						
							|  |  |  |  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | 
					
						
							|  |  |  |  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL | 
					
						
							|  |  |  |  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | 
					
						
							|  |  |  |  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | 
					
						
							|  |  |  |  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | 
					
						
							|  |  |  |  * IN THE SOFTWARE. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * Authors: | 
					
						
							|  |  |  |  *    Keith Packard <keithp@keithp.com> | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | 
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											2012-10-02 18:01:07 +01:00
										 |  |  | #include <drm/drmP.h>
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							|  |  |  | #include <drm/i915_drm.h>
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										 |  |  | #include "i915_drv.h"
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							|  |  |  | 
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										 |  |  | #if WATCH_LISTS
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							|  |  |  | int | 
					
						
							|  |  |  | i915_verify_lists(struct drm_device *dev) | 
					
						
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										 |  |  | { | 
					
						
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										 |  |  | 	static int warned; | 
					
						
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										 |  |  | 	struct drm_i915_private *dev_priv = dev->dev_private; | 
					
						
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										 |  |  | 	struct drm_i915_gem_object *obj; | 
					
						
							|  |  |  | 	int err = 0; | 
					
						
							|  |  |  | 
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							|  |  |  | 	if (warned) | 
					
						
							|  |  |  | 		return 0; | 
					
						
							|  |  |  | 
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							|  |  |  | 	list_for_each_entry(obj, &dev_priv->render_ring.active_list, list) { | 
					
						
							|  |  |  | 		if (obj->base.dev != dev || | 
					
						
							|  |  |  | 		    !atomic_read(&obj->base.refcount.refcount)) { | 
					
						
							|  |  |  | 			DRM_ERROR("freed render active %p\n", obj); | 
					
						
							|  |  |  | 			err++; | 
					
						
							|  |  |  | 			break; | 
					
						
							|  |  |  | 		} else if (!obj->active || | 
					
						
							|  |  |  | 			   (obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) { | 
					
						
							|  |  |  | 			DRM_ERROR("invalid render active %p (a %d r %x)\n", | 
					
						
							|  |  |  | 				  obj, | 
					
						
							|  |  |  | 				  obj->active, | 
					
						
							|  |  |  | 				  obj->base.read_domains); | 
					
						
							|  |  |  | 			err++; | 
					
						
							|  |  |  | 		} else if (obj->base.write_domain && list_empty(&obj->gpu_write_list)) { | 
					
						
							|  |  |  | 			DRM_ERROR("invalid render active %p (w %x, gwl %d)\n", | 
					
						
							|  |  |  | 				  obj, | 
					
						
							|  |  |  | 				  obj->base.write_domain, | 
					
						
							|  |  |  | 				  !list_empty(&obj->gpu_write_list)); | 
					
						
							|  |  |  | 			err++; | 
					
						
							|  |  |  | 		} | 
					
						
							|  |  |  | 	} | 
					
						
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							|  |  |  | 	list_for_each_entry(obj, &dev_priv->mm.flushing_list, list) { | 
					
						
							|  |  |  | 		if (obj->base.dev != dev || | 
					
						
							|  |  |  | 		    !atomic_read(&obj->base.refcount.refcount)) { | 
					
						
							|  |  |  | 			DRM_ERROR("freed flushing %p\n", obj); | 
					
						
							|  |  |  | 			err++; | 
					
						
							|  |  |  | 			break; | 
					
						
							|  |  |  | 		} else if (!obj->active || | 
					
						
							|  |  |  | 			   (obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0 || | 
					
						
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										 |  |  | 			   list_empty(&obj->gpu_write_list)) { | 
					
						
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										 |  |  | 			DRM_ERROR("invalid flushing %p (a %d w %x gwl %d)\n", | 
					
						
							|  |  |  | 				  obj, | 
					
						
							|  |  |  | 				  obj->active, | 
					
						
							|  |  |  | 				  obj->base.write_domain, | 
					
						
							|  |  |  | 				  !list_empty(&obj->gpu_write_list)); | 
					
						
							|  |  |  | 			err++; | 
					
						
							|  |  |  | 		} | 
					
						
							|  |  |  | 	} | 
					
						
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							|  |  |  | 	list_for_each_entry(obj, &dev_priv->mm.gpu_write_list, gpu_write_list) { | 
					
						
							|  |  |  | 		if (obj->base.dev != dev || | 
					
						
							|  |  |  | 		    !atomic_read(&obj->base.refcount.refcount)) { | 
					
						
							|  |  |  | 			DRM_ERROR("freed gpu write %p\n", obj); | 
					
						
							|  |  |  | 			err++; | 
					
						
							|  |  |  | 			break; | 
					
						
							|  |  |  | 		} else if (!obj->active || | 
					
						
							|  |  |  | 			   (obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) { | 
					
						
							|  |  |  | 			DRM_ERROR("invalid gpu write %p (a %d w %x)\n", | 
					
						
							|  |  |  | 				  obj, | 
					
						
							|  |  |  | 				  obj->active, | 
					
						
							|  |  |  | 				  obj->base.write_domain); | 
					
						
							|  |  |  | 			err++; | 
					
						
							|  |  |  | 		} | 
					
						
							|  |  |  | 	} | 
					
						
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										 |  |  | 	list_for_each_entry(obj, &i915_gtt_vm->inactive_list, list) { | 
					
						
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										 |  |  | 		if (obj->base.dev != dev || | 
					
						
							|  |  |  | 		    !atomic_read(&obj->base.refcount.refcount)) { | 
					
						
							|  |  |  | 			DRM_ERROR("freed inactive %p\n", obj); | 
					
						
							|  |  |  | 			err++; | 
					
						
							|  |  |  | 			break; | 
					
						
							|  |  |  | 		} else if (obj->pin_count || obj->active || | 
					
						
							|  |  |  | 			   (obj->base.write_domain & I915_GEM_GPU_DOMAINS)) { | 
					
						
							|  |  |  | 			DRM_ERROR("invalid inactive %p (p %d a %d w %x)\n", | 
					
						
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										 |  |  | 				  obj, | 
					
						
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										 |  |  | 				  obj->pin_count, obj->active, | 
					
						
							|  |  |  | 				  obj->base.write_domain); | 
					
						
							|  |  |  | 			err++; | 
					
						
							|  |  |  | 		} | 
					
						
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										 |  |  | 	} | 
					
						
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										 |  |  | 
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							|  |  |  | 	return warned = err; | 
					
						
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										 |  |  | } | 
					
						
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										 |  |  | #endif /* WATCH_LIST */
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