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glider/pcb/mainboard/pcb.kicad_pro
Wenting Zhang 40d2564772 pcb: r0p5
2022-11-20 21:59:07 -05:00

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{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.12,
"silk_text_italic": false,
"silk_text_size_h": 0.7,
"silk_text_size_v": 0.7,
"silk_text_thickness": 0.09999999999999999,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.11
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [
"clearance|111375000|70787500|8043308d-7c45-4b18-b445-5e6c4387d7b4|a85ba101-eea1-4cbe-a2a6-47823743aeb3",
"clearance|111425000|71350000|b54c3c8d-e9c4-411e-aa64-48334be98732|a85ba101-eea1-4cbe-a2a6-47823743aeb3"
],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "warning",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "error",
"silk_overlap": "error",
"skew_out_of_range": "error",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.024999999999999998,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.09999999999999999,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.44999999999999996,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"use_height_for_length_calcs": true
},
"track_widths": [
0.0,
0.1,
0.11,
0.12,
0.13,
0.15,
0.2,
0.3,
0.5,
0.6,
1.0
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.46,
"drill": 0.2
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
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],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "pcb.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.11,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.11,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.11,
"diff_pair_gap": 0.11,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.15,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "DP",
"nets": [
"/dp_in/DP0N",
"/dp_in/DP0P",
"/dp_in/DP1N",
"/dp_in/DP1P",
"/dp_in/DPAUXN",
"/dp_in/DPAUXP",
"/dp_in/RX1N",
"/dp_in/RX1NC",
"/dp_in/RX1P",
"/dp_in/RX1PC",
"/dp_in/RX2N",
"/dp_in/RX2NC",
"/dp_in/RX2P",
"/dp_in/RX2PC",
"/dp_in/TX1N",
"/dp_in/TX1NC",
"/dp_in/TX1P",
"/dp_in/TX1PC",
"/dp_in/TX2N",
"/dp_in/TX2NC",
"/dp_in/TX2P",
"/dp_in/TX2PC"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.11,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "EPD",
"nets": [
"/eink/ED0",
"/eink/ED1",
"/eink/ED10",
"/eink/ED11",
"/eink/ED12",
"/eink/ED13",
"/eink/ED14",
"/eink/ED15",
"/eink/ED2",
"/eink/ED3",
"/eink/ED4",
"/eink/ED5",
"/eink/ED6",
"/eink/ED7",
"/eink/ED8",
"/eink/ED9",
"/eink/ESDCLK",
"/eink/ESDLE",
"/eink/ESDOE",
"EPDC_D0",
"EPDC_D1",
"EPDC_D10",
"EPDC_D11",
"EPDC_D12",
"EPDC_D13",
"EPDC_D14",
"EPDC_D15",
"EPDC_D2",
"EPDC_D3",
"EPDC_D4",
"EPDC_D5",
"EPDC_D6",
"EPDC_D7",
"EPDC_D8",
"EPDC_D9",
"EPDC_GDCLK",
"EPDC_GDOE",
"EPDC_GDSP",
"EPDC_SDCE0",
"EPDC_SDCLK",
"EPDC_SDLE",
"EPDC_SDOE"
],
"pcb_color": "rgb(255, 0, 191)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.11,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.11,
"diff_pair_gap": 0.11,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.15,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "LVDS",
"nets": [
"LVDS_EVEN_AN",
"LVDS_EVEN_AP",
"LVDS_EVEN_BN",
"LVDS_EVEN_BP",
"LVDS_EVEN_CN",
"LVDS_EVEN_CP",
"LVDS_ODD_AN",
"LVDS_ODD_AP",
"LVDS_ODD_BN",
"LVDS_ODD_BP",
"LVDS_ODD_CKN",
"LVDS_ODD_CKP",
"LVDS_ODD_CN",
"LVDS_ODD_CP"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.1,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "SDRAM_A",
"nets": [
"/fpga_ddr/DRAM_ADDR0",
"/fpga_ddr/DRAM_ADDR1",
"/fpga_ddr/DRAM_ADDR10",
"/fpga_ddr/DRAM_ADDR11",
"/fpga_ddr/DRAM_ADDR12",
"/fpga_ddr/DRAM_ADDR13",
"/fpga_ddr/DRAM_ADDR14",
"/fpga_ddr/DRAM_ADDR2",
"/fpga_ddr/DRAM_ADDR3",
"/fpga_ddr/DRAM_ADDR4",
"/fpga_ddr/DRAM_ADDR5",
"/fpga_ddr/DRAM_ADDR6",
"/fpga_ddr/DRAM_ADDR7",
"/fpga_ddr/DRAM_ADDR8",
"/fpga_ddr/DRAM_ADDR9",
"/fpga_ddr/DRAM_BA0",
"/fpga_ddr/DRAM_BA1",
"/fpga_ddr/DRAM_BA2",
"/fpga_ddr/DRAM_CASB",
"/fpga_ddr/DRAM_CKE",
"/fpga_ddr/DRAM_CKN",
"/fpga_ddr/DRAM_CKP",
"/fpga_ddr/DRAM_CSB",
"/fpga_ddr/DRAM_ODT",
"/fpga_ddr/DRAM_RASB",
"/fpga_ddr/DRAM_RST",
"/fpga_ddr/DRAM_WEB"
],
"pcb_color": "rgb(103, 255, 0)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
},
{
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"clearance": 0.1,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "SDRAM_H",
"nets": [
"/fpga_ddr/DRAM_DATA10",
"/fpga_ddr/DRAM_DATA11",
"/fpga_ddr/DRAM_DATA12",
"/fpga_ddr/DRAM_DATA13",
"/fpga_ddr/DRAM_DATA14",
"/fpga_ddr/DRAM_DATA15",
"/fpga_ddr/DRAM_DATA8",
"/fpga_ddr/DRAM_DATA9",
"/fpga_ddr/DRAM_UDM",
"/fpga_ddr/DRAM_UDQSN",
"/fpga_ddr/DRAM_UDQSP"
],
"pcb_color": "rgb(255, 252, 0)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
},
{
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"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "SDRAM_L",
"nets": [
"/fpga_ddr/DRAM_DATA0",
"/fpga_ddr/DRAM_DATA1",
"/fpga_ddr/DRAM_DATA2",
"/fpga_ddr/DRAM_DATA3",
"/fpga_ddr/DRAM_DATA4",
"/fpga_ddr/DRAM_DATA5",
"/fpga_ddr/DRAM_DATA6",
"/fpga_ddr/DRAM_DATA7",
"/fpga_ddr/DRAM_LDM",
"/fpga_ddr/DRAM_LDQSN",
"/fpga_ddr/DRAM_LDQSP"
],
"pcb_color": "rgb(255, 131, 3)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.11,
"diff_pair_gap": 0.11,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.18,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "USB",
"nets": [],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": {
"+1V1": "rgb(255, 92, 56)",
"+1V35": "rgb(185, 61, 143)",
"+3V3": "rgb(179, 228, 50)",
"+5V": "rgb(255, 122, 107)",
"GND": "rgb(0, 94, 255)"
}
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 400,
"drawing": {
"default_bus_thickness": 12.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "./",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"4654897e-3e2f-4522-96c3-20b19803c088",
""
],
[
"0606a719-6980-4867-837f-aa642737d361",
"power"
],
[
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"fpga"
],
[
"b1d5941d-0481-47a2-a434-0b8e587a166a",
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[
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[
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"dp_in"
],
[
"f69cfcc8-f979-4315-84ee-316a84fb66a2",
"mcu"
]
],
"text_variables": {}
}
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