2022-03-05 21:48:31 +00:00
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{
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"board": {
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.049999999999999996,
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"copper_line_width": 0.19999999999999998,
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"dimension_units": 3,
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"dimensions": {
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"arrow_length": 1270000,
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},
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"fab_line_width": 0.09999999999999999,
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"fab_text_italic": false,
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"other_line_width": 0.09999999999999999,
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"pads": {
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"height": 1.524,
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"width": 1.524
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},
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"silk_line_width": 0.12,
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"silk_text_italic": false,
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2022-07-04 02:44:02 +00:00
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"silk_text_size_h": 0.7,
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"silk_text_size_v": 0.7,
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"silk_text_thickness": 0.09999999999999999,
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2022-03-05 21:48:31 +00:00
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"silk_text_upright": false,
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"zones": {
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"min_clearance": 0.11
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}
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},
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{
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"gap": 0.0,
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"width": 0.0
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}
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],
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"drc_exclusions": [
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"clearance|111375000|70787500|8043308d-7c45-4b18-b445-5e6c4387d7b4|a85ba101-eea1-4cbe-a2a6-47823743aeb3",
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"clearance|111425000|71350000|b54c3c8d-e9c4-411e-aa64-48334be98732|a85ba101-eea1-4cbe-a2a6-47823743aeb3"
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],
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"meta": {
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"version": 2
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},
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"rule_severities": {
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"annular_width": "error",
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"clearance": "error",
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"copper_edge_clearance": "error",
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"courtyards_overlap": "warning",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"footprint_type_mismatch": "error",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"invalid_outline": "error",
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"item_on_disabled_layer": "error",
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"items_not_allowed": "error",
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"length_out_of_range": "error",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"net_conflict": "warning",
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"npth_inside_courtyard": "ignore",
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"padstack": "error",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"silk_over_copper": "error",
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"silk_overlap": "error",
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"skew_out_of_range": "error",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"track_dangling": "warning",
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"track_width": "error",
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"tracks_crossing": "error",
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"unconnected_items": "error",
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"unresolved_variable": "error",
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"via_dangling": "warning",
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"zone_has_empty_net": "error",
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"zones_intersect": "error"
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},
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"rules": {
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"allow_blind_buried_vias": false,
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"max_error": 0.005,
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"min_clearance": 0.0,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.19999999999999998,
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"min_via_diameter": 0.44999999999999996,
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"solder_mask_clearance": 0.0,
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"solder_mask_min_width": 0.0,
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"use_height_for_length_calcs": true
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},
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"track_widths": [
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0.0,
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0.11,
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0.12,
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0.6,
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1.0
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"via_dimensions": [
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{
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"diameter": 0.0,
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{
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"diameter": 0.46,
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}
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"zones_allow_external_fillets": false,
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"zones_use_no_outline": true
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"boards": [],
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"erc": {
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"erc_exclusions": [],
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"meta": {
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"version": 0
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"rule_severities": {
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"bus_definition_conflict": "error",
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"bus_entry_needed": "error",
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"bus_label_syntax": "error",
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"bus_to_bus_conflict": "error",
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"bus_to_net_conflict": "error",
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"different_unit_footprint": "error",
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"different_unit_net": "error",
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"duplicate_reference": "error",
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"duplicate_sheet_names": "error",
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"extra_units": "error",
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"global_label_dangling": "warning",
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"hier_label_mismatch": "error",
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"label_dangling": "error",
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"lib_symbol_issues": "warning",
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"multiple_net_names": "warning",
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"net_not_bus_member": "warning",
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"no_connect_connected": "warning",
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"no_connect_dangling": "warning",
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"pin_not_connected": "error",
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"pin_not_driven": "error",
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"pin_to_pin": "warning",
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"power_pin_not_driven": "error",
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"similar_labels": "warning",
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"unannotated": "error",
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"unit_value_mismatch": "error",
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"unresolved_variable": "error",
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|
|
"wire_dangling": "error"
|
|
|
|
|
}
|
|
|
|
|
},
|
|
|
|
|
"libraries": {
|
|
|
|
|
"pinned_footprint_libs": [],
|
|
|
|
|
"pinned_symbol_libs": []
|
|
|
|
|
},
|
|
|
|
|
"meta": {
|
|
|
|
|
"filename": "pcb.kicad_pro",
|
|
|
|
|
"version": 1
|
|
|
|
|
},
|
|
|
|
|
"net_settings": {
|
|
|
|
|
"classes": [
|
|
|
|
|
{
|
|
|
|
|
"bus_width": 12.0,
|
2022-07-04 02:44:02 +00:00
|
|
|
"clearance": 0.11,
|
2022-03-05 21:48:31 +00:00
|
|
|
"diff_pair_gap": 0.1,
|
|
|
|
|
"diff_pair_via_gap": 0.25,
|
|
|
|
|
"diff_pair_width": 0.2,
|
|
|
|
|
"line_style": 0,
|
|
|
|
|
"microvia_diameter": 0.3,
|
|
|
|
|
"microvia_drill": 0.1,
|
|
|
|
|
"name": "Default",
|
|
|
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"track_width": 0.11,
|
|
|
|
|
"via_diameter": 0.45,
|
|
|
|
|
"via_drill": 0.2,
|
|
|
|
|
"wire_width": 6.0
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"bus_width": 12.0,
|
2022-07-04 02:44:02 +00:00
|
|
|
"clearance": 0.11,
|
|
|
|
|
"diff_pair_gap": 0.11,
|
2022-03-05 21:48:31 +00:00
|
|
|
"diff_pair_via_gap": 0.25,
|
2022-07-04 02:44:02 +00:00
|
|
|
"diff_pair_width": 0.15,
|
2022-03-05 21:48:31 +00:00
|
|
|
"line_style": 0,
|
|
|
|
|
"microvia_diameter": 0.3,
|
|
|
|
|
"microvia_drill": 0.1,
|
|
|
|
|
"name": "DP",
|
|
|
|
|
"nets": [
|
|
|
|
|
"/dp_in/DP0N",
|
|
|
|
|
"/dp_in/DP0P",
|
|
|
|
|
"/dp_in/DP1N",
|
|
|
|
|
"/dp_in/DP1P",
|
|
|
|
|
"/dp_in/DPAUXN",
|
2022-07-04 02:44:02 +00:00
|
|
|
"/dp_in/DPAUXP",
|
|
|
|
|
"/dp_in/RX1N",
|
|
|
|
|
"/dp_in/RX1NC",
|
|
|
|
|
"/dp_in/RX1P",
|
|
|
|
|
"/dp_in/RX1PC",
|
|
|
|
|
"/dp_in/RX2N",
|
|
|
|
|
"/dp_in/RX2NC",
|
|
|
|
|
"/dp_in/RX2P",
|
|
|
|
|
"/dp_in/RX2PC",
|
|
|
|
|
"/dp_in/TX1N",
|
|
|
|
|
"/dp_in/TX1NC",
|
|
|
|
|
"/dp_in/TX1P",
|
|
|
|
|
"/dp_in/TX1PC",
|
|
|
|
|
"/dp_in/TX2N",
|
|
|
|
|
"/dp_in/TX2NC",
|
|
|
|
|
"/dp_in/TX2P",
|
|
|
|
|
"/dp_in/TX2PC"
|
2022-03-05 21:48:31 +00:00
|
|
|
],
|
|
|
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"track_width": 0.15,
|
|
|
|
|
"via_diameter": 0.45,
|
|
|
|
|
"via_drill": 0.2,
|
|
|
|
|
"wire_width": 6.0
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"bus_width": 12.0,
|
2022-07-04 02:44:02 +00:00
|
|
|
"clearance": 0.11,
|
2022-03-05 21:48:31 +00:00
|
|
|
"diff_pair_gap": 0.25,
|
|
|
|
|
"diff_pair_via_gap": 0.25,
|
|
|
|
|
"diff_pair_width": 0.2,
|
|
|
|
|
"line_style": 0,
|
|
|
|
|
"microvia_diameter": 0.3,
|
|
|
|
|
"microvia_drill": 0.1,
|
|
|
|
|
"name": "EPD",
|
|
|
|
|
"nets": [
|
|
|
|
|
"/eink/ED0",
|
|
|
|
|
"/eink/ED1",
|
|
|
|
|
"/eink/ED10",
|
|
|
|
|
"/eink/ED11",
|
|
|
|
|
"/eink/ED12",
|
|
|
|
|
"/eink/ED13",
|
|
|
|
|
"/eink/ED14",
|
|
|
|
|
"/eink/ED15",
|
|
|
|
|
"/eink/ED2",
|
|
|
|
|
"/eink/ED3",
|
|
|
|
|
"/eink/ED4",
|
|
|
|
|
"/eink/ED5",
|
|
|
|
|
"/eink/ED6",
|
|
|
|
|
"/eink/ED7",
|
|
|
|
|
"/eink/ED8",
|
|
|
|
|
"/eink/ED9",
|
|
|
|
|
"/eink/ESDCLK",
|
|
|
|
|
"/eink/ESDLE",
|
|
|
|
|
"/eink/ESDOE",
|
|
|
|
|
"EPDC_D0",
|
|
|
|
|
"EPDC_D1",
|
|
|
|
|
"EPDC_D10",
|
|
|
|
|
"EPDC_D11",
|
|
|
|
|
"EPDC_D12",
|
|
|
|
|
"EPDC_D13",
|
|
|
|
|
"EPDC_D14",
|
|
|
|
|
"EPDC_D15",
|
|
|
|
|
"EPDC_D2",
|
|
|
|
|
"EPDC_D3",
|
|
|
|
|
"EPDC_D4",
|
|
|
|
|
"EPDC_D5",
|
|
|
|
|
"EPDC_D6",
|
|
|
|
|
"EPDC_D7",
|
|
|
|
|
"EPDC_D8",
|
|
|
|
|
"EPDC_D9",
|
|
|
|
|
"EPDC_GDCLK",
|
|
|
|
|
"EPDC_GDOE",
|
|
|
|
|
"EPDC_GDSP",
|
|
|
|
|
"EPDC_SDCE0",
|
|
|
|
|
"EPDC_SDCLK",
|
|
|
|
|
"EPDC_SDLE",
|
|
|
|
|
"EPDC_SDOE"
|
|
|
|
|
],
|
|
|
|
|
"pcb_color": "rgb(255, 0, 191)",
|
|
|
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"track_width": 0.11,
|
|
|
|
|
"via_diameter": 0.45,
|
|
|
|
|
"via_drill": 0.2,
|
|
|
|
|
"wire_width": 6.0
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"bus_width": 12.0,
|
2022-07-04 02:44:02 +00:00
|
|
|
"clearance": 0.11,
|
|
|
|
|
"diff_pair_gap": 0.11,
|
2022-03-05 21:48:31 +00:00
|
|
|
"diff_pair_via_gap": 0.25,
|
2022-07-04 02:44:02 +00:00
|
|
|
"diff_pair_width": 0.15,
|
2022-03-05 21:48:31 +00:00
|
|
|
"line_style": 0,
|
|
|
|
|
"microvia_diameter": 0.3,
|
|
|
|
|
"microvia_drill": 0.1,
|
2022-07-04 02:44:02 +00:00
|
|
|
"name": "LVDS",
|
|
|
|
|
"nets": [
|
|
|
|
|
"LVDS_EVEN_AN",
|
|
|
|
|
"LVDS_EVEN_AP",
|
|
|
|
|
"LVDS_EVEN_BN",
|
|
|
|
|
"LVDS_EVEN_BP",
|
|
|
|
|
"LVDS_EVEN_CN",
|
|
|
|
|
"LVDS_EVEN_CP",
|
|
|
|
|
"LVDS_ODD_AN",
|
|
|
|
|
"LVDS_ODD_AP",
|
|
|
|
|
"LVDS_ODD_BN",
|
|
|
|
|
"LVDS_ODD_BP",
|
|
|
|
|
"LVDS_ODD_CKN",
|
|
|
|
|
"LVDS_ODD_CKP",
|
|
|
|
|
"LVDS_ODD_CN",
|
|
|
|
|
"LVDS_ODD_CP"
|
|
|
|
|
],
|
2022-03-05 21:48:31 +00:00
|
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"track_width": 0.15,
|
|
|
|
|
"via_diameter": 0.45,
|
|
|
|
|
"via_drill": 0.2,
|
|
|
|
|
"wire_width": 6.0
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"bus_width": 12.0,
|
|
|
|
|
"clearance": 0.1,
|
|
|
|
|
"diff_pair_gap": 0.1,
|
|
|
|
|
"diff_pair_via_gap": 0.25,
|
|
|
|
|
"diff_pair_width": 0.1,
|
|
|
|
|
"line_style": 0,
|
|
|
|
|
"microvia_diameter": 0.3,
|
|
|
|
|
"microvia_drill": 0.1,
|
|
|
|
|
"name": "SDRAM_A",
|
|
|
|
|
"nets": [
|
|
|
|
|
"/fpga_ddr/DRAM_ADDR0",
|
|
|
|
|
"/fpga_ddr/DRAM_ADDR1",
|
|
|
|
|
"/fpga_ddr/DRAM_ADDR10",
|
|
|
|
|
"/fpga_ddr/DRAM_ADDR11",
|
|
|
|
|
"/fpga_ddr/DRAM_ADDR12",
|
|
|
|
|
"/fpga_ddr/DRAM_ADDR13",
|
|
|
|
|
"/fpga_ddr/DRAM_ADDR14",
|
|
|
|
|
"/fpga_ddr/DRAM_ADDR2",
|
|
|
|
|
"/fpga_ddr/DRAM_ADDR3",
|
|
|
|
|
"/fpga_ddr/DRAM_ADDR4",
|
|
|
|
|
"/fpga_ddr/DRAM_ADDR5",
|
|
|
|
|
"/fpga_ddr/DRAM_ADDR6",
|
|
|
|
|
"/fpga_ddr/DRAM_ADDR7",
|
|
|
|
|
"/fpga_ddr/DRAM_ADDR8",
|
|
|
|
|
"/fpga_ddr/DRAM_ADDR9",
|
|
|
|
|
"/fpga_ddr/DRAM_BA0",
|
|
|
|
|
"/fpga_ddr/DRAM_BA1",
|
|
|
|
|
"/fpga_ddr/DRAM_BA2",
|
|
|
|
|
"/fpga_ddr/DRAM_CASB",
|
|
|
|
|
"/fpga_ddr/DRAM_CKE",
|
|
|
|
|
"/fpga_ddr/DRAM_CKN",
|
|
|
|
|
"/fpga_ddr/DRAM_CKP",
|
|
|
|
|
"/fpga_ddr/DRAM_CSB",
|
|
|
|
|
"/fpga_ddr/DRAM_ODT",
|
|
|
|
|
"/fpga_ddr/DRAM_RASB",
|
|
|
|
|
"/fpga_ddr/DRAM_RST",
|
|
|
|
|
"/fpga_ddr/DRAM_WEB"
|
|
|
|
|
],
|
|
|
|
|
"pcb_color": "rgb(103, 255, 0)",
|
|
|
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"track_width": 0.1,
|
|
|
|
|
"via_diameter": 0.45,
|
|
|
|
|
"via_drill": 0.2,
|
|
|
|
|
"wire_width": 6.0
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"bus_width": 12.0,
|
|
|
|
|
"clearance": 0.1,
|
|
|
|
|
"diff_pair_gap": 0.1,
|
|
|
|
|
"diff_pair_via_gap": 0.25,
|
|
|
|
|
"diff_pair_width": 0.1,
|
|
|
|
|
"line_style": 0,
|
|
|
|
|
"microvia_diameter": 0.3,
|
|
|
|
|
"microvia_drill": 0.1,
|
|
|
|
|
"name": "SDRAM_H",
|
|
|
|
|
"nets": [
|
|
|
|
|
"/fpga_ddr/DRAM_DATA10",
|
|
|
|
|
"/fpga_ddr/DRAM_DATA11",
|
|
|
|
|
"/fpga_ddr/DRAM_DATA12",
|
|
|
|
|
"/fpga_ddr/DRAM_DATA13",
|
|
|
|
|
"/fpga_ddr/DRAM_DATA14",
|
|
|
|
|
"/fpga_ddr/DRAM_DATA15",
|
|
|
|
|
"/fpga_ddr/DRAM_DATA8",
|
|
|
|
|
"/fpga_ddr/DRAM_DATA9",
|
|
|
|
|
"/fpga_ddr/DRAM_UDM",
|
|
|
|
|
"/fpga_ddr/DRAM_UDQSN",
|
|
|
|
|
"/fpga_ddr/DRAM_UDQSP"
|
|
|
|
|
],
|
|
|
|
|
"pcb_color": "rgb(255, 252, 0)",
|
|
|
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"track_width": 0.1,
|
|
|
|
|
"via_diameter": 0.45,
|
|
|
|
|
"via_drill": 0.2,
|
|
|
|
|
"wire_width": 6.0
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"bus_width": 12.0,
|
|
|
|
|
"clearance": 0.1,
|
|
|
|
|
"diff_pair_gap": 0.1,
|
|
|
|
|
"diff_pair_via_gap": 0.25,
|
|
|
|
|
"diff_pair_width": 0.1,
|
|
|
|
|
"line_style": 0,
|
|
|
|
|
"microvia_diameter": 0.3,
|
|
|
|
|
"microvia_drill": 0.1,
|
|
|
|
|
"name": "SDRAM_L",
|
|
|
|
|
"nets": [
|
|
|
|
|
"/fpga_ddr/DRAM_DATA0",
|
|
|
|
|
"/fpga_ddr/DRAM_DATA1",
|
|
|
|
|
"/fpga_ddr/DRAM_DATA2",
|
|
|
|
|
"/fpga_ddr/DRAM_DATA3",
|
|
|
|
|
"/fpga_ddr/DRAM_DATA4",
|
|
|
|
|
"/fpga_ddr/DRAM_DATA5",
|
|
|
|
|
"/fpga_ddr/DRAM_DATA6",
|
|
|
|
|
"/fpga_ddr/DRAM_DATA7",
|
|
|
|
|
"/fpga_ddr/DRAM_LDM",
|
|
|
|
|
"/fpga_ddr/DRAM_LDQSN",
|
|
|
|
|
"/fpga_ddr/DRAM_LDQSP"
|
|
|
|
|
],
|
|
|
|
|
"pcb_color": "rgb(255, 131, 3)",
|
|
|
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"track_width": 0.1,
|
|
|
|
|
"via_diameter": 0.45,
|
|
|
|
|
"via_drill": 0.2,
|
|
|
|
|
"wire_width": 6.0
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"bus_width": 12.0,
|
2022-07-04 02:44:02 +00:00
|
|
|
"clearance": 0.11,
|
|
|
|
|
"diff_pair_gap": 0.11,
|
2022-03-05 21:48:31 +00:00
|
|
|
"diff_pair_via_gap": 0.25,
|
2022-07-04 02:44:02 +00:00
|
|
|
"diff_pair_width": 0.18,
|
2022-03-05 21:48:31 +00:00
|
|
|
"line_style": 0,
|
|
|
|
|
"microvia_diameter": 0.3,
|
|
|
|
|
"microvia_drill": 0.1,
|
|
|
|
|
"name": "USB",
|
|
|
|
|
"nets": [],
|
|
|
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"track_width": 0.15,
|
|
|
|
|
"via_diameter": 0.45,
|
|
|
|
|
"via_drill": 0.2,
|
|
|
|
|
"wire_width": 6.0
|
|
|
|
|
}
|
|
|
|
|
],
|
|
|
|
|
"meta": {
|
|
|
|
|
"version": 2
|
|
|
|
|
},
|
|
|
|
|
"net_colors": {
|
|
|
|
|
"+1V1": "rgb(255, 92, 56)",
|
|
|
|
|
"+1V35": "rgb(185, 61, 143)",
|
|
|
|
|
"+3V3": "rgb(179, 228, 50)",
|
|
|
|
|
"+5V": "rgb(255, 122, 107)",
|
|
|
|
|
"GND": "rgb(0, 94, 255)"
|
|
|
|
|
}
|
|
|
|
|
},
|
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2022-11-21 02:58:28 +00:00
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2022-03-05 21:48:31 +00:00
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}
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