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Initial USB command implementation

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This commit is contained in:
Wenting Zhang 2024-02-15 00:28:30 -05:00
parent 53487358ff
commit 2380384e70
5 changed files with 37 additions and 13 deletions
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19
fw/caster.c
View file

@ -56,27 +56,33 @@ void caster_init(void) {
// fpga_write_reg8(CSR_CONTROL, 1); // Enable refresh // fpga_write_reg8(CSR_CONTROL, 1); // Enable refresh
} }
void caster_load_waveform(uint8_t *waveform, uint8_t frames) { static uint8_t is_busy() {
wait(); uint8_t status = fpga_write_reg8(CSR_STATUS, 0x00);
return !!(status & STATUS_OP_QUEUE);
}
uint8_t caster_load_waveform(uint8_t *waveform, uint8_t frames) {
fpga_write_reg8(CSR_LUT_FRAME, 0); // Reset value before loading fpga_write_reg8(CSR_LUT_FRAME, 0); // Reset value before loading
fpga_write_reg16(CSR_LUT_ADDR, 0); fpga_write_reg16(CSR_LUT_ADDR, 0);
fpga_write_bulk(CSR_LUT_WR, waveform, WAVEFORM_SIZE); fpga_write_bulk(CSR_LUT_WR, waveform, WAVEFORM_SIZE);
waveform_frames = frames; waveform_frames = frames;
return 0;
} }
void caster_redraw(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1) { uint8_t caster_redraw(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1) {
wait(); if (is_busy()) return 1;
fpga_write_reg16(CSR_OP_LEFT, x0); fpga_write_reg16(CSR_OP_LEFT, x0);
fpga_write_reg16(CSR_OP_TOP, y0); fpga_write_reg16(CSR_OP_TOP, y0);
fpga_write_reg16(CSR_OP_RIGHT, x1); fpga_write_reg16(CSR_OP_RIGHT, x1);
fpga_write_reg16(CSR_OP_BOTTOM, y1); fpga_write_reg16(CSR_OP_BOTTOM, y1);
fpga_write_reg8(CSR_OP_LENGTH, get_update_frames()); fpga_write_reg8(CSR_OP_LENGTH, get_update_frames());
fpga_write_reg8(CSR_OP_CMD, OP_EXT_REDRAW); fpga_write_reg8(CSR_OP_CMD, OP_EXT_REDRAW);
return 0;
} }
void caster_setmode(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1, uint8_t caster_setmode(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1,
UPDATE_MODE mode) { UPDATE_MODE mode) {
wait(); if (is_busy()) return 1;
fpga_write_reg16(CSR_OP_LEFT, x0); fpga_write_reg16(CSR_OP_LEFT, x0);
fpga_write_reg16(CSR_OP_TOP, y0); fpga_write_reg16(CSR_OP_TOP, y0);
fpga_write_reg16(CSR_OP_RIGHT, x1); fpga_write_reg16(CSR_OP_RIGHT, x1);
@ -84,4 +90,5 @@ void caster_setmode(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1,
fpga_write_reg8(CSR_OP_LENGTH, get_update_frames()); fpga_write_reg8(CSR_OP_LENGTH, get_update_frames());
fpga_write_reg8(CSR_OP_PARAM, (uint8_t)mode); fpga_write_reg8(CSR_OP_PARAM, (uint8_t)mode);
fpga_write_reg8(CSR_OP_CMD, OP_EXT_SETMODE); fpga_write_reg8(CSR_OP_CMD, OP_EXT_SETMODE);
return 0;
} }

7
fw/caster.h
View file

@ -52,6 +52,7 @@
#define CSR_CFG_FBYTES_B2 27 #define CSR_CFG_FBYTES_B2 27
#define CSR_CFG_FBYTES_B1 28 #define CSR_CFG_FBYTES_B1 28
#define CSR_CFG_FBYTES_B0 29 #define CSR_CFG_FBYTES_B0 29
#define CSR_STATUS 32
// Alias for 16bit registers // Alias for 16bit registers
#define CSR_LUT_ADDR CSR_LUT_ADDR_HI #define CSR_LUT_ADDR CSR_LUT_ADDR_HI
#define CSR_OP_LEFT CSR_OP_LEFT_HI #define CSR_OP_LEFT CSR_OP_LEFT_HI
@ -89,7 +90,7 @@ typedef enum {
} UPDATE_MODE; } UPDATE_MODE;
void caster_init(void); void caster_init(void);
void caster_load_waveform(uint8_t *waveform, uint8_t frames); uint8_t caster_load_waveform(uint8_t *waveform, uint8_t frames);
void caster_redraw(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1); uint8_t caster_redraw(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1);
void caster_setmode(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1, uint8_t caster_setmode(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1,
UPDATE_MODE mode); UPDATE_MODE mode);

15
fw/fpga.c
View file

@ -60,22 +60,31 @@ static void fpga_send_byte(uint8_t byte) {
} }
} }
static void fpga_send_byte_slow(uint8_t byte) { static uint8_t fpga_send_byte_slow(uint8_t byte) {
uint8_t rxbyte;
for (int i = 0; i < 8; i++) { for (int i = 0; i < 8; i++) {
gpio_put(FPGA_MOSI, byte & 0x80); gpio_put(FPGA_MOSI, byte & 0x80);
delay_loop(20); delay_loop(20);
rxbyte |= gpio_get(FPGA_MISO);
gpio_put(FPGA_SCLK, 1); gpio_put(FPGA_SCLK, 1);
delay_loop(20); delay_loop(20);
byte <<= 1; byte <<= 1;
rxbyte <<= 1;
gpio_put(FPGA_SCLK, 0); gpio_put(FPGA_SCLK, 0);
} }
delay_loop(20);
rxbyte |= gpio_get(FPGA_MISO);
gpio_put(FPGA_SCLK, 1);
return rxbyte;
} }
void fpga_write_reg8(uint8_t addr, uint8_t val) { uint8_t fpga_write_reg8(uint8_t addr, uint8_t val) {
uint8_t oldval;
gpio_put(FPGA_CS, 0); gpio_put(FPGA_CS, 0);
fpga_send_byte_slow(addr); fpga_send_byte_slow(addr);
fpga_send_byte_slow(val); oldval = fpga_send_byte_slow(val);
gpio_put(FPGA_CS, 1); gpio_put(FPGA_CS, 1);
return oldval;
} }
void fpga_write_reg16(uint8_t addr, uint16_t val) { void fpga_write_reg16(uint8_t addr, uint16_t val) {

2
fw/fpga.h
View file

@ -24,6 +24,6 @@
void fpga_init(void); void fpga_init(void);
void fpga_suspend(void); void fpga_suspend(void);
void fpga_resume(void); void fpga_resume(void);
void fpga_write_reg8(uint8_t addr, uint8_t val); uint8_t fpga_write_reg8(uint8_t addr, uint8_t val);
void fpga_write_reg16(uint8_t addr, uint16_t val); void fpga_write_reg16(uint8_t addr, uint16_t val);
void fpga_write_bulk(uint8_t addr, uint8_t *buf, int length); void fpga_write_bulk(uint8_t addr, uint8_t *buf, int length);

7
fw/usbapp.h
View file

@ -21,5 +21,12 @@
// //
#pragma once #pragma once
#define USBCMD_RESET 0x00
#define USBCMD_POWERDOWN 0x01
#define USBCMD_POWERUP 0x02
#define USBCMD_SETINPUT 0x03
#define USBCMD_REDRAW 0x04
#define USBCMD_SETMODE 0x05
void usbapp_init(void); void usbapp_init(void);
void usbapp_task(void); void usbapp_task(void);