diff --git a/fw/caster.c b/fw/caster.c
index 8044ab6..0d4e012 100644
--- a/fw/caster.c
+++ b/fw/caster.c
@@ -56,27 +56,33 @@ void caster_init(void) {
     // fpga_write_reg8(CSR_CONTROL, 1); // Enable refresh
 }
 
-void caster_load_waveform(uint8_t *waveform, uint8_t frames) {
-    wait();
+static uint8_t is_busy() {
+    uint8_t status = fpga_write_reg8(CSR_STATUS, 0x00);
+    return !!(status & STATUS_OP_QUEUE);
+}
+
+uint8_t caster_load_waveform(uint8_t *waveform, uint8_t frames) {
     fpga_write_reg8(CSR_LUT_FRAME, 0); // Reset value before loading
     fpga_write_reg16(CSR_LUT_ADDR, 0);
     fpga_write_bulk(CSR_LUT_WR, waveform, WAVEFORM_SIZE);
     waveform_frames = frames;
+    return 0;
 }
 
-void caster_redraw(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1) {
-    wait();
+uint8_t caster_redraw(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1) {
+    if (is_busy()) return 1;
     fpga_write_reg16(CSR_OP_LEFT, x0);
     fpga_write_reg16(CSR_OP_TOP, y0);
     fpga_write_reg16(CSR_OP_RIGHT, x1);
     fpga_write_reg16(CSR_OP_BOTTOM, y1);
     fpga_write_reg8(CSR_OP_LENGTH, get_update_frames());
     fpga_write_reg8(CSR_OP_CMD, OP_EXT_REDRAW);
+    return 0;
 }
 
-void caster_setmode(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1,
+uint8_t caster_setmode(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1,
         UPDATE_MODE mode) {
-    wait();
+    if (is_busy()) return 1;
     fpga_write_reg16(CSR_OP_LEFT, x0);
     fpga_write_reg16(CSR_OP_TOP, y0);
     fpga_write_reg16(CSR_OP_RIGHT, x1);
@@ -84,4 +90,5 @@ void caster_setmode(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1,
     fpga_write_reg8(CSR_OP_LENGTH, get_update_frames());
     fpga_write_reg8(CSR_OP_PARAM, (uint8_t)mode);
     fpga_write_reg8(CSR_OP_CMD, OP_EXT_SETMODE);
+    return 0;
 }
\ No newline at end of file
diff --git a/fw/caster.h b/fw/caster.h
index 7fbc4aa..cfc25b5 100644
--- a/fw/caster.h
+++ b/fw/caster.h
@@ -52,6 +52,7 @@
 #define CSR_CFG_FBYTES_B2   27
 #define CSR_CFG_FBYTES_B1   28
 #define CSR_CFG_FBYTES_B0   29
+#define CSR_STATUS          32
 // Alias for 16bit registers
 #define CSR_LUT_ADDR        CSR_LUT_ADDR_HI
 #define CSR_OP_LEFT         CSR_OP_LEFT_HI
@@ -89,7 +90,7 @@ typedef enum {
 } UPDATE_MODE;
 
 void caster_init(void);
-void caster_load_waveform(uint8_t *waveform, uint8_t frames);
-void caster_redraw(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1);
-void caster_setmode(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1,
+uint8_t caster_load_waveform(uint8_t *waveform, uint8_t frames);
+uint8_t caster_redraw(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1);
+uint8_t caster_setmode(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1,
         UPDATE_MODE mode);
diff --git a/fw/fpga.c b/fw/fpga.c
index 6913bba..fa7a243 100644
--- a/fw/fpga.c
+++ b/fw/fpga.c
@@ -60,22 +60,31 @@ static void fpga_send_byte(uint8_t byte) {
     }
 }
 
-static void fpga_send_byte_slow(uint8_t byte) {
+static uint8_t fpga_send_byte_slow(uint8_t byte) {
+    uint8_t rxbyte;
     for (int i = 0; i < 8; i++) {
         gpio_put(FPGA_MOSI, byte & 0x80);
         delay_loop(20);
+        rxbyte |= gpio_get(FPGA_MISO);
         gpio_put(FPGA_SCLK, 1);
         delay_loop(20);
         byte <<= 1;
+        rxbyte <<= 1;
         gpio_put(FPGA_SCLK, 0);
     }
+    delay_loop(20);
+    rxbyte |= gpio_get(FPGA_MISO);
+    gpio_put(FPGA_SCLK, 1);
+    return rxbyte;
 }
 
-void fpga_write_reg8(uint8_t addr, uint8_t val) {
+uint8_t fpga_write_reg8(uint8_t addr, uint8_t val) {
+    uint8_t oldval;
     gpio_put(FPGA_CS, 0);
     fpga_send_byte_slow(addr);
-    fpga_send_byte_slow(val);
+    oldval = fpga_send_byte_slow(val);
     gpio_put(FPGA_CS, 1);
+    return oldval;
 }
 
 void fpga_write_reg16(uint8_t addr, uint16_t val) {
diff --git a/fw/fpga.h b/fw/fpga.h
index f932a80..8acc106 100644
--- a/fw/fpga.h
+++ b/fw/fpga.h
@@ -24,6 +24,6 @@
 void fpga_init(void);
 void fpga_suspend(void);
 void fpga_resume(void);
-void fpga_write_reg8(uint8_t addr, uint8_t val);
+uint8_t fpga_write_reg8(uint8_t addr, uint8_t val);
 void fpga_write_reg16(uint8_t addr, uint16_t val);
 void fpga_write_bulk(uint8_t addr, uint8_t *buf, int length);
\ No newline at end of file
diff --git a/fw/usbapp.h b/fw/usbapp.h
index 52ab326..1227f71 100644
--- a/fw/usbapp.h
+++ b/fw/usbapp.h
@@ -21,5 +21,12 @@
 //
 #pragma once
 
+#define USBCMD_RESET        0x00
+#define USBCMD_POWERDOWN    0x01
+#define USBCMD_POWERUP      0x02
+#define USBCMD_SETINPUT     0x03
+#define USBCMD_REDRAW       0x04
+#define USBCMD_SETMODE      0x05
+
 void usbapp_init(void);
 void usbapp_task(void);