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synced 2024-09-20 11:23:16 +00:00
main/llvm17: Revert "[LoongArch] Support InlineAsm for LSX and LASX"
This reverts commit d25c79dc70008b835312e5cc7ef48b199fda3165.
D154931[1] needs to be reverted on LLVM17. As Loongson SIMD Extension(LSX) and
Loongson Advanced SIMD Extension(LASX) are not fully supported on LLVM17,
InlineAsm for LSX and LASX should not be supported as well. Otherwise it leads
to the following error:
'''
LLVM ERROR: Cannot select: 0x7ffea41a3650: ch = store<(store (s128) into %ir.mask
store52)> 0x7ffea41a35e0, 0x7ffea4196a30, FrameIndex:i64<6>, undef:i64
'''
LSX and LASX are fully supported on LLVM18 and are not supported on LLVM16,
thus only LLVM17 has the problem.
[1] https://reviews.llvm.org/D154931
[2] d25c79dc70
This commit is contained in:
Jingyun Hua
Natanael Copa
parent
00ecf18337
commit
13efced704
2 changed files with 468 additions and 0 deletions
|
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@ -44,6 +44,7 @@ source="https://github.com/llvm/llvm-project/releases/download/llvmorg-$pkgver/l
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0001-Revert-Pseudo-Probe-Make-.pseudo_probe-GC-able.patch
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fix-hexagon-tests.patch
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workaround-codegen-riscv-xtheadmempair-miscompile.patch
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Revert-LoongArch-Support-InlineAsm-for-LSX-and-LASX.patch
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"
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builddir="$srcdir/$_pkgname-project-$pkgver.src"
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|
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@ -327,4 +328,5 @@ ebc0be314c129ef38f00c8c2be9d589658cae89ac8cda109e35933b5044e775a3d370c0c584d3e50
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|||
58a4887feedb72f2aa286b396f91348a6730028c358686701c30e084dd968de9597d86373e118c865f0b495d201e094bb0a2cdc19ede49d9f60e34eb7b0b71dc 0001-Revert-Pseudo-Probe-Make-.pseudo_probe-GC-able.patch
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||||
bd51d487c46472963a350cd90f7d7a5d8a4494467716f4e4e3d21ba6be5f65c0e84f173a5bb8468fb68325e75401f08110f8886320d5caa9acd339d795b254bc fix-hexagon-tests.patch
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||||
7367b26f263cb0d36a358b79fe41256b4e8632170f3955e00aeeac3ccc6c3ae5dc370d596370bcf8c6b847473f02445fd1de7e6af36de6bd34b87995736fbf16 workaround-codegen-riscv-xtheadmempair-miscompile.patch
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aaf99948c2b22e00e5244a0302bd98f541650d9b0bff576de9704a63e3bc2c0acb6a6f667898dbae92884062cefff3f8600fec47cf268e520c636ee903a03a92 Revert-LoongArch-Support-InlineAsm-for-LSX-and-LASX.patch
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"
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|
|
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@ -0,0 +1,466 @@
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From 7236a15338bafc4bb4c6e61d4b151e0b9cc85448 Mon Sep 17 00:00:00 2001
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From: chenli <chenli@loongson.cn>
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Date: Mon, 18 Mar 2024 15:16:34 +0800
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Subject: [PATCH] Revert "[LoongArch] Support InlineAsm for LSX and LASX"
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This reverts commit d25c79dc70008b835312e5cc7ef48b199fda3165.
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D154931[1] needs to be reverted on LLVM17. As Loongson SIMD Extension(LSX) and
|
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Loongson Advanced SIMD Extension(LASX) are not fully supported on LLVM17,
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InlineAsm for LSX and LASX should not be supported as well. Otherwise it leads
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to the following issue[2]:
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'''
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LLVM ERROR: Cannot select: 0x7ffea41a3650: ch = store<(store (s128) into %ir.mask
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store52)> 0x7ffea41a35e0, 0x7ffea4196a30, FrameIndex:i64<6>, undef:i64
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'''
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LSX and LASX are fully supported on LLVM18 and are not supported on LLVM16,
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thus only LLVM17 has the problem.
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[1] https://reviews.llvm.org/D154931
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---
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clang/lib/Basic/Targets/LoongArch.cpp | 12 +---
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.../lasx/inline-asm-gcc-regs-error.c | 10 ----
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.../LoongArch/lasx/inline-asm-gcc-regs.c | 36 ------------
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.../lasx/inline-asm-operand-modifier.c | 15 -----
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.../LoongArch/lsx/inline-asm-gcc-regs-error.c | 10 ----
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.../LoongArch/lsx/inline-asm-gcc-regs.c | 36 ------------
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.../lsx/inline-asm-operand-modifier.c | 15 -----
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.../Target/LoongArch/LoongArchAsmPrinter.cpp | 14 -----
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.../LoongArch/LoongArchISelLowering.cpp | 17 +-----
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.../lasx/inline-asm-operand-modifier.ll | 14 -----
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.../LoongArch/lasx/inline-asm-reg-names.ll | 58 -------------------
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.../lsx/inline-asm-operand-modifier.ll | 14 -----
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.../LoongArch/lsx/inline-asm-reg-names.ll | 58 -------------------
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13 files changed, 2 insertions(+), 307 deletions(-)
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delete mode 100644 clang/test/CodeGen/LoongArch/lasx/inline-asm-gcc-regs-error.c
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delete mode 100644 clang/test/CodeGen/LoongArch/lasx/inline-asm-gcc-regs.c
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delete mode 100644 clang/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.c
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delete mode 100644 clang/test/CodeGen/LoongArch/lsx/inline-asm-gcc-regs-error.c
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delete mode 100644 clang/test/CodeGen/LoongArch/lsx/inline-asm-gcc-regs.c
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delete mode 100644 clang/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.c
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delete mode 100644 llvm/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.ll
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delete mode 100644 llvm/test/CodeGen/LoongArch/lasx/inline-asm-reg-names.ll
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delete mode 100644 llvm/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.ll
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delete mode 100644 llvm/test/CodeGen/LoongArch/lsx/inline-asm-reg-names.ll
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diff --git a/clang/lib/Basic/Targets/LoongArch.cpp b/clang/lib/Basic/Targets/LoongArch.cpp
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index 4448a2ae10a1..96ef29620eb6 100644
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--- a/clang/lib/Basic/Targets/LoongArch.cpp
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+++ b/clang/lib/Basic/Targets/LoongArch.cpp
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@@ -33,17 +33,7 @@ ArrayRef<const char *> LoongArchTargetInfo::getGCCRegNames() const {
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"$f19", "$f20", "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27",
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"$f28", "$f29", "$f30", "$f31",
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// Condition flag registers.
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- "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5", "$fcc6", "$fcc7",
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- // 128-bit vector registers.
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- "$vr0", "$vr1", "$vr2", "$vr3", "$vr4", "$vr5", "$vr6", "$vr7", "$vr8",
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- "$vr9", "$vr10", "$vr11", "$vr12", "$vr13", "$vr14", "$vr15", "$vr16",
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- "$vr17", "$vr18", "$vr19", "$vr20", "$vr21", "$vr22", "$vr23", "$vr24",
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- "$vr25", "$vr26", "$vr27", "$vr28", "$vr29", "$vr30", "$vr31",
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- // 256-bit vector registers.
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- "$xr0", "$xr1", "$xr2", "$xr3", "$xr4", "$xr5", "$xr6", "$xr7", "$xr8",
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- "$xr9", "$xr10", "$xr11", "$xr12", "$xr13", "$xr14", "$xr15", "$xr16",
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- "$xr17", "$xr18", "$xr19", "$xr20", "$xr21", "$xr22", "$xr23", "$xr24",
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- "$xr25", "$xr26", "$xr27", "$xr28", "$xr29", "$xr30", "$xr31"};
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+ "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5", "$fcc6", "$fcc7"};
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return llvm::ArrayRef(GCCRegNames);
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}
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diff --git a/clang/test/CodeGen/LoongArch/lasx/inline-asm-gcc-regs-error.c b/clang/test/CodeGen/LoongArch/lasx/inline-asm-gcc-regs-error.c
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deleted file mode 100644
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index 1fd602574b8e..000000000000
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--- a/clang/test/CodeGen/LoongArch/lasx/inline-asm-gcc-regs-error.c
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+++ /dev/null
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@@ -1,10 +0,0 @@
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-// RUN: not %clang_cc1 -triple loongarch64 -emit-llvm -O2 %s 2>&1 -o - | FileCheck %s
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-
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-typedef signed char v32i8 __attribute__((vector_size(32), aligned(32)));
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-
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-void test() {
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-// CHECK: :[[#@LINE+1]]:28: error: unknown register name 'xr0' in asm
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- register v32i8 p0 asm ("xr0");
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-// CHECK: :[[#@LINE+1]]:29: error: unknown register name '$xr32' in asm
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- register v32i8 p32 asm ("$xr32");
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-}
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diff --git a/clang/test/CodeGen/LoongArch/lasx/inline-asm-gcc-regs.c b/clang/test/CodeGen/LoongArch/lasx/inline-asm-gcc-regs.c
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deleted file mode 100644
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index ed1a9660a06c..000000000000
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--- a/clang/test/CodeGen/LoongArch/lasx/inline-asm-gcc-regs.c
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+++ /dev/null
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@@ -1,36 +0,0 @@
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-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --filter "^define |tail call"
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-// RUN: %clang_cc1 -triple loongarch64 -emit-llvm -O2 %s -o - | FileCheck %s
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-
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-typedef signed char v32i8 __attribute__((vector_size(32), aligned(32)));
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-
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-// CHECK-LABEL: @test_xr0(
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-// CHECK: tail call void asm sideeffect "", "{$xr0}"(<32 x i8> undef) #[[ATTR1:[0-9]+]], !srcloc !2
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-//
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-void test_xr0() {
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- register v32i8 a asm ("$xr0");
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- asm ("" :: "f"(a));
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-}
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-
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-// CHECK-LABEL: @test_xr7(
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-// CHECK: tail call void asm sideeffect "", "{$xr7}"(<32 x i8> undef) #[[ATTR1]], !srcloc !3
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-//
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-void test_xr7() {
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- register v32i8 a asm ("$xr7");
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- asm ("" :: "f"(a));
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-}
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-
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-// CHECK-LABEL: @test_xr15(
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-// CHECK: tail call void asm sideeffect "", "{$xr15}"(<32 x i8> undef) #[[ATTR1]], !srcloc !4
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-//
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-void test_xr15() {
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- register v32i8 a asm ("$xr15");
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- asm ("" :: "f"(a));
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-}
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-
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-// CHECK-LABEL: @test_xr31(
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-// CHECK: tail call void asm sideeffect "", "{$xr31}"(<32 x i8> undef) #[[ATTR1]], !srcloc !5
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-//
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-void test_xr31() {
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- register v32i8 a asm ("$xr31");
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- asm ("" :: "f"(a));
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-}
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diff --git a/clang/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.c b/clang/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.c
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deleted file mode 100644
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index a5cc8798fd66..000000000000
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--- a/clang/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.c
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+++ /dev/null
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@@ -1,15 +0,0 @@
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-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
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-// RUN: %clang_cc1 -triple loongarch64 -emit-llvm -O2 %s -o - | FileCheck %s
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-
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-typedef long long v4i64 __attribute__ ((vector_size(32), aligned(32)));
|
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-
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-// CHECK-LABEL: define dso_local void @test_u
|
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-// CHECK-SAME: () local_unnamed_addr #[[ATTR0:[0-9]+]] {
|
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-// CHECK-NEXT: entry:
|
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-// CHECK-NEXT: [[TMP0:%.*]] = tail call <4 x i64> asm sideeffect "xvldi ${0:u}, 1", "=f"() #[[ATTR1:[0-9]+]], !srcloc !2
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-// CHECK-NEXT: ret void
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-//
|
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-void test_u() {
|
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- v4i64 v4i64_r;
|
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- asm volatile ("xvldi %u0, 1" : "=f" (v4i64_r));
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-}
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diff --git a/clang/test/CodeGen/LoongArch/lsx/inline-asm-gcc-regs-error.c b/clang/test/CodeGen/LoongArch/lsx/inline-asm-gcc-regs-error.c
|
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deleted file mode 100644
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index 54132307e93f..000000000000
|
||||
--- a/clang/test/CodeGen/LoongArch/lsx/inline-asm-gcc-regs-error.c
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+++ /dev/null
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@@ -1,10 +0,0 @@
|
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-// RUN: not %clang_cc1 -triple loongarch64 -emit-llvm -O2 %s 2>&1 -o - | FileCheck %s
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-
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-typedef signed char v16i8 __attribute__((vector_size(16), aligned(16)));
|
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-
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-void test() {
|
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-// CHECK: :[[#@LINE+1]]:28: error: unknown register name 'vr0' in asm
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- register v16i8 p0 asm ("vr0");
|
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-// CHECK: :[[#@LINE+1]]:29: error: unknown register name '$vr32' in asm
|
||||
- register v16i8 p32 asm ("$vr32");
|
||||
-}
|
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diff --git a/clang/test/CodeGen/LoongArch/lsx/inline-asm-gcc-regs.c b/clang/test/CodeGen/LoongArch/lsx/inline-asm-gcc-regs.c
|
||||
deleted file mode 100644
|
||||
index b05b1c8c15fa..000000000000
|
||||
--- a/clang/test/CodeGen/LoongArch/lsx/inline-asm-gcc-regs.c
|
||||
+++ /dev/null
|
||||
@@ -1,36 +0,0 @@
|
||||
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --filter "^define |tail call"
|
||||
-// RUN: %clang_cc1 -triple loongarch64 -emit-llvm -O2 %s -o - | FileCheck %s
|
||||
-
|
||||
-typedef signed char v16i8 __attribute__((vector_size(16), aligned(16)));
|
||||
-
|
||||
-// CHECK-LABEL: @test_vr0(
|
||||
-// CHECK: tail call void asm sideeffect "", "{$vr0}"(<16 x i8> undef) #[[ATTR1:[0-9]+]], !srcloc !2
|
||||
-//
|
||||
-void test_vr0() {
|
||||
- register v16i8 a asm ("$vr0");
|
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- asm ("" :: "f"(a));
|
||||
-}
|
||||
-
|
||||
-// CHECK-LABEL: @test_vr7(
|
||||
-// CHECK: tail call void asm sideeffect "", "{$vr7}"(<16 x i8> undef) #[[ATTR1]], !srcloc !3
|
||||
-//
|
||||
-void test_vr7() {
|
||||
- register v16i8 a asm ("$vr7");
|
||||
- asm ("" :: "f"(a));
|
||||
-}
|
||||
-
|
||||
-// CHECK-LABEL: @test_vr15(
|
||||
-// CHECK: tail call void asm sideeffect "", "{$vr15}"(<16 x i8> undef) #[[ATTR1]], !srcloc !4
|
||||
-//
|
||||
-void test_vr15() {
|
||||
- register v16i8 a asm ("$vr15");
|
||||
- asm ("" :: "f"(a));
|
||||
-}
|
||||
-
|
||||
-// CHECK-LABEL: @test_vr31(
|
||||
-// CHECK: tail call void asm sideeffect "", "{$vr31}"(<16 x i8> undef) #[[ATTR1]], !srcloc !5
|
||||
-//
|
||||
-void test_vr31() {
|
||||
- register v16i8 a asm ("$vr31");
|
||||
- asm ("" :: "f"(a));
|
||||
-}
|
||||
diff --git a/clang/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.c b/clang/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.c
|
||||
deleted file mode 100644
|
||||
index 5e0fae984134..000000000000
|
||||
--- a/clang/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.c
|
||||
+++ /dev/null
|
||||
@@ -1,15 +0,0 @@
|
||||
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
|
||||
-// RUN: %clang_cc1 -triple loongarch64 -emit-llvm -O2 %s -o - | FileCheck %s
|
||||
-
|
||||
-typedef long long v2i64 __attribute__ ((vector_size(16), aligned(16)));
|
||||
-
|
||||
-// CHECK-LABEL: define dso_local void @test_w
|
||||
-// CHECK-SAME: () local_unnamed_addr #[[ATTR0:[0-9]+]] {
|
||||
-// CHECK-NEXT: entry:
|
||||
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <2 x i64> asm sideeffect "vldi ${0:w}, 1", "=f"() #[[ATTR1:[0-9]+]], !srcloc !2
|
||||
-// CHECK-NEXT: ret void
|
||||
-//
|
||||
-void test_w() {
|
||||
- v2i64 v2i64_r;
|
||||
- asm volatile ("vldi %w0, 1" : "=f" (v2i64_r));
|
||||
-}
|
||||
diff --git a/llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp b/llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
|
||||
index 27979a830b10..5cf0673df69a 100644
|
||||
--- a/llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
|
||||
+++ b/llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
|
||||
@@ -75,20 +75,6 @@ bool LoongArchAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
- case 'w': // Print LSX registers.
|
||||
- if (MO.getReg().id() >= LoongArch::VR0 &&
|
||||
- MO.getReg().id() <= LoongArch::VR31)
|
||||
- break;
|
||||
- // The modifier is 'w' but the operand is not an LSX register; Report an
|
||||
- // unknown operand error.
|
||||
- return true;
|
||||
- case 'u': // Print LASX registers.
|
||||
- if (MO.getReg().id() >= LoongArch::XR0 &&
|
||||
- MO.getReg().id() <= LoongArch::XR31)
|
||||
- break;
|
||||
- // The modifier is 'u' but the operand is not an LASX register; Report an
|
||||
- // unknown operand error.
|
||||
- return true;
|
||||
// TODO: handle other extra codes if any.
|
||||
}
|
||||
}
|
||||
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
|
||||
index db5961fc501a..488e1c7f3a76 100644
|
||||
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
|
||||
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
|
||||
@@ -53,14 +53,6 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
|
||||
addRegisterClass(MVT::f32, &LoongArch::FPR32RegClass);
|
||||
if (Subtarget.hasBasicD())
|
||||
addRegisterClass(MVT::f64, &LoongArch::FPR64RegClass);
|
||||
- if (Subtarget.hasExtLSX())
|
||||
- for (auto VT : {MVT::v4f32, MVT::v2f64, MVT::v16i8, MVT::v8i16, MVT::v4i32,
|
||||
- MVT::v2i64})
|
||||
- addRegisterClass(VT, &LoongArch::LSX128RegClass);
|
||||
- if (Subtarget.hasExtLASX())
|
||||
- for (auto VT : {MVT::v8f32, MVT::v4f64, MVT::v32i8, MVT::v16i16, MVT::v8i32,
|
||||
- MVT::v4i64})
|
||||
- addRegisterClass(VT, &LoongArch::LASX256RegClass);
|
||||
|
||||
setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, GRLenVT,
|
||||
MVT::i1, Promote);
|
||||
@@ -3056,12 +3048,6 @@ LoongArchTargetLowering::getRegForInlineAsmConstraint(
|
||||
return std::make_pair(0U, &LoongArch::FPR32RegClass);
|
||||
if (Subtarget.hasBasicD() && VT == MVT::f64)
|
||||
return std::make_pair(0U, &LoongArch::FPR64RegClass);
|
||||
- if (Subtarget.hasExtLSX() &&
|
||||
- TRI->isTypeLegalForClass(LoongArch::LSX128RegClass, VT))
|
||||
- return std::make_pair(0U, &LoongArch::LSX128RegClass);
|
||||
- if (Subtarget.hasExtLASX() &&
|
||||
- TRI->isTypeLegalForClass(LoongArch::LASX256RegClass, VT))
|
||||
- return std::make_pair(0U, &LoongArch::LASX256RegClass);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
@@ -3079,8 +3065,7 @@ LoongArchTargetLowering::getRegForInlineAsmConstraint(
|
||||
// decode the usage of register name aliases into their official names. And
|
||||
// AFAIK, the not yet upstreamed `rustc` for LoongArch will always use
|
||||
// official register names.
|
||||
- if (Constraint.startswith("{$r") || Constraint.startswith("{$f") ||
|
||||
- Constraint.startswith("{$vr") || Constraint.startswith("{$xr")) {
|
||||
+ if (Constraint.startswith("{$r") || Constraint.startswith("{$f")) {
|
||||
bool IsFP = Constraint[2] == 'f';
|
||||
std::pair<StringRef, StringRef> Temp = Constraint.split('$');
|
||||
std::pair<unsigned, const TargetRegisterClass *> R;
|
||||
diff --git a/llvm/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.ll b/llvm/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.ll
|
||||
deleted file mode 100644
|
||||
index 201e34c8b5ae..000000000000
|
||||
--- a/llvm/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.ll
|
||||
+++ /dev/null
|
||||
@@ -1,14 +0,0 @@
|
||||
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
|
||||
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
|
||||
-
|
||||
-define void @test_u() nounwind {
|
||||
-; CHECK-LABEL: test_u:
|
||||
-; CHECK: # %bb.0: # %entry
|
||||
-; CHECK-NEXT: #APP
|
||||
-; CHECK-NEXT: xvldi $xr0, 1
|
||||
-; CHECK-NEXT: #NO_APP
|
||||
-; CHECK-NEXT: ret
|
||||
-entry:
|
||||
- %0 = tail call <4 x i64> asm sideeffect "xvldi ${0:u}, 1", "=f"()
|
||||
- ret void
|
||||
-}
|
||||
diff --git a/llvm/test/CodeGen/LoongArch/lasx/inline-asm-reg-names.ll b/llvm/test/CodeGen/LoongArch/lasx/inline-asm-reg-names.ll
|
||||
deleted file mode 100644
|
||||
index dd400ecfcf91..000000000000
|
||||
--- a/llvm/test/CodeGen/LoongArch/lasx/inline-asm-reg-names.ll
|
||||
+++ /dev/null
|
||||
@@ -1,58 +0,0 @@
|
||||
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
|
||||
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
|
||||
-
|
||||
-define void @register_xr1() nounwind {
|
||||
-; CHECK-LABEL: register_xr1:
|
||||
-; CHECK: # %bb.0: # %entry
|
||||
-; CHECK-NEXT: #APP
|
||||
-; CHECK-NEXT: xvldi $xr1, 1
|
||||
-; CHECK-NEXT: #NO_APP
|
||||
-; CHECK-NEXT: ret
|
||||
-entry:
|
||||
- %0 = tail call <4 x i64> asm sideeffect "xvldi ${0:u}, 1", "={$xr1}"()
|
||||
- ret void
|
||||
-}
|
||||
-
|
||||
-define void @register_xr7() nounwind {
|
||||
-; CHECK-LABEL: register_xr7:
|
||||
-; CHECK: # %bb.0: # %entry
|
||||
-; CHECK-NEXT: #APP
|
||||
-; CHECK-NEXT: xvldi $xr7, 1
|
||||
-; CHECK-NEXT: #NO_APP
|
||||
-; CHECK-NEXT: ret
|
||||
-entry:
|
||||
- %0 = tail call <4 x i64> asm sideeffect "xvldi ${0:u}, 1", "={$xr7}"()
|
||||
- ret void
|
||||
-}
|
||||
-
|
||||
-define void @register_xr23() nounwind {
|
||||
-; CHECK-LABEL: register_xr23:
|
||||
-; CHECK: # %bb.0: # %entry
|
||||
-; CHECK-NEXT: #APP
|
||||
-; CHECK-NEXT: xvldi $xr23, 1
|
||||
-; CHECK-NEXT: #NO_APP
|
||||
-; CHECK-NEXT: ret
|
||||
-entry:
|
||||
- %0 = tail call <4 x i64> asm sideeffect "xvldi ${0:u}, 1", "={$xr23}"()
|
||||
- ret void
|
||||
-}
|
||||
-
|
||||
-;; The lower 64-bit of the vector register '$xr31' is overlapped with
|
||||
-;; the floating-point register '$f31' ('$fs7'). And '$f31' ('$fs7')
|
||||
-;; is a callee-saved register which is preserved across calls.
|
||||
-;; That's why the fst.d and fld.d instructions are emitted.
|
||||
-define void @register_xr31() nounwind {
|
||||
-; CHECK-LABEL: register_xr31:
|
||||
-; CHECK: # %bb.0: # %entry
|
||||
-; CHECK-NEXT: addi.d $sp, $sp, -16
|
||||
-; CHECK-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill
|
||||
-; CHECK-NEXT: #APP
|
||||
-; CHECK-NEXT: xvldi $xr31, 1
|
||||
-; CHECK-NEXT: #NO_APP
|
||||
-; CHECK-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload
|
||||
-; CHECK-NEXT: addi.d $sp, $sp, 16
|
||||
-; CHECK-NEXT: ret
|
||||
-entry:
|
||||
- %0 = tail call <4 x i64> asm sideeffect "xvldi ${0:u}, 1", "={$xr31}"()
|
||||
- ret void
|
||||
-}
|
||||
diff --git a/llvm/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.ll b/llvm/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.ll
|
||||
deleted file mode 100644
|
||||
index c46e624ddaa8..000000000000
|
||||
--- a/llvm/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.ll
|
||||
+++ /dev/null
|
||||
@@ -1,14 +0,0 @@
|
||||
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
|
||||
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
|
||||
-
|
||||
-define void @test_w() nounwind {
|
||||
-; CHECK-LABEL: test_w:
|
||||
-; CHECK: # %bb.0: # %entry
|
||||
-; CHECK-NEXT: #APP
|
||||
-; CHECK-NEXT: vldi $vr0, 1
|
||||
-; CHECK-NEXT: #NO_APP
|
||||
-; CHECK-NEXT: ret
|
||||
-entry:
|
||||
- %0 = tail call <2 x i64> asm sideeffect "vldi ${0:w}, 1", "=f"()
|
||||
- ret void
|
||||
-}
|
||||
diff --git a/llvm/test/CodeGen/LoongArch/lsx/inline-asm-reg-names.ll b/llvm/test/CodeGen/LoongArch/lsx/inline-asm-reg-names.ll
|
||||
deleted file mode 100644
|
||||
index ceea3621be2f..000000000000
|
||||
--- a/llvm/test/CodeGen/LoongArch/lsx/inline-asm-reg-names.ll
|
||||
+++ /dev/null
|
||||
@@ -1,58 +0,0 @@
|
||||
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
|
||||
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
|
||||
-
|
||||
-define void @register_vr1() nounwind {
|
||||
-; CHECK-LABEL: register_vr1:
|
||||
-; CHECK: # %bb.0: # %entry
|
||||
-; CHECK-NEXT: #APP
|
||||
-; CHECK-NEXT: vldi $vr1, 1
|
||||
-; CHECK-NEXT: #NO_APP
|
||||
-; CHECK-NEXT: ret
|
||||
-entry:
|
||||
- %0 = tail call <2 x i64> asm sideeffect "vldi ${0:w}, 1", "={$vr1}"()
|
||||
- ret void
|
||||
-}
|
||||
-
|
||||
-define void @register_vr7() nounwind {
|
||||
-; CHECK-LABEL: register_vr7:
|
||||
-; CHECK: # %bb.0: # %entry
|
||||
-; CHECK-NEXT: #APP
|
||||
-; CHECK-NEXT: vldi $vr7, 1
|
||||
-; CHECK-NEXT: #NO_APP
|
||||
-; CHECK-NEXT: ret
|
||||
-entry:
|
||||
- %0 = tail call <2 x i64> asm sideeffect "vldi ${0:w}, 1", "={$vr7}"()
|
||||
- ret void
|
||||
-}
|
||||
-
|
||||
-define void @register_vr23() nounwind {
|
||||
-; CHECK-LABEL: register_vr23:
|
||||
-; CHECK: # %bb.0: # %entry
|
||||
-; CHECK-NEXT: #APP
|
||||
-; CHECK-NEXT: vldi $vr23, 1
|
||||
-; CHECK-NEXT: #NO_APP
|
||||
-; CHECK-NEXT: ret
|
||||
-entry:
|
||||
- %0 = tail call <2 x i64> asm sideeffect "vldi ${0:w}, 1", "={$vr23}"()
|
||||
- ret void
|
||||
-}
|
||||
-
|
||||
-;; The lower half of the vector register '$vr31' is overlapped with
|
||||
-;; the floating-point register '$f31'. And '$f31' is a callee-saved
|
||||
-;; register which is preserved across calls. That's why the
|
||||
-;; fst.d and fld.d instructions are emitted.
|
||||
-define void @register_vr31() nounwind {
|
||||
-; CHECK-LABEL: register_vr31:
|
||||
-; CHECK: # %bb.0: # %entry
|
||||
-; CHECK-NEXT: addi.d $sp, $sp, -16
|
||||
-; CHECK-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill
|
||||
-; CHECK-NEXT: #APP
|
||||
-; CHECK-NEXT: vldi $vr31, 1
|
||||
-; CHECK-NEXT: #NO_APP
|
||||
-; CHECK-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload
|
||||
-; CHECK-NEXT: addi.d $sp, $sp, 16
|
||||
-; CHECK-NEXT: ret
|
||||
-entry:
|
||||
- %0 = tail call <2 x i64> asm sideeffect "vldi ${0:w}, 1", "={$vr31}"()
|
||||
- ret void
|
||||
-}
|
||||
--
|
||||
2.27.0
|
||||
|
||||
Loading…
Reference in a new issue