035dbe6708
* initial IBRS/IBPB/SPEC_CTRL support * regression fixes for KPTI * additional hardening against Spectre based on Ubuntu-4.13.0-29.32 and mainline 4.14
64 lines
2.3 KiB
Diff
64 lines
2.3 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Nick Desaulniers <ndesaulniers@google.com>
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Date: Wed, 3 Jan 2018 12:39:52 -0800
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Subject: [PATCH] x86/process: Define cpu_tss_rw in same section as declaration
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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cpu_tss_rw is declared with DECLARE_PER_CPU_PAGE_ALIGNED
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but then defined with DEFINE_PER_CPU_SHARED_ALIGNED
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leading to section mismatch warnings.
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Use DEFINE_PER_CPU_PAGE_ALIGNED consistently. This is necessary because
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it's mapped to the cpu entry area and must be page aligned.
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[ tglx: Massaged changelog a bit ]
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Fixes: 1a935bc3d4ea ("x86/entry: Move SYSENTER_stack to the beginning of struct tss_struct")
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Suggested-by: Thomas Gleixner <tglx@linutronix.de>
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Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Cc: thomas.lendacky@amd.com
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Cc: Borislav Petkov <bpetkov@suse.de>
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Cc: tklauser@distanz.ch
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Cc: minipli@googlemail.com
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Cc: me@kylehuey.com
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Cc: namit@vmware.com
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Cc: luto@kernel.org
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Cc: jpoimboe@redhat.com
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Cc: tj@kernel.org
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Cc: cl@linux.com
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Cc: bp@suse.de
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Cc: thgarnie@google.com
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Cc: kirill.shutemov@linux.intel.com
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Cc: stable@vger.kernel.org
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Link: https://lkml.kernel.org/r/20180103203954.183360-1-ndesaulniers@google.com
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(cherry picked from commit 2fd9c41aea47f4ad071accf94b94f94f2c4d31eb)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit f45e574914ae47825d2eea46abc9d6fbabe55e56)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/kernel/process.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
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index 3688a7b9d055..07e6218ad7d9 100644
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--- a/arch/x86/kernel/process.c
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+++ b/arch/x86/kernel/process.c
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@@ -46,7 +46,7 @@
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* section. Since TSS's are completely CPU-local, we want them
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* on exact cacheline boundaries, to eliminate cacheline ping-pong.
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*/
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-__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss_rw) = {
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+__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
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.x86_tss = {
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/*
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* .sp0 is only used when entering ring 0 from a lower
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--
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2.14.2
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