a0f7ab8a6a
cherry-pick from upstream 4.14
86 lines
4.1 KiB
Diff
86 lines
4.1 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
|
From: Gayatri Kammela <gayatri.kammela@intel.com>
|
|
Date: Mon, 30 Oct 2017 18:20:29 -0700
|
|
Subject: [PATCH] x86/cpufeatures: Enable new SSE/AVX/AVX512 CPU features
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
CVE-2017-5754
|
|
|
|
Add a few new SSE/AVX/AVX512 instruction groups/features for enumeration
|
|
in /proc/cpuinfo: AVX512_VBMI2, GFNI, VAES, VPCLMULQDQ, AVX512_VNNI,
|
|
AVX512_BITALG.
|
|
|
|
CPUID.(EAX=7,ECX=0):ECX[bit 6] AVX512_VBMI2
|
|
CPUID.(EAX=7,ECX=0):ECX[bit 8] GFNI
|
|
CPUID.(EAX=7,ECX=0):ECX[bit 9] VAES
|
|
CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
|
|
CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512_VNNI
|
|
CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG
|
|
|
|
Detailed information of CPUID bits for these features can be found
|
|
in the Intel Architecture Instruction Set Extensions and Future Features
|
|
Programming Interface document (refer to Table 1-1. and Table 1-2.).
|
|
A copy of this document is available at
|
|
https://bugzilla.kernel.org/show_bug.cgi?id=197239
|
|
|
|
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
|
|
Acked-by: Thomas Gleixner <tglx@linutronix.de>
|
|
Cc: Andi Kleen <andi.kleen@intel.com>
|
|
Cc: Fenghua Yu <fenghua.yu@intel.com>
|
|
Cc: Linus Torvalds <torvalds@linux-foundation.org>
|
|
Cc: Peter Zijlstra <peterz@infradead.org>
|
|
Cc: Ravi Shankar <ravi.v.shankar@intel.com>
|
|
Cc: Ricardo Neri <ricardo.neri@intel.com>
|
|
Cc: Yang Zhong <yang.zhong@intel.com>
|
|
Cc: bp@alien8.de
|
|
Link: http://lkml.kernel.org/r/1509412829-23380-1-git-send-email-gayatri.kammela@intel.com
|
|
Signed-off-by: Ingo Molnar <mingo@kernel.org>
|
|
(cherry picked from commit c128dbfa0f879f8ce7b79054037889b0b2240728)
|
|
Signed-off-by: Andy Whitcroft <apw@canonical.com>
|
|
Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
|
|
(cherry picked from commit b29eb29c5aca4708d66fa977db40c779366636a2)
|
|
Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
|
|
---
|
|
arch/x86/include/asm/cpufeatures.h | 6 ++++++
|
|
arch/x86/kernel/cpu/cpuid-deps.c | 6 ++++++
|
|
2 files changed, 12 insertions(+)
|
|
|
|
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
|
|
index f4e145c4b06f..c465bd6613ed 100644
|
|
--- a/arch/x86/include/asm/cpufeatures.h
|
|
+++ b/arch/x86/include/asm/cpufeatures.h
|
|
@@ -297,6 +297,12 @@
|
|
#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
|
|
#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
|
|
#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
|
|
+#define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
|
|
+#define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */
|
|
+#define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */
|
|
+#define X86_FEATURE_VPCLMULQDQ (16*32+ 10) /* Carry-Less Multiplication Double Quadword */
|
|
+#define X86_FEATURE_AVX512_VNNI (16*32+ 11) /* Vector Neural Network Instructions */
|
|
+#define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB */
|
|
#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
|
|
#define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */
|
|
#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */
|
|
diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c
|
|
index c1d49842a411..c21f22d836ad 100644
|
|
--- a/arch/x86/kernel/cpu/cpuid-deps.c
|
|
+++ b/arch/x86/kernel/cpu/cpuid-deps.c
|
|
@@ -50,6 +50,12 @@ const static struct cpuid_dep cpuid_deps[] = {
|
|
{ X86_FEATURE_AVX512BW, X86_FEATURE_AVX512F },
|
|
{ X86_FEATURE_AVX512VL, X86_FEATURE_AVX512F },
|
|
{ X86_FEATURE_AVX512VBMI, X86_FEATURE_AVX512F },
|
|
+ { X86_FEATURE_AVX512_VBMI2, X86_FEATURE_AVX512VL },
|
|
+ { X86_FEATURE_GFNI, X86_FEATURE_AVX512VL },
|
|
+ { X86_FEATURE_VAES, X86_FEATURE_AVX512VL },
|
|
+ { X86_FEATURE_VPCLMULQDQ, X86_FEATURE_AVX512VL },
|
|
+ { X86_FEATURE_AVX512_VNNI, X86_FEATURE_AVX512VL },
|
|
+ { X86_FEATURE_AVX512_BITALG, X86_FEATURE_AVX512VL },
|
|
{ X86_FEATURE_AVX512_4VNNIW, X86_FEATURE_AVX512F },
|
|
{ X86_FEATURE_AVX512_4FMAPS, X86_FEATURE_AVX512F },
|
|
{ X86_FEATURE_AVX512_VPOPCNTDQ, X86_FEATURE_AVX512F },
|
|
--
|
|
2.14.2
|
|
|