62 lines
1.9 KiB
Diff
62 lines
1.9 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Elena Reshetova <elena.reshetova@intel.com>
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Date: Mon, 4 Sep 2017 13:11:43 +0300
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Subject: [PATCH] locking/barriers: introduce new memory barrier gmb()
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5753
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CVE-2017-5715
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In constrast to existing mb() and rmb() barriers,
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gmb() barrier is arch-independent and can be used to
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implement any type of memory barrier.
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In x86 case, it is either lfence or mfence, based on
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processor type. ARM and others can define it according
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to their needs.
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Suggested-by: Arjan van de Ven <arjan@linux.intel.com>
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Signed-off-by: Elena Reshetova <elena.reshetova@intel.com>
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Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com>
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 6834bd7e6159da957a6c01deebf16132a694bc23)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/barrier.h | 3 +++
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include/asm-generic/barrier.h | 4 ++++
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2 files changed, 7 insertions(+)
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diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h
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index bfb28caf97b1..aae78054cae2 100644
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--- a/arch/x86/include/asm/barrier.h
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+++ b/arch/x86/include/asm/barrier.h
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@@ -23,6 +23,9 @@
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#define wmb() asm volatile("sfence" ::: "memory")
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#endif
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+#define gmb() alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC, \
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+ "lfence", X86_FEATURE_LFENCE_RDTSC);
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+
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#ifdef CONFIG_X86_PPRO_FENCE
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#define dma_rmb() rmb()
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#else
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diff --git a/include/asm-generic/barrier.h b/include/asm-generic/barrier.h
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index fe297b599b0a..0ee1345c9222 100644
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--- a/include/asm-generic/barrier.h
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+++ b/include/asm-generic/barrier.h
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@@ -42,6 +42,10 @@
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#define wmb() mb()
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#endif
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+#ifndef gmb
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+#define gmb() do { } while (0)
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+#endif
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+
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#ifndef dma_rmb
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#define dma_rmb() rmb()
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#endif
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--
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2.14.2
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