275 lines
12 KiB
Diff
275 lines
12 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Dave Hansen <dave.hansen@linux.intel.com>
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Date: Fri, 5 Jan 2018 09:44:36 -0800
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Subject: [PATCH] x86/Documentation: Add PTI description
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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Add some details about how PTI works, what some of the downsides
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are, and how to debug it when things go wrong.
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Also document the kernel parameter: 'pti/nopti'.
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Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
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Reviewed-by: Kees Cook <keescook@chromium.org>
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Cc: Moritz Lipp <moritz.lipp@iaik.tugraz.at>
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Cc: Daniel Gruss <daniel.gruss@iaik.tugraz.at>
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Cc: Michael Schwarz <michael.schwarz@iaik.tugraz.at>
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Cc: Richard Fellner <richard.fellner@student.tugraz.at>
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Cc: Andy Lutomirski <luto@kernel.org>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Hugh Dickins <hughd@google.com>
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Cc: Andi Lutomirsky <luto@kernel.org>
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Cc: stable@vger.kernel.org
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Link: https://lkml.kernel.org/r/20180105174436.1BC6FA2B@viggo.jf.intel.com
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(cherry picked from commit 01c9b17bf673b05bb401b76ec763e9730ccf1376)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 1acf87c45b0170e717fc1b06a2d6fef47e07f79b)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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Documentation/admin-guide/kernel-parameters.txt | 21 ++-
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Documentation/x86/pti.txt | 186 ++++++++++++++++++++++++
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2 files changed, 200 insertions(+), 7 deletions(-)
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create mode 100644 Documentation/x86/pti.txt
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diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
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index b4d2edf316db..1a6ebc6cdf26 100644
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--- a/Documentation/admin-guide/kernel-parameters.txt
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+++ b/Documentation/admin-guide/kernel-parameters.txt
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@@ -2677,8 +2677,6 @@
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steal time is computed, but won't influence scheduler
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behaviour
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- nopti [X86-64] Disable kernel page table isolation
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-
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nolapic [X86-32,APIC] Do not enable or use the local APIC.
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nolapic_timer [X86-32,APIC] Do not use the local APIC timer.
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@@ -3247,11 +3245,20 @@
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pt. [PARIDE]
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See Documentation/blockdev/paride.txt.
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- pti= [X86_64]
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- Control user/kernel address space isolation:
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- on - enable
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- off - disable
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- auto - default setting
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+ pti= [X86_64] Control Page Table Isolation of user and
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+ kernel address spaces. Disabling this feature
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+ removes hardening, but improves performance of
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+ system calls and interrupts.
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+
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+ on - unconditionally enable
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+ off - unconditionally disable
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+ auto - kernel detects whether your CPU model is
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+ vulnerable to issues that PTI mitigates
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+
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+ Not specifying this option is equivalent to pti=auto.
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+
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+ nopti [X86_64]
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+ Equivalent to pti=off
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pty.legacy_count=
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[KNL] Number of legacy pty's. Overwrites compiled-in
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diff --git a/Documentation/x86/pti.txt b/Documentation/x86/pti.txt
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new file mode 100644
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index 000000000000..d11eff61fc9a
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--- /dev/null
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+++ b/Documentation/x86/pti.txt
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@@ -0,0 +1,186 @@
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+Overview
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+========
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+
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+Page Table Isolation (pti, previously known as KAISER[1]) is a
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+countermeasure against attacks on the shared user/kernel address
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+space such as the "Meltdown" approach[2].
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+
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+To mitigate this class of attacks, we create an independent set of
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+page tables for use only when running userspace applications. When
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+the kernel is entered via syscalls, interrupts or exceptions, the
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+page tables are switched to the full "kernel" copy. When the system
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+switches back to user mode, the user copy is used again.
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+
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+The userspace page tables contain only a minimal amount of kernel
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+data: only what is needed to enter/exit the kernel such as the
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+entry/exit functions themselves and the interrupt descriptor table
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+(IDT). There are a few strictly unnecessary things that get mapped
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+such as the first C function when entering an interrupt (see
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+comments in pti.c).
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+
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+This approach helps to ensure that side-channel attacks leveraging
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+the paging structures do not function when PTI is enabled. It can be
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+enabled by setting CONFIG_PAGE_TABLE_ISOLATION=y at compile time.
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+Once enabled at compile-time, it can be disabled at boot with the
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+'nopti' or 'pti=' kernel parameters (see kernel-parameters.txt).
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+
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+Page Table Management
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+=====================
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+
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+When PTI is enabled, the kernel manages two sets of page tables.
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+The first set is very similar to the single set which is present in
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+kernels without PTI. This includes a complete mapping of userspace
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+that the kernel can use for things like copy_to_user().
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+
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+Although _complete_, the user portion of the kernel page tables is
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+crippled by setting the NX bit in the top level. This ensures
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+that any missed kernel->user CR3 switch will immediately crash
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+userspace upon executing its first instruction.
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+
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+The userspace page tables map only the kernel data needed to enter
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+and exit the kernel. This data is entirely contained in the 'struct
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+cpu_entry_area' structure which is placed in the fixmap which gives
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+each CPU's copy of the area a compile-time-fixed virtual address.
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+
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+For new userspace mappings, the kernel makes the entries in its
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+page tables like normal. The only difference is when the kernel
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+makes entries in the top (PGD) level. In addition to setting the
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+entry in the main kernel PGD, a copy of the entry is made in the
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+userspace page tables' PGD.
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+
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+This sharing at the PGD level also inherently shares all the lower
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+layers of the page tables. This leaves a single, shared set of
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+userspace page tables to manage. One PTE to lock, one set of
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+accessed bits, dirty bits, etc...
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+
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+Overhead
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+========
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+
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+Protection against side-channel attacks is important. But,
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+this protection comes at a cost:
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+
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+1. Increased Memory Use
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+ a. Each process now needs an order-1 PGD instead of order-0.
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+ (Consumes an additional 4k per process).
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+ b. The 'cpu_entry_area' structure must be 2MB in size and 2MB
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+ aligned so that it can be mapped by setting a single PMD
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+ entry. This consumes nearly 2MB of RAM once the kernel
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+ is decompressed, but no space in the kernel image itself.
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+
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+2. Runtime Cost
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+ a. CR3 manipulation to switch between the page table copies
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+ must be done at interrupt, syscall, and exception entry
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+ and exit (it can be skipped when the kernel is interrupted,
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+ though.) Moves to CR3 are on the order of a hundred
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+ cycles, and are required at every entry and exit.
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+ b. A "trampoline" must be used for SYSCALL entry. This
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+ trampoline depends on a smaller set of resources than the
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+ non-PTI SYSCALL entry code, so requires mapping fewer
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+ things into the userspace page tables. The downside is
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+ that stacks must be switched at entry time.
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+ d. Global pages are disabled for all kernel structures not
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+ mapped into both kernel and userspace page tables. This
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+ feature of the MMU allows different processes to share TLB
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+ entries mapping the kernel. Losing the feature means more
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+ TLB misses after a context switch. The actual loss of
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+ performance is very small, however, never exceeding 1%.
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+ d. Process Context IDentifiers (PCID) is a CPU feature that
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+ allows us to skip flushing the entire TLB when switching page
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+ tables by setting a special bit in CR3 when the page tables
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+ are changed. This makes switching the page tables (at context
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+ switch, or kernel entry/exit) cheaper. But, on systems with
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+ PCID support, the context switch code must flush both the user
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+ and kernel entries out of the TLB. The user PCID TLB flush is
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+ deferred until the exit to userspace, minimizing the cost.
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+ See intel.com/sdm for the gory PCID/INVPCID details.
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+ e. The userspace page tables must be populated for each new
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+ process. Even without PTI, the shared kernel mappings
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+ are created by copying top-level (PGD) entries into each
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+ new process. But, with PTI, there are now *two* kernel
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+ mappings: one in the kernel page tables that maps everything
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+ and one for the entry/exit structures. At fork(), we need to
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+ copy both.
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+ f. In addition to the fork()-time copying, there must also
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+ be an update to the userspace PGD any time a set_pgd() is done
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+ on a PGD used to map userspace. This ensures that the kernel
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+ and userspace copies always map the same userspace
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+ memory.
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+ g. On systems without PCID support, each CR3 write flushes
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+ the entire TLB. That means that each syscall, interrupt
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+ or exception flushes the TLB.
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+ h. INVPCID is a TLB-flushing instruction which allows flushing
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+ of TLB entries for non-current PCIDs. Some systems support
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+ PCIDs, but do not support INVPCID. On these systems, addresses
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+ can only be flushed from the TLB for the current PCID. When
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+ flushing a kernel address, we need to flush all PCIDs, so a
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+ single kernel address flush will require a TLB-flushing CR3
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+ write upon the next use of every PCID.
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+
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+Possible Future Work
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+====================
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+1. We can be more careful about not actually writing to CR3
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+ unless its value is actually changed.
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+2. Allow PTI to be enabled/disabled at runtime in addition to the
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+ boot-time switching.
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+
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+Testing
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+========
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+
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+To test stability of PTI, the following test procedure is recommended,
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+ideally doing all of these in parallel:
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+
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+1. Set CONFIG_DEBUG_ENTRY=y
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+2. Run several copies of all of the tools/testing/selftests/x86/ tests
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+ (excluding MPX and protection_keys) in a loop on multiple CPUs for
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+ several minutes. These tests frequently uncover corner cases in the
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+ kernel entry code. In general, old kernels might cause these tests
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+ themselves to crash, but they should never crash the kernel.
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+3. Run the 'perf' tool in a mode (top or record) that generates many
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+ frequent performance monitoring non-maskable interrupts (see "NMI"
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+ in /proc/interrupts). This exercises the NMI entry/exit code which
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+ is known to trigger bugs in code paths that did not expect to be
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+ interrupted, including nested NMIs. Using "-c" boosts the rate of
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+ NMIs, and using two -c with separate counters encourages nested NMIs
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+ and less deterministic behavior.
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+
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+ while true; do perf record -c 10000 -e instructions,cycles -a sleep 10; done
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+
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+4. Launch a KVM virtual machine.
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+5. Run 32-bit binaries on systems supporting the SYSCALL instruction.
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+ This has been a lightly-tested code path and needs extra scrutiny.
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+
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+Debugging
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+=========
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+
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+Bugs in PTI cause a few different signatures of crashes
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+that are worth noting here.
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+
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+ * Failures of the selftests/x86 code. Usually a bug in one of the
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+ more obscure corners of entry_64.S
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+ * Crashes in early boot, especially around CPU bringup. Bugs
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+ in the trampoline code or mappings cause these.
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+ * Crashes at the first interrupt. Caused by bugs in entry_64.S,
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+ like screwing up a page table switch. Also caused by
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+ incorrectly mapping the IRQ handler entry code.
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+ * Crashes at the first NMI. The NMI code is separate from main
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+ interrupt handlers and can have bugs that do not affect
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+ normal interrupts. Also caused by incorrectly mapping NMI
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+ code. NMIs that interrupt the entry code must be very
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+ careful and can be the cause of crashes that show up when
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+ running perf.
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+ * Kernel crashes at the first exit to userspace. entry_64.S
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+ bugs, or failing to map some of the exit code.
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+ * Crashes at first interrupt that interrupts userspace. The paths
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+ in entry_64.S that return to userspace are sometimes separate
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+ from the ones that return to the kernel.
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+ * Double faults: overflowing the kernel stack because of page
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+ faults upon page faults. Caused by touching non-pti-mapped
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+ data in the entry code, or forgetting to switch to kernel
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+ CR3 before calling into C functions which are not pti-mapped.
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+ * Userspace segfaults early in boot, sometimes manifesting
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+ as mount(8) failing to mount the rootfs. These have
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+ tended to be TLB invalidation issues. Usually invalidating
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+ the wrong PCID, or otherwise missing an invalidation.
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+
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+1. https://gruss.cc/files/kaiser.pdf
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+2. https://meltdownattack.com/meltdown.pdf
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--
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2.14.2
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