161 lines
5.5 KiB
Diff
161 lines
5.5 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Andy Lutomirski <luto@kernel.org>
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Date: Mon, 4 Dec 2017 15:07:21 +0100
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Subject: [PATCH] x86/entry/64: Separate cpu_current_top_of_stack from TSS.sp0
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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On 64-bit kernels, we used to assume that TSS.sp0 was the current
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top of stack. With the addition of an entry trampoline, this will
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no longer be the case. Store the current top of stack in TSS.sp1,
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which is otherwise unused but shares the same cacheline.
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Signed-off-by: Andy Lutomirski <luto@kernel.org>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Borislav Petkov <bp@suse.de>
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Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Borislav Petkov <bpetkov@suse.de>
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Cc: Brian Gerst <brgerst@gmail.com>
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Cc: Dave Hansen <dave.hansen@intel.com>
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Cc: Dave Hansen <dave.hansen@linux.intel.com>
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Cc: David Laight <David.Laight@aculab.com>
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Cc: Denys Vlasenko <dvlasenk@redhat.com>
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Cc: Eduardo Valentin <eduval@amazon.com>
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Cc: Greg KH <gregkh@linuxfoundation.org>
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Cc: H. Peter Anvin <hpa@zytor.com>
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Cc: Josh Poimboeuf <jpoimboe@redhat.com>
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Cc: Juergen Gross <jgross@suse.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Rik van Riel <riel@redhat.com>
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Cc: Will Deacon <will.deacon@arm.com>
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Cc: aliguori@amazon.com
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Cc: daniel.gruss@iaik.tugraz.at
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Cc: hughd@google.com
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Cc: keescook@google.com
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Link: https://lkml.kernel.org/r/20171204150606.050864668@linutronix.de
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(cherry picked from commit 9aaefe7b59ae00605256a7d6bd1c1456432495fc)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 281be4ff07f7c67dc2a9c75ab24a7b9ff25544ae)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/processor.h | 18 +++++++++++++-----
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arch/x86/include/asm/thread_info.h | 2 +-
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arch/x86/kernel/asm-offsets_64.c | 1 +
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arch/x86/kernel/process.c | 10 ++++++++++
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arch/x86/kernel/process_64.c | 1 +
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5 files changed, 26 insertions(+), 6 deletions(-)
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diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
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index 55885465c3a7..1bfe4bad797a 100644
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--- a/arch/x86/include/asm/processor.h
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+++ b/arch/x86/include/asm/processor.h
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@@ -303,7 +303,13 @@ struct x86_hw_tss {
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struct x86_hw_tss {
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u32 reserved1;
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u64 sp0;
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+
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+ /*
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+ * We store cpu_current_top_of_stack in sp1 so it's always accessible.
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+ * Linux does not use ring 1, so sp1 is not otherwise needed.
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+ */
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u64 sp1;
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+
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u64 sp2;
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u64 reserved2;
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u64 ist[7];
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@@ -362,6 +368,8 @@ DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss);
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#ifdef CONFIG_X86_32
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DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
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+#else
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+#define cpu_current_top_of_stack cpu_tss.x86_tss.sp1
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#endif
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/*
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@@ -533,12 +541,12 @@ static inline void native_swapgs(void)
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static inline unsigned long current_top_of_stack(void)
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{
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-#ifdef CONFIG_X86_64
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- return this_cpu_read_stable(cpu_tss.x86_tss.sp0);
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-#else
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- /* sp0 on x86_32 is special in and around vm86 mode. */
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+ /*
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+ * We can't read directly from tss.sp0: sp0 on x86_32 is special in
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+ * and around vm86 mode and sp0 on x86_64 is special because of the
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+ * entry trampoline.
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+ */
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return this_cpu_read_stable(cpu_current_top_of_stack);
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-#endif
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}
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static inline bool on_thread_stack(void)
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diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
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index ec8ef3bbb7dc..760dd8a73927 100644
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--- a/arch/x86/include/asm/thread_info.h
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+++ b/arch/x86/include/asm/thread_info.h
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@@ -214,7 +214,7 @@ static inline int arch_within_stack_frames(const void * const stack,
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#else /* !__ASSEMBLY__ */
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#ifdef CONFIG_X86_64
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-# define cpu_current_top_of_stack (cpu_tss + TSS_sp0)
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+# define cpu_current_top_of_stack (cpu_tss + TSS_sp1)
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#endif
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#endif
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diff --git a/arch/x86/kernel/asm-offsets_64.c b/arch/x86/kernel/asm-offsets_64.c
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index c21a5315b38e..048f68ff3396 100644
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--- a/arch/x86/kernel/asm-offsets_64.c
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+++ b/arch/x86/kernel/asm-offsets_64.c
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@@ -65,6 +65,7 @@ int main(void)
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OFFSET(TSS_ist, tss_struct, x86_tss.ist);
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OFFSET(TSS_sp0, tss_struct, x86_tss.sp0);
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+ OFFSET(TSS_sp1, tss_struct, x86_tss.sp1);
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BLANK();
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#ifdef CONFIG_CC_STACKPROTECTOR
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diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
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index aa86e810fb54..407fc37a8718 100644
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--- a/arch/x86/kernel/process.c
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+++ b/arch/x86/kernel/process.c
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@@ -55,6 +55,16 @@ __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = {
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* Poison it.
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*/
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.sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
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+
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+#ifdef CONFIG_X86_64
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+ /*
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+ * .sp1 is cpu_current_top_of_stack. The init task never
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+ * runs user code, but cpu_current_top_of_stack should still
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+ * be well defined before the first context switch.
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+ */
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+ .sp1 = TOP_OF_INIT_STACK,
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+#endif
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+
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#ifdef CONFIG_X86_32
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.ss0 = __KERNEL_DS,
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.ss1 = __KERNEL_CS,
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diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
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index 01b119bebb68..157f81816915 100644
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--- a/arch/x86/kernel/process_64.c
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+++ b/arch/x86/kernel/process_64.c
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@@ -461,6 +461,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
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* Switch the PDA and FPU contexts.
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*/
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this_cpu_write(current_task, next_p);
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+ this_cpu_write(cpu_current_top_of_stack, task_top_of_stack(next_p));
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/* Reload sp0. */
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update_sp0(next_p);
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--
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2.14.2
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