fix #1366: pinctl fix for AMD Ryzen on Gigabyte MBs
This commit is contained in:
Fabian Grünbichler
parent
d8cc30e0cd
commit
5aa54b7501
3 changed files with 470 additions and 0 deletions
2
Makefile
2
Makefile
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@ -241,6 +241,8 @@ ${KERNEL_SRC}/README ${KERNEL_CFG_ORG}: ${KERNEL_SRC_SUBMODULE} | submodules
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cd ${KERNEL_SRC}; patch -p1 < ../CVE-2017-9075-sctp-do-not-inherit-ipv6_-mc-ac-fl-_list-from-parent.patch
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cd ${KERNEL_SRC}; patch -p1 < ../CVE-2017-9075-sctp-do-not-inherit-ipv6_-mc-ac-fl-_list-from-parent.patch
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cd ${KERNEL_SRC}; patch -p1 < ../CVE-2017-9076_9077-ipv6-dccp-do-not-inherit-ipv6_mc_list-from-parent.patch
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cd ${KERNEL_SRC}; patch -p1 < ../CVE-2017-9076_9077-ipv6-dccp-do-not-inherit-ipv6_mc_list-from-parent.patch
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cd ${KERNEL_SRC}; patch -p1 < ../CVE-2017-9242-ipv6-fix-out-of-bound-writes-in-__ip6_append_data.patch
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cd ${KERNEL_SRC}; patch -p1 < ../CVE-2017-9242-ipv6-fix-out-of-bound-writes-in-__ip6_append_data.patch
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cd ${KERNEL_SRC}; patch -p1 < ../pinctl-amd-ryzen-01-make-use-of-raw_spinlock-variants.patch
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cd ${KERNEL_SRC}; patch -p1 < ../pinctl-amd-ryzen-02-Use-regular-interrupt-instead-of-chained.patch
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sed -i ${KERNEL_SRC}/Makefile -e 's/^EXTRAVERSION.*$$/EXTRAVERSION=${EXTRAVERSION}/'
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sed -i ${KERNEL_SRC}/Makefile -e 's/^EXTRAVERSION.*$$/EXTRAVERSION=${EXTRAVERSION}/'
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touch $@
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touch $@
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303
pinctl-amd-ryzen-01-make-use-of-raw_spinlock-variants.patch
Normal file
303
pinctl-amd-ryzen-01-make-use-of-raw_spinlock-variants.patch
Normal file
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@ -0,0 +1,303 @@
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From 78388cbea036c9a9e2fd0c71e21d608cfc63939a Mon Sep 17 00:00:00 2001
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From: Julia Cartwright <julia@ni.com>
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Date: Thu, 1 Jun 2017 13:12:16 +0800
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Subject: [PATCH] pinctrl: amd: make use of raw_spinlock variants
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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BugLink: https://bugs.launchpad.net/bugs/1671360
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The amd pinctrl drivers currently implement an irq_chip for handling
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interrupts; due to how irq_chip handling is done, it's necessary for the
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irq_chip methods to be invoked from hardirq context, even on a a
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real-time kernel. Because the spinlock_t type becomes a "sleeping"
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spinlock w/ RT kernels, it is not suitable to be used with irq_chips.
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A quick audit of the operations under the lock reveal that they do only
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minimal, bounded work, and are therefore safe to do under a raw spinlock.
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Signed-off-by: Julia Cartwright <julia@ni.com>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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(cherry picked from commit 229710fecdd805abb753c480778ea0de47cbb1e2)
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Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
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Acked-by: Stefan Bader <stefan.bader@canonical.com>
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Acked-by: Seth Forshee <seth.forshee@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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drivers/pinctrl/pinctrl-amd.h | 2 +-
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drivers/pinctrl/pinctrl-amd.c | 66 +++++++++++++++++++++----------------------
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2 files changed, 34 insertions(+), 34 deletions(-)
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diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h
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index 7bfea47dbb47..4d5d5cac48a9 100644
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--- a/drivers/pinctrl/pinctrl-amd.h
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+++ b/drivers/pinctrl/pinctrl-amd.h
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@@ -86,7 +86,7 @@ struct amd_function {
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};
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struct amd_gpio {
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- spinlock_t lock;
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+ raw_spinlock_t lock;
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void __iomem *base;
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const struct amd_pingroup *groups;
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diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
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index 537b52055756..cfcf9db02c7d 100644
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--- a/drivers/pinctrl/pinctrl-amd.c
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+++ b/drivers/pinctrl/pinctrl-amd.c
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@@ -41,11 +41,11 @@ static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
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u32 pin_reg;
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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- spin_lock_irqsave(&gpio_dev->lock, flags);
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+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + offset * 4);
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pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
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writel(pin_reg, gpio_dev->base + offset * 4);
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- spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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return 0;
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}
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@@ -57,7 +57,7 @@ static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
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unsigned long flags;
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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- spin_lock_irqsave(&gpio_dev->lock, flags);
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+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + offset * 4);
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pin_reg |= BIT(OUTPUT_ENABLE_OFF);
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if (value)
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@@ -65,7 +65,7 @@ static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
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else
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pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
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writel(pin_reg, gpio_dev->base + offset * 4);
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- spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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return 0;
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}
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@@ -76,9 +76,9 @@ static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
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unsigned long flags;
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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- spin_lock_irqsave(&gpio_dev->lock, flags);
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+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + offset * 4);
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- spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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return !!(pin_reg & BIT(PIN_STS_OFF));
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}
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@@ -89,14 +89,14 @@ static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
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unsigned long flags;
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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- spin_lock_irqsave(&gpio_dev->lock, flags);
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+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + offset * 4);
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if (value)
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pin_reg |= BIT(OUTPUT_VALUE_OFF);
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else
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pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
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writel(pin_reg, gpio_dev->base + offset * 4);
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- spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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}
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static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
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@@ -108,7 +108,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
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unsigned long flags;
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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- spin_lock_irqsave(&gpio_dev->lock, flags);
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+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + offset * 4);
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if (debounce) {
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@@ -159,7 +159,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
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pin_reg &= ~DB_CNTRl_MASK;
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}
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writel(pin_reg, gpio_dev->base + offset * 4);
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- spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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return ret;
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}
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@@ -208,9 +208,9 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
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for (; i < pin_num; i++) {
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seq_printf(s, "pin%d\t", i);
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- spin_lock_irqsave(&gpio_dev->lock, flags);
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+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + i * 4);
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- spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
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interrupt_enable = "interrupt is enabled|";
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@@ -315,12 +315,12 @@ static void amd_gpio_irq_enable(struct irq_data *d)
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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- spin_lock_irqsave(&gpio_dev->lock, flags);
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+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
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pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
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pin_reg |= BIT(INTERRUPT_MASK_OFF);
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writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
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- spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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}
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static void amd_gpio_irq_disable(struct irq_data *d)
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@@ -330,12 +330,12 @@ static void amd_gpio_irq_disable(struct irq_data *d)
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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- spin_lock_irqsave(&gpio_dev->lock, flags);
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+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
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pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
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pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
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writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
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- spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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}
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static void amd_gpio_irq_mask(struct irq_data *d)
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@@ -345,11 +345,11 @@ static void amd_gpio_irq_mask(struct irq_data *d)
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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- spin_lock_irqsave(&gpio_dev->lock, flags);
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+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
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pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
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writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
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- spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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}
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static void amd_gpio_irq_unmask(struct irq_data *d)
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@@ -359,11 +359,11 @@ static void amd_gpio_irq_unmask(struct irq_data *d)
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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- spin_lock_irqsave(&gpio_dev->lock, flags);
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+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
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pin_reg |= BIT(INTERRUPT_MASK_OFF);
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writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
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- spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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}
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static void amd_gpio_irq_eoi(struct irq_data *d)
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@@ -373,11 +373,11 @@ static void amd_gpio_irq_eoi(struct irq_data *d)
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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- spin_lock_irqsave(&gpio_dev->lock, flags);
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+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
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reg |= EOI_MASK;
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writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
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- spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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}
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static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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@@ -388,7 +388,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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- spin_lock_irqsave(&gpio_dev->lock, flags);
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+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
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/* Ignore the settings coming from the client and
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@@ -453,7 +453,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
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writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
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- spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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return ret;
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}
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@@ -494,14 +494,14 @@ static void amd_gpio_irq_handler(struct irq_desc *desc)
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chained_irq_enter(chip, desc);
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/*enable GPIO interrupt again*/
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- spin_lock_irqsave(&gpio_dev->lock, flags);
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+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
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reg64 = reg;
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reg64 = reg64 << 32;
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reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
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reg64 |= reg;
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- spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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/*
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* first 46 bits indicates interrupt status.
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@@ -529,11 +529,11 @@ static void amd_gpio_irq_handler(struct irq_desc *desc)
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if (handled == 0)
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handle_bad_irq(desc);
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- spin_lock_irqsave(&gpio_dev->lock, flags);
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+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
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reg |= EOI_MASK;
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writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
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- spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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chained_irq_exit(chip, desc);
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}
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@@ -585,9 +585,9 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev,
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struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
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enum pin_config_param param = pinconf_to_config_param(*config);
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- spin_lock_irqsave(&gpio_dev->lock, flags);
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+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + pin*4);
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- spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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switch (param) {
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case PIN_CONFIG_INPUT_DEBOUNCE:
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arg = pin_reg & DB_TMR_OUT_MASK;
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@@ -627,7 +627,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
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enum pin_config_param param;
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||||||
|
struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
|
||||||
|
|
||||||
|
- spin_lock_irqsave(&gpio_dev->lock, flags);
|
||||||
|
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
|
||||||
|
for (i = 0; i < num_configs; i++) {
|
||||||
|
param = pinconf_to_config_param(configs[i]);
|
||||||
|
arg = pinconf_to_config_argument(configs[i]);
|
||||||
|
@@ -666,7 +666,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||||
|
|
||||||
|
writel(pin_reg, gpio_dev->base + pin*4);
|
||||||
|
}
|
||||||
|
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
|
||||||
|
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
@@ -734,7 +734,7 @@ static int amd_gpio_probe(struct platform_device *pdev)
|
||||||
|
if (!gpio_dev)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
- spin_lock_init(&gpio_dev->lock);
|
||||||
|
+ raw_spin_lock_init(&gpio_dev->lock);
|
||||||
|
|
||||||
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||||
|
if (!res) {
|
||||||
|
--
|
||||||
|
2.11.0
|
||||||
|
|
||||||
|
|
@ -0,0 +1,165 @@
|
||||||
|
From c075f8efc5513551233dabce366eed01e32b62a4 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Thomas Gleixner <tglx@linutronix.de>
|
||||||
|
Date: Thu, 1 Jun 2017 13:12:18 +0800
|
||||||
|
Subject: [PATCH] pinctrl/amd: Use regular interrupt instead of chained
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
BugLink: https://bugs.launchpad.net/bugs/1671360
|
||||||
|
|
||||||
|
The AMD pinctrl driver uses a chained interrupt to demultiplex the GPIO
|
||||||
|
interrupts. Kevin Vandeventer reported, that his new AMD Ryzen locks up
|
||||||
|
hard on boot when the AMD pinctrl driver is initialized. The reason is an
|
||||||
|
interrupt storm. It's not clear whether that's caused by hardware or
|
||||||
|
firmware or both.
|
||||||
|
|
||||||
|
Using chained interrupts on X86 is a dangerous endavour. If a system is
|
||||||
|
misconfigured or the hardware buggy there is no safety net to catch an
|
||||||
|
interrupt storm.
|
||||||
|
|
||||||
|
Convert the driver to use a regular interrupt for the demultiplex
|
||||||
|
handler. This allows the interrupt storm detector to catch the malfunction
|
||||||
|
and lets the system boot up.
|
||||||
|
|
||||||
|
This should be backported to stable because it's likely that more users run
|
||||||
|
into this problem as the AMD Ryzen machines are spreading.
|
||||||
|
|
||||||
|
Reported-by: Kevin Vandeventer
|
||||||
|
Link: https://bugzilla.suse.com/show_bug.cgi?id=1034261
|
||||||
|
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
|
||||||
|
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
||||||
|
(backported from commit babdc22b0ccf4ef5a3075ce6e4afc26b7a279faf linux-next)
|
||||||
|
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
|
||||||
|
Acked-by: Stefan Bader <stefan.bader@canonical.com>
|
||||||
|
Acked-by: Seth Forshee <seth.forshee@canonical.com>
|
||||||
|
Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
|
||||||
|
|
||||||
|
Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
|
||||||
|
---
|
||||||
|
drivers/pinctrl/pinctrl-amd.c | 90 +++++++++++++++++++------------------------
|
||||||
|
1 file changed, 40 insertions(+), 50 deletions(-)
|
||||||
|
|
||||||
|
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
|
||||||
|
index cfcf9db02c7d..07a88b83e02b 100644
|
||||||
|
--- a/drivers/pinctrl/pinctrl-amd.c
|
||||||
|
+++ b/drivers/pinctrl/pinctrl-amd.c
|
||||||
|
@@ -478,64 +478,54 @@ static struct irq_chip amd_gpio_irqchip = {
|
||||||
|
.irq_set_type = amd_gpio_irq_set_type,
|
||||||
|
};
|
||||||
|
|
||||||
|
-static void amd_gpio_irq_handler(struct irq_desc *desc)
|
||||||
|
+#define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
|
||||||
|
+
|
||||||
|
+static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
|
||||||
|
{
|
||||||
|
- u32 i;
|
||||||
|
- u32 off;
|
||||||
|
- u32 reg;
|
||||||
|
- u32 pin_reg;
|
||||||
|
- u64 reg64;
|
||||||
|
- int handled = 0;
|
||||||
|
- unsigned int irq;
|
||||||
|
+ struct amd_gpio *gpio_dev = dev_id;
|
||||||
|
+ struct gpio_chip *gc = &gpio_dev->gc;
|
||||||
|
+ irqreturn_t ret = IRQ_NONE;
|
||||||
|
+ unsigned int i, irqnr;
|
||||||
|
unsigned long flags;
|
||||||
|
- struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||||
|
- struct gpio_chip *gc = irq_desc_get_handler_data(desc);
|
||||||
|
- struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
|
||||||
|
+ u32 *regs, regval;
|
||||||
|
+ u64 status, mask;
|
||||||
|
|
||||||
|
- chained_irq_enter(chip, desc);
|
||||||
|
- /*enable GPIO interrupt again*/
|
||||||
|
+ /* Read the wake status */
|
||||||
|
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
|
||||||
|
- reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
|
||||||
|
- reg64 = reg;
|
||||||
|
- reg64 = reg64 << 32;
|
||||||
|
-
|
||||||
|
- reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
|
||||||
|
- reg64 |= reg;
|
||||||
|
+ status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
|
||||||
|
+ status <<= 32;
|
||||||
|
+ status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
|
||||||
|
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
|
||||||
|
|
||||||
|
- /*
|
||||||
|
- * first 46 bits indicates interrupt status.
|
||||||
|
- * one bit represents four interrupt sources.
|
||||||
|
- */
|
||||||
|
- for (off = 0; off < 46 ; off++) {
|
||||||
|
- if (reg64 & BIT(off)) {
|
||||||
|
- for (i = 0; i < 4; i++) {
|
||||||
|
- pin_reg = readl(gpio_dev->base +
|
||||||
|
- (off * 4 + i) * 4);
|
||||||
|
- if ((pin_reg & BIT(INTERRUPT_STS_OFF)) ||
|
||||||
|
- (pin_reg & BIT(WAKE_STS_OFF))) {
|
||||||
|
- irq = irq_find_mapping(gc->irqdomain,
|
||||||
|
- off * 4 + i);
|
||||||
|
- generic_handle_irq(irq);
|
||||||
|
- writel(pin_reg,
|
||||||
|
- gpio_dev->base
|
||||||
|
- + (off * 4 + i) * 4);
|
||||||
|
- handled++;
|
||||||
|
- }
|
||||||
|
- }
|
||||||
|
+ /* Bit 0-45 contain the relevant status bits */
|
||||||
|
+ status &= (1ULL << 46) - 1;
|
||||||
|
+ regs = gpio_dev->base;
|
||||||
|
+ for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
|
||||||
|
+ if (!(status & mask))
|
||||||
|
+ continue;
|
||||||
|
+ status &= ~mask;
|
||||||
|
+
|
||||||
|
+ /* Each status bit covers four pins */
|
||||||
|
+ for (i = 0; i < 4; i++) {
|
||||||
|
+ regval = readl(regs + i);
|
||||||
|
+ if (!(regval & PIN_IRQ_PENDING))
|
||||||
|
+ continue;
|
||||||
|
+ irq = irq_find_mapping(gc->irqdomain, irqnr + i);
|
||||||
|
+ generic_handle_irq(irq);
|
||||||
|
+ /* Clear interrupt */
|
||||||
|
+ writel(regval, regs + i);
|
||||||
|
+ ret = IRQ_HANDLED;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
- if (handled == 0)
|
||||||
|
- handle_bad_irq(desc);
|
||||||
|
-
|
||||||
|
+ /* Signal EOI to the GPIO unit */
|
||||||
|
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
|
||||||
|
- reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
|
||||||
|
- reg |= EOI_MASK;
|
||||||
|
- writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
|
||||||
|
+ regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
|
||||||
|
+ regval |= EOI_MASK;
|
||||||
|
+ writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
|
||||||
|
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
|
||||||
|
|
||||||
|
- chained_irq_exit(chip, desc);
|
||||||
|
+ return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int amd_get_groups_count(struct pinctrl_dev *pctldev)
|
||||||
|
@@ -803,10 +793,10 @@ static int amd_gpio_probe(struct platform_device *pdev)
|
||||||
|
goto out2;
|
||||||
|
}
|
||||||
|
|
||||||
|
- gpiochip_set_chained_irqchip(&gpio_dev->gc,
|
||||||
|
- &amd_gpio_irqchip,
|
||||||
|
- irq_base,
|
||||||
|
- amd_gpio_irq_handler);
|
||||||
|
+ ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0,
|
||||||
|
+ KBUILD_MODNAME, gpio_dev);
|
||||||
|
+ if (ret)
|
||||||
|
+ goto out2;
|
||||||
|
|
||||||
|
platform_set_drvdata(pdev, gpio_dev);
|
||||||
|
|
||||||
|
--
|
||||||
|
2.11.0
|
||||||
|
|
||||||
Loading…
Reference in a new issue