add EDAC cherry-picks
This commit is contained in:
Fabian Grünbichler
parent
a70918fbbc
commit
1da60899e3
2 changed files with 139 additions and 0 deletions
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
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Date: Wed, 13 Sep 2017 18:42:14 +0800
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Subject: [PATCH] EDAC, sb_edac: Don't create a second memory controller if HA1
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is not present
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Yi Zhang reported the following failure on a 2-socket Haswell (E5-2603v3)
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server (DELL PowerEdge 730xd):
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EDAC sbridge: Some needed devices are missing
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EDAC MC: Removed device 0 for sb_edac.c Haswell SrcID#0_Ha#0: DEV 0000:7f:12.0
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EDAC MC: Removed device 1 for sb_edac.c Haswell SrcID#1_Ha#0: DEV 0000:ff:12.0
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EDAC sbridge: Couldn't find mci handler
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EDAC sbridge: Couldn't find mci handler
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EDAC sbridge: Failed to register device with error -19.
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The refactored sb_edac driver creates the IMC1 (the 2nd memory
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controller) if any IMC1 device is present. In this case only
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HA1_TA of IMC1 was present, but the driver expected to find
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HA1/HA1_TM/HA1_TAD[0-3] devices too, leading to the above failure.
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The document [1] says the 'E5-2603 v3' CPU has 4 memory channels max. Yi
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Zhang inserted one DIMM per channel for each CPU, and did random error
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address injection test with this patch:
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4024 addresses fell in TOLM hole area
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12715 addresses fell in CPU_SrcID#0_Ha#0_Chan#0_DIMM#0
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12774 addresses fell in CPU_SrcID#0_Ha#0_Chan#1_DIMM#0
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12798 addresses fell in CPU_SrcID#0_Ha#0_Chan#2_DIMM#0
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12913 addresses fell in CPU_SrcID#0_Ha#0_Chan#3_DIMM#0
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12674 addresses fell in CPU_SrcID#1_Ha#0_Chan#0_DIMM#0
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12686 addresses fell in CPU_SrcID#1_Ha#0_Chan#1_DIMM#0
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12882 addresses fell in CPU_SrcID#1_Ha#0_Chan#2_DIMM#0
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12934 addresses fell in CPU_SrcID#1_Ha#0_Chan#3_DIMM#0
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106400 addresses were injected totally.
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The test result shows that all the 4 channels belong to IMC0 per CPU, so
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the server really only has one IMC per CPU.
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In the 1st page of chapter 2 in datasheet [2], it also says 'E5-2600 v3'
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implements either one or two IMCs. For CPUs with one IMC, IMC1 is not
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used and should be ignored.
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Thus, do not create a second memory controller if the key HA1 is absent.
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[1] http://ark.intel.com/products/83349/Intel-Xeon-Processor-E5-2603-v3-15M-Cache-1_60-GHz
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[2] https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v3-datasheet-vol-2.pdf
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Reported-and-tested-by: Yi Zhang <yizhan@redhat.com>
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Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
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Cc: Tony Luck <tony.luck@intel.com>
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Cc: linux-edac <linux-edac@vger.kernel.org>
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Fixes: e2f747b1f42a ("EDAC, sb_edac: Assign EDAC memory controller per h/w controller")
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Link: http://lkml.kernel.org/r/20170913104214.7325-1-qiuxu.zhuo@intel.com
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[ Massage commit message. ]
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Signed-off-by: Borislav Petkov <bp@suse.de>
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(cherry picked from commit 15cc3ae001873845b5d842e212478a6570c7d938)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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drivers/edac/sb_edac.c | 9 ++++++++-
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1 file changed, 8 insertions(+), 1 deletion(-)
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diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
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index 80d860cb0746..7a3b201d51df 100644
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--- a/drivers/edac/sb_edac.c
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+++ b/drivers/edac/sb_edac.c
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@@ -455,6 +455,7 @@ static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
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static const struct pci_id_descr pci_dev_descr_ibridge[] = {
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/* Processor Home Agent */
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0, IMC0) },
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+ { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1, IMC1) },
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/* Memory controller */
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0, IMC0) },
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@@ -465,7 +466,6 @@ static const struct pci_id_descr pci_dev_descr_ibridge[] = {
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0, IMC0) },
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/* Optional, mode 2HA */
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- { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1, IMC1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1, IMC1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1, IMC1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1, IMC1) },
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@@ -2260,6 +2260,13 @@ static int sbridge_get_onedevice(struct pci_dev **prev,
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next_imc:
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sbridge_dev = get_sbridge_dev(bus, dev_descr->dom, multi_bus, sbridge_dev);
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if (!sbridge_dev) {
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+ /* If the HA1 wasn't found, don't create EDAC second memory controller */
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+ if (dev_descr->dom == IMC1 && devno != 1) {
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+ edac_dbg(0, "Skip IMC1: %04x:%04x (since HA1 was absent)\n",
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+ PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
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+ pci_dev_put(pdev);
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+ return 0;
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+ }
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if (dev_descr->dom == SOCK)
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goto out_imc;
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--
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2.14.2
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@ -0,0 +1,37 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: "Gustavo A. R. Silva" <garsilva@embeddedor.com>
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Date: Mon, 16 Oct 2017 12:40:29 -0500
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Subject: [PATCH] EDAC, sb_edac: Fix missing break in switch
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Add missing break statement in order to prevent the code from falling
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through.
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Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
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Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
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Cc: linux-edac <linux-edac@vger.kernel.org>
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Link: http://lkml.kernel.org/r/20171016174029.GA19757@embeddedor.com
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Signed-off-by: Borislav Petkov <bp@suse.de>
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(cherry picked from commit a8e9b186f153a44690ad0363a56716e7077ad28c)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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drivers/edac/sb_edac.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
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index 7a3b201d51df..fb0264ef83a3 100644
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--- a/drivers/edac/sb_edac.c
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+++ b/drivers/edac/sb_edac.c
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@@ -2467,6 +2467,7 @@ static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
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case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
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case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA:
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pvt->pci_ta = pdev;
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+ break;
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case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
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case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS:
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pvt->pci_ras = pdev;
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--
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2.14.2
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