84 lines
2.5 KiB
Diff
84 lines
2.5 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Tom Lendacky <thomas.lendacky@amd.com>
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Date: Wed, 20 Dec 2017 10:55:47 +0000
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Subject: [PATCH] x86/svm: Set IBRS value on VM entry and exit
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5753
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CVE-2017-5715
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Set/restore the guests IBRS value on VM entry. On VM exit back to the
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kernel save the guest IBRS value and then set IBRS to 1.
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 72f71e6826fac9a656c3994fb6f979cd65a14c64)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/kvm/svm.c | 17 +++++++++++++++++
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1 file changed, 17 insertions(+)
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diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
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index 94adf6becc2e..a1b19e810c49 100644
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--- a/arch/x86/kvm/svm.c
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+++ b/arch/x86/kvm/svm.c
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@@ -175,6 +175,8 @@ struct vcpu_svm {
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u64 next_rip;
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+ u64 spec_ctrl;
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+
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u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
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struct {
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u16 fs;
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@@ -3547,6 +3549,9 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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case MSR_VM_CR:
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msr_info->data = svm->nested.vm_cr_msr;
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break;
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+ case MSR_IA32_SPEC_CTRL:
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+ msr_info->data = svm->spec_ctrl;
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+ break;
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case MSR_IA32_UCODE_REV:
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msr_info->data = 0x01000065;
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break;
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@@ -3702,6 +3707,9 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
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case MSR_VM_IGNNE:
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vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
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break;
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+ case MSR_IA32_SPEC_CTRL:
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+ svm->spec_ctrl = data;
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+ break;
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case MSR_IA32_APICBASE:
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if (kvm_vcpu_apicv_active(vcpu))
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avic_update_vapic_bar(to_svm(vcpu), data);
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@@ -4883,6 +4891,9 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu)
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local_irq_enable();
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+ if (ibrs_inuse && (svm->spec_ctrl != FEATURE_ENABLE_IBRS))
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+ wrmsrl(MSR_IA32_SPEC_CTRL, svm->spec_ctrl);
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+
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asm volatile (
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"push %%" _ASM_BP "; \n\t"
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"mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
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@@ -4975,6 +4986,12 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu)
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#endif
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);
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+ if (ibrs_inuse) {
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+ rdmsrl(MSR_IA32_SPEC_CTRL, svm->spec_ctrl);
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+ if (svm->spec_ctrl != FEATURE_ENABLE_IBRS)
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+ wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
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+ }
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+
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#ifdef CONFIG_X86_64
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wrmsrl(MSR_GS_BASE, svm->host.gs_base);
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#else
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--
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2.14.2
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