94 lines
3.3 KiB
Diff
94 lines
3.3 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Elena Reshetova <elena.reshetova@intel.com>
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Date: Mon, 4 Sep 2017 13:11:45 +0300
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Subject: [PATCH] x86, bpf, jit: prevent speculative execution when JIT is
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enabled
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5753
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CVE-2017-5715
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When constant blinding is enabled (bpf_jit_harden = 1), this adds
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a generic memory barrier (lfence for intel, mfence for AMD) before
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emitting x86 jitted code for the BPF_ALU(64)_OR_X and BPF_ALU_LHS_X
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(for BPF_REG_AX register) eBPF instructions. This is needed in order
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to prevent speculative execution on out of bounds BPF_MAP array
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indexes when JIT is enabled. This way an arbitary kernel memory is
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not exposed through side-channel attacks.
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For more details, please see this Google Project Zero report: tbd
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Signed-off-by: Elena Reshetova <elena.reshetova@intel.com>
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Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com>
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit cf9676859a05d0d784067072e8121e63888bacc7)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/net/bpf_jit_comp.c | 33 ++++++++++++++++++++++++++++++++-
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1 file changed, 32 insertions(+), 1 deletion(-)
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diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c
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index 4d50ced94686..879dbfefb66d 100644
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--- a/arch/x86/net/bpf_jit_comp.c
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+++ b/arch/x86/net/bpf_jit_comp.c
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@@ -107,6 +107,27 @@ static void bpf_flush_icache(void *start, void *end)
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set_fs(old_fs);
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}
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+static void emit_memory_barrier(u8 **pprog)
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+{
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+ u8 *prog = *pprog;
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+ int cnt = 0;
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+
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+ if (bpf_jit_blinding_enabled()) {
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+ if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
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+ /* x86 LFENCE opcode 0F AE E8 */
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+ EMIT3(0x0f, 0xae, 0xe8);
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+ else if (boot_cpu_has(X86_FEATURE_MFENCE_RDTSC))
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+ /* AMD MFENCE opcode 0F AE F0 */
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+ EMIT3(0x0f, 0xae, 0xf0);
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+ else
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+ /* we should never end up here,
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+ * but if we do, better not to emit anything*/
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+ return;
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+ }
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+ *pprog = prog;
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+ return;
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+}
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+
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#define CHOOSE_LOAD_FUNC(K, func) \
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((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset)
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@@ -399,7 +420,7 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image,
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case BPF_ADD: b2 = 0x01; break;
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case BPF_SUB: b2 = 0x29; break;
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case BPF_AND: b2 = 0x21; break;
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- case BPF_OR: b2 = 0x09; break;
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+ case BPF_OR: b2 = 0x09; emit_memory_barrier(&prog); break;
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case BPF_XOR: b2 = 0x31; break;
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}
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if (BPF_CLASS(insn->code) == BPF_ALU64)
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@@ -646,6 +667,16 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image,
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case BPF_ALU64 | BPF_RSH | BPF_X:
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case BPF_ALU64 | BPF_ARSH | BPF_X:
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+ /* If blinding is enabled, each
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+ * BPF_LD | BPF_IMM | BPF_DW instruction
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+ * is converted to 4 eBPF instructions with
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+ * BPF_ALU64_IMM(BPF_LSH, BPF_REG_AX, 32)
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+ * always present(number 3). Detect such cases
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+ * and insert memory barriers. */
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+ if ((BPF_CLASS(insn->code) == BPF_ALU64)
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+ && (BPF_OP(insn->code) == BPF_LSH)
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+ && (src_reg == BPF_REG_AX))
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+ emit_memory_barrier(&prog);
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/* check for bad case when dst_reg == rcx */
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if (dst_reg == BPF_REG_4) {
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/* mov r11, dst_reg */
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--
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2.14.2
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