84 lines
3 KiB
Diff
84 lines
3 KiB
Diff
From 78cddd6de764caacd120df44fc5cb6939e684628 Mon Sep 17 00:00:00 2001
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From: Alicja Michalska <ahplka19@gmail.com>
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Date: Sun, 26 Nov 2023 18:24:44 +0100
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Subject: [PATCH] arm64: dts: mediatek: mt8183: Add video encoder/decoder
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Clock names should be set correctly according to documentation in
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Linux's dt-bindings, although they differ from ChromeOS.
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This should enable hardware video encoders and decoders to work.
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Signed-off-by: Alicja Michalska <ahplka19@gmail.com>
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---
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arch/arm64/boot/dts/mediatek/mt8183.dtsi | 48 ++++++++++++++++++++++++
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1 file changed, 48 insertions(+)
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diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
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index 6caf5a619379..f80e0378a0d2 100644
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--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
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@@ -2121,6 +2121,35 @@ vdecsys: syscon@16000000 {
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#clock-cells = <1>;
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};
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+ vcodec_dec: vcodec@16000000 {
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+ compatible = "mediatek,mt8183-vcodec-dec";
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+ reg = <0 0x16000000 0 0x1000>, /* VDEC_SYS */
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+ <0 0x16020000 0 0x1000>, /* VDEC_MISC */
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+ <0 0x16021000 0 0x800>, /* VDEC_VLD */
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+ <0 0x16021800 0 0x800>, /* VDEC_TOP */
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+ <0 0x16022000 0 0x1000>, /* VDEC_MC */
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+ <0 0x16023000 0 0x1000>, /* VDEC_AVCVLD */
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+ <0 0x16024000 0 0x1000>, /* VDEC_AVCMV */
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+ <0 0x16025000 0 0x1000>, /* VDEC_PP */
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+ <0 0x16026800 0 0x800>, /* VP8_VD */
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+ <0 0x16027000 0 0x800>, /* VP6_VD */
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+ <0 0x16027800 0 0x800>, /* VP8_VL */
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+ <0 0x16028400 0 0x400>; /* VP9_VD */
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+ interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_LOW>;
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+ mediatek,larb = <&larb1>;
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+ iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
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+ <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
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+ <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
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+ <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
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+ <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
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+ <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
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+ <&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>;
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+ mediatek,scp = <&scp>;
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+ power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
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+ clocks = <&vdecsys CLK_VDEC_VDEC>;
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+ clock-names = "vdec";
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+ };
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+
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larb1: larb@16010000 {
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compatible = "mediatek,mt8183-smi-larb";
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reg = <0 0x16010000 0 0x1000>;
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@@ -2157,6 +2186,25 @@ venc_jpg: venc_jpg@17030000 {
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clock-names = "jpgenc";
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};
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+ vcodec_enc: vcodec@17020000 {
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+ compatible = "mediatek,mt8183-vcodec-enc";
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+ reg = <0 0x17020000 0 0x1000>,
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+ <0 0x17000000 0 0x1000>; /* Dummy?! */
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+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_LOW>;
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+ mediatek,larb = <&larb4>;
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+ iommus = <&iommu M4U_PORT_VENC_REC>,
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+ <&iommu M4U_PORT_VENC_BSDMA>,
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+ <&iommu M4U_PORT_VENC_RD_COMV>,
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+ <&iommu M4U_PORT_VENC_CUR_LUMA>,
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+ <&iommu M4U_PORT_VENC_CUR_CHROMA>,
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+ <&iommu M4U_PORT_VENC_REF_LUMA>,
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+ <&iommu M4U_PORT_VENC_REF_CHROMA>;
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+ mediatek,scp = <&scp>;
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+ power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
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+ clocks = <&vencsys CLK_VENC_VENC>;
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+ clock-names = "venc";
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+ };
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+
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ipu_conn: syscon@19000000 {
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compatible = "mediatek,mt8183-ipu_conn", "syscon";
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reg = <0 0x19000000 0 0x1000>;
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--
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2.43.0
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