63e2807916
- switch sources to official repo https://source.denx.de/u-boot - use tag v2021.07 - extract patches from pine64-org - enable DMA transfers from eMMC and mSD (u-boot from Megi) [ci:skip-build] already built successfully in CI
334 lines
8 KiB
Diff
334 lines
8 KiB
Diff
From 10aa9515a2b13ad865c1c134266fcfc7c4fa90ad Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Thu, 7 May 2020 18:50:28 -0500
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Subject: [PATCH 09/29] sunxi: DT: H5: update device tree files
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Import updated device trees from Linux v5.9.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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.../dts/sun50i-h5-bananapi-m2-plus-v1.2.dts | 1 +
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arch/arm/dts/sun50i-h5-cpu-opp.dtsi | 79 +++++++++++++++++++
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.../arm/dts/sun50i-h5-libretech-all-h3-cc.dts | 1 +
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arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 21 +++++
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.../arm/dts/sun50i-h5-orangepi-zero-plus2.dts | 38 +++++++++
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arch/arm/dts/sun50i-h5.dtsi | 41 +++++++++-
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6 files changed, 179 insertions(+), 2 deletions(-)
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create mode 100644 arch/arm/dts/sun50i-h5-cpu-opp.dtsi
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diff --git a/arch/arm/dts/sun50i-h5-bananapi-m2-plus-v1.2.dts b/arch/arm/dts/sun50i-h5-bananapi-m2-plus-v1.2.dts
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index 2e2b14c0ae..8857a37915 100644
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--- a/arch/arm/dts/sun50i-h5-bananapi-m2-plus-v1.2.dts
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+++ b/arch/arm/dts/sun50i-h5-bananapi-m2-plus-v1.2.dts
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@@ -3,6 +3,7 @@
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/dts-v1/;
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#include "sun50i-h5.dtsi"
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+#include "sun50i-h5-cpu-opp.dtsi"
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#include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi>
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/ {
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diff --git a/arch/arm/dts/sun50i-h5-cpu-opp.dtsi b/arch/arm/dts/sun50i-h5-cpu-opp.dtsi
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new file mode 100644
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index 0000000000..b265720195
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--- /dev/null
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+++ b/arch/arm/dts/sun50i-h5-cpu-opp.dtsi
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@@ -0,0 +1,79 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
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+
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+/ {
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+ cpu_opp_table: cpu-opp-table {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-408000000 {
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+ opp-hz = /bits/ 64 <408000000>;
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+ opp-microvolt = <1000000 1000000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-648000000 {
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+ opp-hz = /bits/ 64 <648000000>;
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+ opp-microvolt = <1040000 1040000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-816000000 {
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+ opp-hz = /bits/ 64 <816000000>;
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+ opp-microvolt = <1080000 1080000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-912000000 {
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+ opp-hz = /bits/ 64 <912000000>;
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+ opp-microvolt = <1120000 1120000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-960000000 {
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+ opp-hz = /bits/ 64 <960000000>;
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+ opp-microvolt = <1160000 1160000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1008000000 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt = <1200000 1200000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1056000000 {
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+ opp-hz = /bits/ 64 <1056000000>;
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+ opp-microvolt = <1240000 1240000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1104000000 {
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+ opp-hz = /bits/ 64 <1104000000>;
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+ opp-microvolt = <1260000 1260000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1152000000 {
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+ opp-hz = /bits/ 64 <1152000000>;
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+ opp-microvolt = <1300000 1300000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+ };
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+};
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+
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+&cpu0 {
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+ operating-points-v2 = <&cpu_opp_table>;
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+};
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+
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+&cpu1 {
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+ operating-points-v2 = <&cpu_opp_table>;
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+};
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+
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+&cpu2 {
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+ operating-points-v2 = <&cpu_opp_table>;
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+};
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+
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+&cpu3 {
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+ operating-points-v2 = <&cpu_opp_table>;
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+};
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diff --git a/arch/arm/dts/sun50i-h5-libretech-all-h3-cc.dts b/arch/arm/dts/sun50i-h5-libretech-all-h3-cc.dts
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index a91806618e..016da3ec32 100644
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--- a/arch/arm/dts/sun50i-h5-libretech-all-h3-cc.dts
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+++ b/arch/arm/dts/sun50i-h5-libretech-all-h3-cc.dts
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@@ -4,6 +4,7 @@
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/dts-v1/;
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#include "sun50i-h5.dtsi"
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+#include "sun50i-h5-cpu-opp.dtsi"
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#include <sunxi-libretech-all-h3-cc.dtsi>
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/ {
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diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
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index 70b5f09984..7d7aad18f0 100644
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--- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
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+++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
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@@ -61,6 +61,7 @@
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label = "sw4";
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linux,code = <BTN_0>;
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gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
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+ wakeup-source;
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};
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};
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@@ -93,6 +94,10 @@
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status = "okay";
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};
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+&cpu0 {
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+ cpu-supply = <®_vdd_cpux>;
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+};
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+
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&de {
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status = "okay";
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};
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@@ -168,6 +173,22 @@
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status = "okay";
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};
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+&r_i2c {
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+ status = "okay";
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+
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+ reg_vdd_cpux: regulator@65 {
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+ compatible = "silergy,sy8106a";
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+ reg = <0x65>;
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+ regulator-name = "vdd-cpux";
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+ silergy,fixed-microvolt = <1100000>;
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+ regulator-min-microvolt = <1000000>;
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+ regulator-max-microvolt = <1400000>;
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+ regulator-ramp-delay = <200>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+};
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+
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&spi0 {
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status = "okay";
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diff --git a/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts
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index c95a685413..de19e68eb8 100644
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--- a/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts
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+++ b/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts
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@@ -30,6 +30,21 @@
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};
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};
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+ leds {
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+ compatible = "gpio-leds";
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+
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+ pwr {
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+ label = "orangepi:green:pwr";
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+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
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+ default-state = "on";
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+ };
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+
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+ status {
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+ label = "orangepi:red:status";
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+ gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
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+ };
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+ };
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+
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reg_vcc3v3: vcc3v3 {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3";
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@@ -48,6 +63,10 @@
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status = "okay";
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};
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+&ehci0 {
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+ status = "okay";
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+};
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+
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&hdmi {
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status = "okay";
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};
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@@ -92,6 +111,10 @@
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status = "okay";
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};
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+&ohci0 {
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+ status = "okay";
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+};
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+
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pa_pins>;
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@@ -103,3 +126,18 @@
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pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
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status = "okay";
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};
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+
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+&usb_otg {
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+ /*
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+ * According to schematics CN1 MicroUSB port can be used to take
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+ * external 5V to power up the board VBUS. On the contrary CN1 MicroUSB
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+ * port cannot provide power externally even if the board is powered
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+ * via GPIO pins. It thus makes sense to force peripheral mode.
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+ */
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+ dr_mode = "peripheral";
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+ status = "okay";
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+};
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+
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+&usbphy {
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+ status = "okay";
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+};
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diff --git a/arch/arm/dts/sun50i-h5.dtsi b/arch/arm/dts/sun50i-h5.dtsi
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index 3a1c8b2efd..9c73c4e4c3 100644
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--- a/arch/arm/dts/sun50i-h5.dtsi
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+++ b/arch/arm/dts/sun50i-h5.dtsi
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@@ -3,6 +3,8 @@
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#include <sunxi-h3-h5.dtsi>
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+#include <dt-bindings/thermal/thermal.h>
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+
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/ {
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cpus {
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#address-cells = <1>;
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@@ -13,6 +15,9 @@
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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+ clocks = <&ccu CLK_CPUX>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ #cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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@@ -20,6 +25,9 @@
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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+ clocks = <&ccu CLK_CPUX>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ #cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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@@ -27,6 +35,9 @@
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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+ clocks = <&ccu CLK_CPUX>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ #cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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@@ -34,12 +45,14 @@
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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+ clocks = <&ccu CLK_CPUX>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ #cooling-cells = <2>;
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};
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};
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pmu {
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- compatible = "arm,cortex-a53-pmu",
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- "arm,armv8-pmuv3";
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+ compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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@@ -166,6 +179,30 @@
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&ths 0>;
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+
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+ trips {
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+ cpu_hot_trip: cpu-hot {
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+ temperature = <80000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+
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+ cpu_very_hot_trip: cpu-very-hot {
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+ temperature = <100000>;
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+ hysteresis = <0>;
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+ type = "critical";
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+ };
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+ };
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+
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+ cooling-maps {
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+ cpu-hot-limit {
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+ trip = <&cpu_hot_trip>;
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+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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};
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gpu_thermal {
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--
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2.31.1
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