51 lines
1.5 KiB
Diff
51 lines
1.5 KiB
Diff
From 8f096d8846f8ca59060d4f4427568a343e4b4a89 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
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Date: Sun, 4 Sep 2022 17:20:43 +0200
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Subject: [PATCH] DONOTMERGE: Enable AArch64 system timer properly
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With this, an initramfs can be reached.
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Long-term, this will be moved someplace such as U-Boot.
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---
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drivers/clk/mmp/clk-of-pxa1908.c | 18 ++++++++++++++++++
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1 file changed, 18 insertions(+)
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diff --git a/drivers/clk/mmp/clk-of-pxa1908.c b/drivers/clk/mmp/clk-of-pxa1908.c
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index 753dd031b147..4c9580f9efa1 100644
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--- a/drivers/clk/mmp/clk-of-pxa1908.c
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+++ b/drivers/clk/mmp/clk-of-pxa1908.c
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@@ -31,6 +31,7 @@
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#define APBC_TWSI1 0x60
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#define APBC_THERMAL 0x6c
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#define APBC_TWSI3 0x70
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+#define APBC_COUNTER_CLK_SEL 0x64
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#define APBCP_UART2 0x1c
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#define APBCP_TWSI2 0x28
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@@ -261,6 +262,23 @@ static void __init pxa1908_apbc_clk_init(struct device_node *np)
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mmp_clk_init(np, &pxa_unit->unit, APBC_NR_CLKS);
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pxa1908_apb_periph_clk_init(pxa_unit);
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+
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+ /* Assign a 26MHz clock to the ARM architected timer. */
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+ int tmp = readl(pxa_unit->apbc_base + APBC_COUNTER_CLK_SEL);
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+ if ((tmp >> 16) == 0x319) {
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+ writel(tmp | 1, pxa_unit->apbc_base + APBC_COUNTER_CLK_SEL);
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+ }
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+
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+ /* Enable the ARM architected timer. */
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+ void __iomem *cnt_base = ioremap(0xd4101000, 0x1000);
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+ if (!cnt_base)
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+ pr_err("failed to map cnt register\n");
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+ else {
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+ writel(BIT(0) | BIT(1), cnt_base);
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+ iounmap(cnt_base);
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+ }
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+
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+ pr_notice("apbc ready\n");
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}
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CLK_OF_DECLARE(pxa1908_apbc, "marvell,pxa1908-apbc", pxa1908_apbc_clk_init);
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--
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2.42.0
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