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pmaports/device/testing/linux-samsung-i927/0050-ARM-dts-tegra20-glide-Add-EMC-memory-timings.patch
Oliver Smith 64035ac463
device/*: move to device/testing/* (!1063) 
Prepare for better device categorization by moving everything to testing
subdir first.

[skip-ci]: chicken-egg problem: passing pmaports CI depends on pmbootstrap MR
				depends on this MR

Related: postmarketos#16
2020-03-14 08:35:32 +01:00

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From b302defd02e5db34787d577adfbe56c1323385ee Mon Sep 17 00:00:00 2001
From: Sergey Larin <cerg2010cerg2010@mail.ru>
Date: Thu, 20 Jun 2019 20:29:17 +0300
Subject: [PATCH] ARM: dts: tegra20-glide: Add EMC memory timings
There's one memory module inside, so the timings are not versioned.
Extracted from downstream with regex and VIM magic.
Signed-off-by: Sergey Larin <cerg2010cerg2010@mail.ru>
---
arch/arm/boot/dts/tegra20-glide.dts | 272 ++++++++++++++++++++++++++++
1 file changed, 272 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-glide.dts b/arch/arm/boot/dts/tegra20-glide.dts
index 7d3b6066ac0c..0c6a903ef0c7 100644
--- a/arch/arm/boot/dts/tegra20-glide.dts
+++ b/arch/arm/boot/dts/tegra20-glide.dts
@@ -1248,6 +1248,278 @@
nvidia,lp0-vec = <0x1819E000 8192>;
};
+ memory-controller@7000f400 {
+ emc-table@25000 {
+ compatible = "nvidia,tegra20-emc-table";
+ reg = <25000>;
+ clock-frequency = < 25000 >; /* SDRAM frquency */
+ nvidia,emc-registers = <
+ 0x00000002 /* RC */
+ 0x00000006 /* RFC */
+ 0x00000003 /* RAS */
+ 0x00000003 /* RP */
+ 0x00000006 /* R2W */
+ 0x00000004 /* W2R */
+ 0x00000002 /* R2P */
+ 0x0000000b /* W2P */
+ 0x00000003 /* RD_RCD */
+ 0x00000003 /* WR_RCD */
+ 0x00000002 /* RRD */
+ 0x00000002 /* REXT */
+ 0x00000003 /* WDV */
+ 0x00000005 /* QUSE */
+ 0x00000004 /* QRST */
+ 0x00000008 /* QSAFE */
+ 0x0000000c /* RDV */
+ 0x0000004d /* REFRESH */
+ 0x00000000 /* BURST_REFRESH_NUM */
+ 0x00000003 /* PDEX2WR */
+ 0x00000003 /* PDEX2RD */
+ 0x00000003 /* PCHG2PDEN */
+ 0x00000008 /* ACT2PDEN */
+ 0x00000001 /* AR2PDEN */
+ 0x0000000b /* RW2PDEN */
+ 0x00000004 /* TXSR */
+ 0x00000003 /* TCKE */
+ 0x00000008 /* TFAW */
+ 0x00000004 /* TRPAB */
+ 0x00000008 /* TCLKSTABLE */
+ 0x00000002 /* TCLKSTOP */
+ 0x00000068 /* TREFBW */
+ 0x00000000 /* QUSE_EXTRA */
+ 0x00000003 /* FBIO_CFG6 */
+ 0x00000000 /* ODT_WRITE */
+ 0x00000000 /* ODT_READ */
+ 0x00000082 /* FBIO_CFG5 */
+ 0xa06a04ae /* CFG_DIG_DLL */
+ 0x00080000 /* DLL_XFORM_DQS */
+ 0x00000000 /* DLL_XFORM_QUSE */
+ 0x00000000 /* ZCAL_REF_CNT */
+ 0x00000003 /* ZCAL_WAIT_CNT */
+ 0x00000000 /* AUTO_CAL_INTERVAL */
+ 0x00000000 /* CFG_CLKTRIM_0 */
+ 0x00000000 /* CFG_CLKTRIM_1 */
+ 0x00000000 /* CFG_CLKTRIM_2 */
+ >;
+ };
+
+ emc-table@50000 {
+ compatible = "nvidia,tegra20-emc-table";
+ reg = <50000>;
+ clock-frequency = < 50000 >; /* SDRAM frquency */
+ nvidia,emc-registers = <
+ 0x00000003 /* RC */
+ 0x00000007 /* RFC */
+ 0x00000003 /* RAS */
+ 0x00000003 /* RP */
+ 0x00000006 /* R2W */
+ 0x00000004 /* W2R */
+ 0x00000002 /* R2P */
+ 0x0000000b /* W2P */
+ 0x00000003 /* RD_RCD */
+ 0x00000003 /* WR_RCD */
+ 0x00000002 /* RRD */
+ 0x00000002 /* REXT */
+ 0x00000003 /* WDV */
+ 0x00000006 /* QUSE */
+ 0x00000004 /* QRST */
+ 0x00000008 /* QSAFE */
+ 0x0000000c /* RDV */
+ 0x0000009f /* REFRESH */
+ 0x00000000 /* BURST_REFRESH_NUM */
+ 0x00000003 /* PDEX2WR */
+ 0x00000003 /* PDEX2RD */
+ 0x00000003 /* PCHG2PDEN */
+ 0x00000008 /* ACT2PDEN */
+ 0x00000001 /* AR2PDEN */
+ 0x0000000b /* RW2PDEN */
+ 0x00000007 /* TXSR */
+ 0x00000003 /* TCKE */
+ 0x00000008 /* TFAW */
+ 0x00000004 /* TRPAB */
+ 0x00000008 /* TCLKSTABLE */
+ 0x00000002 /* TCLKSTOP */
+ 0x000000d0 /* TREFBW */
+ 0x00000000 /* QUSE_EXTRA */
+ 0x00000000 /* FBIO_CFG6 */
+ 0x00000000 /* ODT_WRITE */
+ 0x00000000 /* ODT_READ */
+ 0x00000082 /* FBIO_CFG5 */
+ 0xa06a04ae /* CFG_DIG_DLL */
+ 0x00080000 /* DLL_XFORM_DQS */
+ 0x00000000 /* DLL_XFORM_QUSE */
+ 0x00000000 /* ZCAL_REF_CNT */
+ 0x00000005 /* ZCAL_WAIT_CNT */
+ 0x00000000 /* AUTO_CAL_INTERVAL */
+ 0x00000000 /* CFG_CLKTRIM_0 */
+ 0x00000000 /* CFG_CLKTRIM_1 */
+ 0x00000000 /* CFG_CLKTRIM_2 */
+ >;
+ };
+
+ emc-table@75000 {
+ compatible = "nvidia,tegra20-emc-table";
+ reg = <75000>;
+ clock-frequency = < 75000 >; /* SDRAM frquency */
+ nvidia,emc-registers = <
+ 0x00000005 /* RC */
+ 0x0000000a /* RFC */
+ 0x00000004 /* RAS */
+ 0x00000003 /* RP */
+ 0x00000006 /* R2W */
+ 0x00000004 /* W2R */
+ 0x00000002 /* R2P */
+ 0x0000000b /* W2P */
+ 0x00000003 /* RD_RCD */
+ 0x00000003 /* WR_RCD */
+ 0x00000002 /* RRD */
+ 0x00000002 /* REXT */
+ 0x00000003 /* WDV */
+ 0x00000006 /* QUSE */
+ 0x00000004 /* QRST */
+ 0x00000008 /* QSAFE */
+ 0x0000000c /* RDV */
+ 0x000000ff /* REFRESH */
+ 0x00000000 /* BURST_REFRESH_NUM */
+ 0x00000003 /* PDEX2WR */
+ 0x00000003 /* PDEX2RD */
+ 0x00000003 /* PCHG2PDEN */
+ 0x00000008 /* ACT2PDEN */
+ 0x00000001 /* AR2PDEN */
+ 0x0000000b /* RW2PDEN */
+ 0x0000000b /* TXSR */
+ 0x00000003 /* TCKE */
+ 0x00000008 /* TFAW */
+ 0x00000004 /* TRPAB */
+ 0x00000008 /* TCLKSTABLE */
+ 0x00000002 /* TCLKSTOP */
+ 0x00000138 /* TREFBW */
+ 0x00000000 /* QUSE_EXTRA */
+ 0x00000000 /* FBIO_CFG6 */
+ 0x00000000 /* ODT_WRITE */
+ 0x00000000 /* ODT_READ */
+ 0x00000082 /* FBIO_CFG5 */
+ 0xa06a04ae /* CFG_DIG_DLL */
+ 0x00080000 /* DLL_XFORM_DQS */
+ 0x00000000 /* DLL_XFORM_QUSE */
+ 0x00000000 /* ZCAL_REF_CNT */
+ 0x00000007 /* ZCAL_WAIT_CNT */
+ 0x00000000 /* AUTO_CAL_INTERVAL */
+ 0x00000000 /* CFG_CLKTRIM_0 */
+ 0x00000000 /* CFG_CLKTRIM_1 */
+ 0x00000000 /* CFG_CLKTRIM_2 */
+ >;
+ };
+
+ emc-table@150000 {
+ compatible = "nvidia,tegra20-emc-table";
+ reg = <150000>;
+ clock-frequency = < 150000 >; /* SDRAM frquency */
+ nvidia,emc-registers = <
+ 0x00000009 /* RC */
+ 0x00000014 /* RFC */
+ 0x00000007 /* RAS */
+ 0x00000003 /* RP */
+ 0x00000006 /* R2W */
+ 0x00000004 /* W2R */
+ 0x00000002 /* R2P */
+ 0x0000000b /* W2P */
+ 0x00000003 /* RD_RCD */
+ 0x00000003 /* WR_RCD */
+ 0x00000002 /* RRD */
+ 0x00000002 /* REXT */
+ 0x00000003 /* WDV */
+ 0x00000006 /* QUSE */
+ 0x00000004 /* QRST */
+ 0x00000008 /* QSAFE */
+ 0x0000000c /* RDV */
+ 0x0000021f /* REFRESH */
+ 0x00000000 /* BURST_REFRESH_NUM */
+ 0x00000003 /* PDEX2WR */
+ 0x00000003 /* PDEX2RD */
+ 0x00000003 /* PCHG2PDEN */
+ 0x00000008 /* ACT2PDEN */
+ 0x00000001 /* AR2PDEN */
+ 0x0000000b /* RW2PDEN */
+ 0x00000015 /* TXSR */
+ 0x00000003 /* TCKE */
+ 0x00000008 /* TFAW */
+ 0x00000004 /* TRPAB */
+ 0x00000008 /* TCLKSTABLE */
+ 0x00000002 /* TCLKSTOP */
+ 0x00000270 /* TREFBW */
+ 0x00000000 /* QUSE_EXTRA */
+ 0x00000001 /* FBIO_CFG6 */
+ 0x00000000 /* ODT_WRITE */
+ 0x00000000 /* ODT_READ */
+ 0x00000082 /* FBIO_CFG5 */
+ 0xa04c04ae /* CFG_DIG_DLL */
+ 0x007dea10 /* DLL_XFORM_DQS */
+ 0x00000000 /* DLL_XFORM_QUSE */
+ 0x00000000 /* ZCAL_REF_CNT */
+ 0x0000000e /* ZCAL_WAIT_CNT */
+ 0x00000000 /* AUTO_CAL_INTERVAL */
+ 0x00000000 /* CFG_CLKTRIM_0 */
+ 0x00000000 /* CFG_CLKTRIM_1 */
+ 0x00000000 /* CFG_CLKTRIM_2 */
+ >;
+ };
+
+ emc-table@300000 {
+ compatible = "nvidia,tegra20-emc-table";
+ reg = <300000>;
+ clock-frequency = < 300000 >; /* SDRAM frquency */
+ nvidia,emc-registers = <
+ 0x00000012 /* RC */
+ 0x00000027 /* RFC */
+ 0x0000000d /* RAS */
+ 0x00000006 /* RP */
+ 0x00000007 /* R2W */
+ 0x00000005 /* W2R */
+ 0x00000003 /* R2P */
+ 0x0000000b /* W2P */
+ 0x00000006 /* RD_RCD */
+ 0x00000006 /* WR_RCD */
+ 0x00000003 /* RRD */
+ 0x00000003 /* REXT */
+ 0x00000003 /* WDV */
+ 0x00000007 /* QUSE */
+ 0x00000004 /* QRST */
+ 0x00000009 /* QSAFE */
+ 0x0000000d /* RDV */
+ 0x0000045f /* REFRESH */
+ 0x00000000 /* BURST_REFRESH_NUM */
+ 0x00000004 /* PDEX2WR */
+ 0x00000004 /* PDEX2RD */
+ 0x00000006 /* PCHG2PDEN */
+ 0x00000008 /* ACT2PDEN */
+ 0x00000001 /* AR2PDEN */
+ 0x0000000f /* RW2PDEN */
+ 0x0000002a /* TXSR */
+ 0x00000003 /* TCKE */
+ 0x0000000f /* TFAW */
+ 0x00000007 /* TRPAB */
+ 0x00000007 /* TCLKSTABLE */
+ 0x00000002 /* TCLKSTOP */
+ 0x000004e0 /* TREFBW */
+ 0x00000006 /* QUSE_EXTRA */
+ 0x00000002 /* FBIO_CFG6 */
+ 0x00000000 /* ODT_WRITE */
+ 0x00000000 /* ODT_READ */
+ 0x00000282 /* FBIO_CFG5 */
+ 0xe03c048b /* CFG_DIG_DLL */
+ 0x007e0010 /* DLL_XFORM_DQS */
+ 0x00000000 /* DLL_XFORM_QUSE */
+ 0x00000000 /* ZCAL_REF_CNT */
+ 0x0000001b /* ZCAL_WAIT_CNT */
+ 0x00000000 /* AUTO_CAL_INTERVAL */
+ 0x00000000 /* CFG_CLKTRIM_0 */
+ 0x00000000 /* CFG_CLKTRIM_1 */
+ 0x00000000 /* CFG_CLKTRIM_2 */
+ >;
+ };
+ };
+
usb@c5000000 {
compatible = "nvidia,tegra20-udc";
status = "okay";
--
2.22.0
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