pmaports/cross/gcc-armhf/0035-Fix-ICE-observed-in-PR110280.patch
2023-07-25 22:19:00 +02:00

61 lines
1.8 KiB
Diff

From ef740fff300fd9eb8285fb5611f6205705ee54ec Mon Sep 17 00:00:00 2001
From: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
Date: Fri, 23 Jun 2023 15:27:17 +0530
Subject: [PATCH 35/35] Fix ICE observed in PR110280.
gcc/ChangeLog:
PR tree-optimization/110280
* match.pd (vec_perm_expr(v, v, mask) -> v): Explicitly build vector
using build_vector_from_val with the element of input operand, and
mask's type if operand and mask's types don't match.
gcc/testsuite/ChangeLog:
PR tree-optimization/110280
* gcc.target/aarch64/sve/pr110280.c: New test.
---
gcc/match.pd | 9 ++++++++-
gcc/testsuite/gcc.target/aarch64/sve/pr110280.c | 12 ++++++++++++
2 files changed, 20 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
diff --git a/gcc/match.pd b/gcc/match.pd
index 91182448250..c3bb4fbc0a7 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -8292,7 +8292,14 @@ and,
(simplify
(vec_perm vec_same_elem_p@0 @0 @1)
- @0)
+ (if (types_match (type, TREE_TYPE (@0)))
+ @0
+ (with
+ {
+ tree elem = uniform_vector_p (@0);
+ }
+ (if (elem)
+ { build_vector_from_val (type, elem); }))))
/* Push VEC_PERM earlier if that may help FMA perception (PR101895). */
(simplify
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
new file mode 100644
index 00000000000..d3279f38362
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fdump-tree-optimized" } */
+
+#include "arm_sve.h"
+
+svuint32_t l()
+{
+ _Alignas(16) const unsigned int lanes[4] = {0, 0, 0, 0};
+ return svld1rq_u32(svptrue_b8(), lanes);
+}
+
+/* { dg-final { scan-tree-dump-not "VEC_PERM_EXPR" "optimized" } } */
--
2.41.0