891a4cb5a1
patches added are (not all, just some) fixes and feature enhancements for msm8992 and msm8994 from qcom mainline maintainer tree [1] for v5.18 and v5.19. Changes: * update deviceinfo_dtb_mainline for device-huawei-angler and device-lg-bullhead. * add sdhc1 support for device-huawei-angler [1] https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git Signed-off-by: Petr Vorel <petr.vorel@gmail.com> [ci:skip-build] Already built successfully in CI in MR
96 lines
4.4 KiB
Diff
96 lines
4.4 KiB
Diff
From b79b46ed4e9360f7f960193d871c9d18cf24f1be Mon Sep 17 00:00:00 2001
|
|
From: Konrad Dybcio <konrad.dybcio@somainline.org>
|
|
Date: Sat, 26 Feb 2022 22:41:25 +0100
|
|
Subject: [PATCH 7/8] clk: qcom: smd: Add missing RPM clocks for msm8992/4
|
|
|
|
XO and MSS_CFG were omitted when first adding the clocks for these SoCs.
|
|
Add them, and while at it, move the XO clock to the top of the definition
|
|
list, as ideally everyone should start using it sooner or later..
|
|
|
|
[ cherry-picked from f804360bb3a50decbed6e2761247964dca72c080 ]
|
|
|
|
Fixes: b4297844995f ("clk: qcom: smd: Add support for MSM8992/4 rpm clocks")
|
|
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
|
|
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
Link: https://lore.kernel.org/r/20220226214126.21209-2-konrad.dybcio@somainline.org
|
|
Signed-off-by: Petr Vorel <petr.vorel@gmail.com>
|
|
---
|
|
drivers/clk/qcom/clk-smd-rpm.c | 13 +++++++++++--
|
|
include/linux/soc/qcom/smd-rpm.h | 1 +
|
|
2 files changed, 12 insertions(+), 2 deletions(-)
|
|
|
|
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
|
|
index ea28e45ca371..418f017e933f 100644
|
|
--- a/drivers/clk/qcom/clk-smd-rpm.c
|
|
+++ b/drivers/clk/qcom/clk-smd-rpm.c
|
|
@@ -413,6 +413,7 @@ static const struct clk_ops clk_smd_rpm_branch_ops = {
|
|
.recalc_rate = clk_smd_rpm_recalc_rate,
|
|
};
|
|
|
|
+DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000);
|
|
DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
|
|
DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
|
|
DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
|
|
@@ -604,7 +605,11 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8, 19200000);
|
|
DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
|
|
DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
|
|
|
|
+DEFINE_CLK_SMD_RPM_BRANCH(msm8992, mss_cfg_ahb_clk, mss_cfg_ahb_a_clk,
|
|
+ QCOM_SMD_RPM_MCFG_CLK, 0, 19200000);
|
|
static struct clk_smd_rpm *msm8992_clks[] = {
|
|
+ [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
|
|
+ [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
|
|
[RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
|
|
[RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
|
|
[RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
|
|
@@ -637,6 +642,8 @@ static struct clk_smd_rpm *msm8992_clks[] = {
|
|
[RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
|
|
[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
|
|
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
|
|
+ [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk,
|
|
+ [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk,
|
|
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
|
|
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
|
|
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
|
|
@@ -661,6 +668,8 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
|
|
DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2);
|
|
|
|
static struct clk_smd_rpm *msm8994_clks[] = {
|
|
+ [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
|
|
+ [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
|
|
[RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
|
|
[RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
|
|
[RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
|
|
@@ -693,6 +702,8 @@ static struct clk_smd_rpm *msm8994_clks[] = {
|
|
[RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
|
|
[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
|
|
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
|
|
+ [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk,
|
|
+ [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk,
|
|
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
|
|
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
|
|
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
|
|
@@ -857,8 +868,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
|
|
.num_clks = ARRAY_SIZE(msm8998_clks),
|
|
};
|
|
|
|
-DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
|
|
- 19200000);
|
|
DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000);
|
|
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_a, 3, 19200000);
|
|
|
|
diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h
|
|
index 860dd8cdf9f3..82c9d489833a 100644
|
|
--- a/include/linux/soc/qcom/smd-rpm.h
|
|
+++ b/include/linux/soc/qcom/smd-rpm.h
|
|
@@ -40,6 +40,7 @@ struct qcom_smd_rpm;
|
|
#define QCOM_SMD_RPM_AGGR_CLK 0x72676761
|
|
#define QCOM_SMD_RPM_HWKM_CLK 0x6d6b7768
|
|
#define QCOM_SMD_RPM_PKA_CLK 0x616b70
|
|
+#define QCOM_SMD_RPM_MCFG_CLK 0x6766636d
|
|
|
|
int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
|
|
int state,
|
|
--
|
|
2.35.1
|
|
|