237 lines
6.3 KiB
Diff
237 lines
6.3 KiB
Diff
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
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index f56132b0ae64..2538255ac2c1 100644
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--- a/drivers/devfreq/Kconfig
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+++ b/drivers/devfreq/Kconfig
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@@ -111,6 +111,16 @@ config ARM_IMX8M_DDRC_DEVFREQ
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This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows
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adjusting DRAM frequency.
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+config ARM_MT8183_CCI_DEVFREQ
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+ tristate "MT8183 CCI DEVFREQ Driver"
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+ depends on ARM_MEDIATEK_CPUFREQ
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+ help
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+ This adds a devfreq driver for Cache Coherent Interconnect
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+ of Mediatek MT8183, which is shared the same regulator
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+ with cpu cluster.
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+ It can track buck voltage and update a proper CCI frequency.
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+ Use notification to get regulator status.
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+
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config ARM_TEGRA_DEVFREQ
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tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver"
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depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \
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diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
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index a16333ea7034..991ef7740759 100644
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--- a/drivers/devfreq/Makefile
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+++ b/drivers/devfreq/Makefile
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@@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
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obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
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obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
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obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
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+obj-$(CONFIG_ARM_MT8183_CCI_DEVFREQ) += mt8183-cci-devfreq.o
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obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
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obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
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diff --git a/drivers/devfreq/mt8183-cci-devfreq.c b/drivers/devfreq/mt8183-cci-devfreq.c
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new file mode 100644
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index 000000000000..018543db7bae
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--- /dev/null
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+++ b/drivers/devfreq/mt8183-cci-devfreq.c
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@@ -0,0 +1,198 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (c) 2021 MediaTek Inc.
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+
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+ * Author: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/devfreq.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/platform_device.h>
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+#include <linux/regulator/consumer.h>
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+#include <linux/time.h>
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+
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+#define MAX_VOLT_LIMIT (1150000)
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+
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+struct cci_devfreq {
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+ struct devfreq *devfreq;
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+ struct regulator *cpu_reg;
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+ struct clk *cci_clk;
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+ int old_vproc;
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+ unsigned long old_freq;
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+};
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+
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+static int mtk_cci_set_voltage(struct cci_devfreq *cci_df, int vproc)
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+{
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+ int ret;
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+
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+ ret = regulator_set_voltage(cci_df->cpu_reg, vproc,
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+ MAX_VOLT_LIMIT);
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+ if (!ret)
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+ cci_df->old_vproc = vproc;
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+ return ret;
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+}
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+
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+static int mtk_cci_devfreq_target(struct device *dev, unsigned long *freq,
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+ u32 flags)
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+{
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+ int ret;
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+ struct cci_devfreq *cci_df = dev_get_drvdata(dev);
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+ struct dev_pm_opp *opp;
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+ unsigned long opp_rate, opp_voltage, old_voltage;
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+
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+ if (!cci_df)
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+ return -EINVAL;
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+
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+ if (cci_df->old_freq == *freq)
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+ return 0;
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+
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+ opp_rate = *freq;
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+ opp = devfreq_recommended_opp(dev, &opp_rate, 1);
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+ opp_voltage = dev_pm_opp_get_voltage(opp);
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+ dev_pm_opp_put(opp);
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+
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+ old_voltage = cci_df->old_vproc;
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+ if (old_voltage == 0)
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+ old_voltage = regulator_get_voltage(cci_df->cpu_reg);
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+
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+ // scale up: set voltage first then freq
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+ if (opp_voltage > old_voltage) {
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+ ret = mtk_cci_set_voltage(cci_df, opp_voltage);
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+ if (ret) {
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+ pr_err("cci: failed to scale up voltage\n");
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+ return ret;
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+ }
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+ }
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+
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+ ret = clk_set_rate(cci_df->cci_clk, *freq);
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+ if (ret) {
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+ pr_err("%s: failed cci to set rate: %d\n", __func__,
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+ ret);
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+ mtk_cci_set_voltage(cci_df, old_voltage);
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+ return ret;
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+ }
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+
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+ // scale down: set freq first then voltage
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+ if (opp_voltage < old_voltage) {
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+ ret = mtk_cci_set_voltage(cci_df, opp_voltage);
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+ if (ret) {
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+ pr_err("cci: failed to scale down voltage\n");
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+ clk_set_rate(cci_df->cci_clk, cci_df->old_freq);
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+ return ret;
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+ }
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+ }
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+
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+ cci_df->old_freq = *freq;
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+
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+ return 0;
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+}
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+
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+static struct devfreq_dev_profile cci_devfreq_profile = {
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+ .target = mtk_cci_devfreq_target,
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+};
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+
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+static int mtk_cci_devfreq_probe(struct platform_device *pdev)
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+{
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+ struct device *cci_dev = &pdev->dev;
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+ struct cci_devfreq *cci_df;
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+ struct devfreq_passive_data *passive_data;
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+ int ret;
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+
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+ cci_df = devm_kzalloc(cci_dev, sizeof(*cci_df), GFP_KERNEL);
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+ if (!cci_df)
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+ return -ENOMEM;
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+
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+ cci_df->cci_clk = devm_clk_get(cci_dev, "cci_clock");
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+ ret = PTR_ERR_OR_ZERO(cci_df->cci_clk);
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+ if (ret) {
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+ if (ret != -EPROBE_DEFER)
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+ dev_err(cci_dev, "failed to get clock for CCI: %d\n",
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+ ret);
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+ return ret;
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+ }
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+ cci_df->cpu_reg = devm_regulator_get_optional(cci_dev, "proc");
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+ ret = PTR_ERR_OR_ZERO(cci_df->cpu_reg);
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+ if (ret) {
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+ if (ret != -EPROBE_DEFER)
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+ dev_err(cci_dev, "failed to get regulator for CCI: %d\n",
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+ ret);
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+ return ret;
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+ }
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+ ret = regulator_enable(cci_df->cpu_reg);
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+ if (ret) {
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+ dev_err(cci_dev, "enable buck for cci fail\n");
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+ return ret;
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+ }
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+
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+ ret = dev_pm_opp_of_add_table(cci_dev);
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+ if (ret) {
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+ dev_err(cci_dev, "Fail to get OPP table for CCI: %d\n", ret);
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+ return ret;
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+ }
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+
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+ platform_set_drvdata(pdev, cci_df);
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+
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+ passive_data = devm_kzalloc(cci_dev, sizeof(*passive_data), GFP_KERNEL);
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+ if (!passive_data) {
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+ ret = -ENOMEM;
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+ goto err_opp;
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+ }
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+
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+ passive_data->parent_type = CPUFREQ_PARENT_DEV;
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+
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+ cci_df->devfreq = devm_devfreq_add_device(cci_dev,
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+ &cci_devfreq_profile,
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+ DEVFREQ_GOV_PASSIVE,
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+ passive_data);
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+ if (IS_ERR(cci_df->devfreq)) {
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+ ret = PTR_ERR(cci_df->devfreq);
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+ dev_err(cci_dev, "cannot create cci devfreq device:%d\n", ret);
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+ goto err_opp;
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+ }
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+
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+ return 0;
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+
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+err_opp:
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+ dev_pm_opp_of_remove_table(cci_dev);
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+ return ret;
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+}
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+
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+static int mtk_cci_devfreq_remove(struct platform_device *pdev)
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+{
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+ struct device *cci_dev = &pdev->dev;
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+ struct cci_devfreq *cci_df;
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+ struct notifier_block *opp_nb;
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+
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+ cci_df = platform_get_drvdata(pdev);
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+ opp_nb = &cci_df->opp_nb;
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+
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+ dev_pm_opp_unregister_notifier(cci_dev, opp_nb);
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+ dev_pm_opp_of_remove_table(cci_dev);
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+ regulator_disable(cci_df->cpu_reg);
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+
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+ return 0;
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+}
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+
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+static const __maybe_unused struct of_device_id
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+ mediatek_cci_of_match[] = {
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+ { .compatible = "mediatek,mt8183-cci" },
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+ { },
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+};
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+MODULE_DEVICE_TABLE(of, mediatek_cci_of_match);
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+
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+static struct platform_driver cci_devfreq_driver = {
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+ .probe = mtk_cci_devfreq_probe,
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+ .remove = mtk_cci_devfreq_remove,
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+ .driver = {
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+ .name = "mediatek-cci-devfreq",
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+ .of_match_table = of_match_ptr(mediatek_cci_of_match),
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+ },
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+};
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+
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+module_platform_driver(cci_devfreq_driver);
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+
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+MODULE_DESCRIPTION("Mediatek CCI devfreq driver");
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+MODULE_AUTHOR("Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>");
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+MODULE_LICENSE("GPL v2");
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