63e2807916
- switch sources to official repo https://source.denx.de/u-boot - use tag v2021.07 - extract patches from pine64-org - enable DMA transfers from eMMC and mSD (u-boot from Megi) [ci:skip-build] already built successfully in CI
41 lines
1.4 KiB
Diff
41 lines
1.4 KiB
Diff
From 43e334d01e4ffb3d536bee35d8eeb57a2e0c497f Mon Sep 17 00:00:00 2001
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From: Andre Przywara <andre.przywara@arm.com>
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Date: Thu, 29 Apr 2021 09:31:58 +0100
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Subject: [PATCH 02/29] mmc: sunxi: Fix warnings with CONFIG_PHYS_64BIT
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When enabling PHYS_64BIT on 32-bit platforms, we get two warnings about
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pointer casts in sunxi_mmc.c. Those are related to MMIO addresses, which
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are always below 1GB on all Allwinner SoCs, so there is no problem with
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anything having more than 32 bits.
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Add the proper casts to make it compile cleanly.
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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---
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drivers/mmc/sunxi_mmc.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
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index 87b79fcf5e..869af993d3 100644
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--- a/drivers/mmc/sunxi_mmc.c
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+++ b/drivers/mmc/sunxi_mmc.c
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@@ -631,14 +631,14 @@ static int sunxi_mmc_probe(struct udevice *dev)
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cfg->f_min = 400000;
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cfg->f_max = 52000000;
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- priv->reg = (void *)dev_read_addr(dev);
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+ priv->reg = dev_read_addr_ptr(dev);
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/* We don't have a sunxi clock driver so find the clock address here */
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ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
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1, &args);
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if (ret)
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return ret;
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- ccu_reg = (u32 *)ofnode_get_addr(args.node);
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+ ccu_reg = (u32 *)(uintptr_t)ofnode_get_addr(args.node);
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priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
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priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4;
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--
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2.31.1
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