171 lines
5.1 KiB
Diff
171 lines
5.1 KiB
Diff
From 9495e512486a63d11baa2db46154cff4962f9f67 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
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Date: Fri, 21 Jul 2023 22:37:47 +0200
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Subject: [PATCH] dt-bindings: clock: Add Marvell PXA1908 clock bindings
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Add dt bindings and documentation for the Marvell PXA1908 clock
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controller.
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Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
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---
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.../bindings/clock/marvell,pxa1908.yaml | 48 ++++++++++
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include/dt-bindings/clock/marvell,pxa1908.h | 88 +++++++++++++++++++
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2 files changed, 136 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
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create mode 100644 include/dt-bindings/clock/marvell,pxa1908.h
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diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
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new file mode 100644
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index 000000000000..4e78933232b6
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
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@@ -0,0 +1,48 @@
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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Marvell PXA1908 Clock Controllers
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+
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+maintainers:
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+ - Duje Mihanović <duje.mihanovic@skole.hr>
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+
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+description: |
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+ The PXA1908 clock subsystem generates and supplies clock to various
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+ controllers within the PXA1908 SoC. The PXA1908 contains numerous clock
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+ controller blocks, with the ones currently supported being APBC, APBCP, MPMU
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+ and APMU roughly corresponding to internal buses.
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+
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+ All these clock identifiers could be found in <include/dt-bindings/marvell,pxa1908.h>.
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+
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+properties:
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+ compatible:
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+ enum:
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+ - marvell,pxa1908-apbc
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+ - marvell,pxa1908-apbcp
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+ - marvell,pxa1908-mpmu
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+ - marvell,pxa1908-apmu
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+
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+ reg:
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+ maxItems: 1
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+
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+ '#clock-cells':
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+ const: 1
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+
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+required:
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+ - compatible
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+ - reg
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+ - '#clock-cells'
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+
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+additionalProperties: false
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+
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+examples:
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+ # APMU block:
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+ - |
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+ clock-controller@d4282800 {
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+ compatible = "marvell,pxa1908-apmu";
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+ reg = <0xd4282800 0x400>;
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+ #clock-cells = <1>;
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+ };
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diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindings/clock/marvell,pxa1908.h
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new file mode 100644
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index 000000000000..fb15b0d0cd4c
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--- /dev/null
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+++ b/include/dt-bindings/clock/marvell,pxa1908.h
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@@ -0,0 +1,88 @@
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+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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+#ifndef __DTS_MARVELL_PXA1908_CLOCK_H
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+#define __DTS_MARVELL_PXA1908_CLOCK_H
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+
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+/* plls */
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+#define PXA1908_CLK_CLK32 1
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+#define PXA1908_CLK_VCTCXO 2
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+#define PXA1908_CLK_PLL1_624 3
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+#define PXA1908_CLK_PLL1_416 4
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+#define PXA1908_CLK_PLL1_499 5
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+#define PXA1908_CLK_PLL1_832 6
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+#define PXA1908_CLK_PLL1_1248 7
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+#define PXA1908_CLK_PLL1_D2 8
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+#define PXA1908_CLK_PLL1_D4 9
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+#define PXA1908_CLK_PLL1_D8 10
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+#define PXA1908_CLK_PLL1_D16 11
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+#define PXA1908_CLK_PLL1_D6 12
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+#define PXA1908_CLK_PLL1_D12 13
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+#define PXA1908_CLK_PLL1_D24 14
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+#define PXA1908_CLK_PLL1_D48 15
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+#define PXA1908_CLK_PLL1_D96 16
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+#define PXA1908_CLK_PLL1_D13 17
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+#define PXA1908_CLK_PLL1_32 18
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+#define PXA1908_CLK_PLL1_208 19
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+#define PXA1908_CLK_PLL1_117 20
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+#define PXA1908_CLK_PLL1_416_GATE 21
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+#define PXA1908_CLK_PLL1_624_GATE 22
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+#define PXA1908_CLK_PLL1_832_GATE 23
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+#define PXA1908_CLK_PLL1_1248_GATE 24
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+#define PXA1908_CLK_PLL1_D2_GATE 25
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+#define PXA1908_CLK_PLL1_499_EN 26
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+#define PXA1908_CLK_PLL2VCO 27
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+#define PXA1908_CLK_PLL2 28
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+#define PXA1908_CLK_PLL2P 29
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+#define PXA1908_CLK_PLL2VCODIV3 30
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+#define PXA1908_CLK_PLL3VCO 31
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+#define PXA1908_CLK_PLL3 32
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+#define PXA1908_CLK_PLL3P 33
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+#define PXA1908_CLK_PLL3VCODIV3 34
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+#define PXA1908_CLK_PLL4VCO 35
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+#define PXA1908_CLK_PLL4 36
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+#define PXA1908_CLK_PLL4P 37
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+#define PXA1908_CLK_PLL4VCODIV3 38
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+
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+/* apb (apbc) peripherals */
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+#define PXA1908_CLK_UART0 1
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+#define PXA1908_CLK_UART1 2
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+#define PXA1908_CLK_GPIO 3
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+#define PXA1908_CLK_PWM0 4
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+#define PXA1908_CLK_PWM1 5
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+#define PXA1908_CLK_PWM2 6
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+#define PXA1908_CLK_PWM3 7
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+#define PXA1908_CLK_SSP0 8
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+#define PXA1908_CLK_SSP1 9
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+#define PXA1908_CLK_IPC_RST 10
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+#define PXA1908_CLK_RTC 11
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+#define PXA1908_CLK_TWSI0 12
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+#define PXA1908_CLK_KPC 13
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+#define PXA1908_CLK_SWJTAG 14
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+#define PXA1908_CLK_SSP2 15
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+#define PXA1908_CLK_TWSI1 16
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+#define PXA1908_CLK_THERMAL 17
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+#define PXA1908_CLK_TWSI3 18
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+
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+/* apb (apbcp) peripherals */
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+#define PXA1908_CLK_UART2 1
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+#define PXA1908_CLK_TWSI2 2
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+#define PXA1908_CLK_AICER 3
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+
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+/* axi (apmu) peripherals */
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+#define PXA1908_CLK_CCIC1 1
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+#define PXA1908_CLK_ISP 2
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+#define PXA1908_CLK_DSI1 3
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+#define PXA1908_CLK_DISP1 4
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+#define PXA1908_CLK_CCIC0 5
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+#define PXA1908_CLK_SDH0 6
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+#define PXA1908_CLK_SDH1 7
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+#define PXA1908_CLK_USB 8
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+#define PXA1908_CLK_NF 9
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+#define PXA1908_CLK_CORE_DEBUG 10
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+#define PXA1908_CLK_VPU 11
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+#define PXA1908_CLK_GC 12
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+#define PXA1908_CLK_SDH2 13
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+#define PXA1908_CLK_GC2D 14
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+#define PXA1908_CLK_TRACE 15
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+#define PXA1908_CLK_DVC_DFC_DEBUG 16
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+
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+#endif
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--
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2.42.0
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