63e2807916
- switch sources to official repo https://source.denx.de/u-boot - use tag v2021.07 - extract patches from pine64-org - enable DMA transfers from eMMC and mSD (u-boot from Megi) [ci:skip-build] already built successfully in CI
148 lines
4.2 KiB
Diff
148 lines
4.2 KiB
Diff
From 6ad822cb4d64beda76cade8761c49b55620a8b5b Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megous@megous.com>
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Date: Tue, 14 Jan 2020 03:56:32 +0100
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Subject: [PATCH 29/29] spl: ARM: Enable CPU caches
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http://u-boot.10912.n7.nabble.com/RFC-PATCH-0-3-spl-Add-D-cache-support-td274750.html
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Signed-off-by: Ondrej Jirman <megous@megous.com>
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---
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arch/arm/lib/cache-cp15.c | 29 ++++++++++++++++++++++++
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common/spl/spl.c | 46 +++++++++++++++++++++++++++++++++++++++
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2 files changed, 75 insertions(+)
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diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
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index aab1bf4360..c2fe0acdc4 100644
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--- a/arch/arm/lib/cache-cp15.c
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+++ b/arch/arm/lib/cache-cp15.c
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@@ -116,6 +116,25 @@ __weak void dram_bank_mmu_setup(int bank)
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set_section_dcache(i, DCACHE_DEFAULT_OPTION);
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}
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+#if defined(CONFIG_SPL_BUILD) && (defined(CONFIG_SPL_MAX_SIZE) || \
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+ defined(CONFIG_SPL_MAX_FOOTPRINT))
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+__weak void sram_bank_mmu_setup(phys_addr_t start, phys_addr_t size)
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+{
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+ int i;
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+
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+ for (i = start >> MMU_SECTION_SHIFT;
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+ i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
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+ i++)
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+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
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+ set_section_dcache(i, DCACHE_WRITETHROUGH);
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+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
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+ set_section_dcache(i, DCACHE_WRITEALLOC);
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+#else
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+ set_section_dcache(i, DCACHE_WRITEBACK);
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+#endif
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+}
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+#endif
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+
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/* to activate the MMU we need to set up virtual memory: use 1M areas */
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static inline void mmu_setup(void)
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{
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@@ -131,6 +150,16 @@ static inline void mmu_setup(void)
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dram_bank_mmu_setup(i);
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}
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+#if defined(CONFIG_SPL_BUILD)
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+#if defined(CONFIG_SPL_MAX_SIZE)
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+ sram_bank_mmu_setup(CONFIG_SPL_TEXT_BASE,
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+ ALIGN(CONFIG_SPL_MAX_SIZE, MMU_SECTION_SIZE));
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+#elif defined(CONFIG_SPL_MAX_FOOTPRINT)
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+ sram_bank_mmu_setup(CONFIG_SPL_TEXT_BASE,
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+ ALIGN(CONFIG_SPL_MAX_FOOTPRINT, MMU_SECTION_SIZE));
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+#endif
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+#endif
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+
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#if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
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/* Set up 4 PTE entries pointing to our 4 1GB page tables */
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for (i = 0; i < 4; i++) {
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diff --git a/common/spl/spl.c b/common/spl/spl.c
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index a0a608fd77..40c9022928 100644
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--- a/common/spl/spl.c
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+++ b/common/spl/spl.c
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@@ -10,6 +10,7 @@
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#include <bloblist.h>
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#include <binman_sym.h>
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#include <bootstage.h>
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+#include <cpu_func.h>
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#include <dm.h>
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#include <handoff.h>
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#include <hang.h>
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@@ -636,6 +637,35 @@ void board_init_f(ulong dummy)
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}
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#endif
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+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
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+ defined(CONFIG_ARM)
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+int reserve_mmu(void)
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+{
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+ phys_addr_t ram_top = 0;
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+ /* reserve TLB table */
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+ gd->arch.tlb_size = PGTABLE_SIZE;
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+
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+#ifdef CONFIG_SYS_SDRAM_BASE
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+ ram_top = CONFIG_SYS_SDRAM_BASE;
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+#endif
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+ ram_top += get_effective_memsize();
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+ gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
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+ debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
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+ gd->arch.tlb_addr + gd->arch.tlb_size);
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+ return 0;
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+}
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+
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+__weak int dram_init_banksize(void)
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+{
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+#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
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+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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+ gd->bd->bi_dram[0].size = get_effective_memsize();
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+#endif
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+ return 0;
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+}
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+
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+#endif
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+
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void board_init_r(gd_t *dummy1, ulong dummy2)
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{
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u32 spl_boot_list[] = {
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@@ -651,6 +681,12 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
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debug(">>" SPL_TPL_PROMPT "board_init_r()\n");
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spl_set_bd();
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+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
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+ defined(CONFIG_ARM)
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+ dram_init_banksize();
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+ reserve_mmu();
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+ enable_caches();
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+#endif
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#if defined(CONFIG_SYS_SPL_MALLOC_START)
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mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
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@@ -661,6 +697,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
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if (spl_init())
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hang();
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}
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+ if (IS_ENABLED(CONFIG_SPL_ALLOC_BD) && spl_alloc_bd()) {
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+ puts("Cannot alloc bd\n");
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+ hang();
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+ }
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+
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#if !defined(CONFIG_PPC) && !defined(CONFIG_ARCH_MX6)
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/*
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* timer_init() does not exist on PPC systems. The timer is initialized
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@@ -728,6 +769,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
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ret);
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}
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+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
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+ defined(CONFIG_ARM)
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+ cleanup_before_linux();
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+#endif
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+
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#ifdef CONFIG_CPU_V7M
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spl_image.entry_point |= 0x1;
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#endif
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--
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2.31.1
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