213d01a99a
tracks https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/tree/?h=for-next and adds sdm660 patches on top of it
519 lines
12 KiB
Diff
519 lines
12 KiB
Diff
From 9dd44ed79e2077eeb88a07f8ef37f70578ca695e Mon Sep 17 00:00:00 2001
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From: Alexey Min <alexey.min@gmail.com>
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Date: Wed, 22 Jan 2020 00:55:00 +0300
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Subject: [PATCH] arm64: dts: qcom: Add sdm630/sdm660 SoC and
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xiaomi-lavender support
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Initial device tree support for Qualcomm SDM660 SoC and
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xiaomi-lavender (Redmi Note 7).
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SDM630 is based on SDM660 soc and all SDM660 specific drivers are
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compatible with it. SDM660 is also based off of MSM8998 so it uses some
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of its drivers as well.
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The device tree is based on the CAF 4.4 kernel tree.
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The device can be booted into the initrd with a shell over UART and
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simple-framebuffer display.
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Features:
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* CPU nodes
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* Timer nodes
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* Interrupt controller
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* Global Clock Controller
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* Top Level Mode Multiplexer (pin controller)
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* UART node
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This is inspired by and based on the work of Craig Tatlor in
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https://patchwork.kernel.org/patch/10563667/
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Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
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Signed-off-by: Alexey Minnekhanov <alexey.min@gmail.com>
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---
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arch/arm64/boot/dts/qcom/Makefile | 1 +
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.../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 75 ++++
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arch/arm64/boot/dts/qcom/sdm660.dtsi | 378 ++++++++++++++++++
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3 files changed, 454 insertions(+)
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create mode 100644 arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
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create mode 100644 arch/arm64/boot/dts/qcom/sdm660.dtsi
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diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
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index cc103f7020fd..0f2c33d611df 100644
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--- a/arch/arm64/boot/dts/qcom/Makefile
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+++ b/arch/arm64/boot/dts/qcom/Makefile
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@@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
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+dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
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diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
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new file mode 100644
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index 000000000000..5305ef843650
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--- /dev/null
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+++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
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@@ -0,0 +1,75 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2020, Aleksey Minnekhanov <alexey.min@gmail.com>
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+ */
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+
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+/dts-v1/;
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+
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+#include "sdm660.dtsi"
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+
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+/ {
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+ model = "Xiaomi Redmi Note 7";
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+ compatible = "xiaomi,lavender", "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp";
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+ /* required for bootloader to select correct board */
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+ qcom,msm-id = <0x13d 0x0>;
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+ qcom,board-id = <0x20008 0>;
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+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
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+ <0x0001001b 0x0201011a 0x0 0x0>,
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+ <0x0001001b 0x0102001a 0x0 0x0>;
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+
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+ aliases {
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+ serial0 = &blsp1_uart2;
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+ };
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+
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+ chosen {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ stdout-path = "serial0:115200n8";
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+
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+ framebuffer@0x9d400000 {
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+ compatible = "simple-framebuffer";
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+ reg = <0x0 0x9d400000 0x0 (1080 * 2340 * 4)>;
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+ width = <1080>;
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+ height = <2340>;
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+ stride = <(1080 * 4)>;
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+ format = "a8r8g8b8";
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+ };
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+ };
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+
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+ reserved-memory {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ linux,cma {
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+ compatible = "shared-dma-pool";
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+ alloc-ranges = <0 0x00000000 0 0xffffffff>;
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+ reusable;
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+ alignment = <0 0x400000>;
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+ size = <0 0x2c00000>;
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+ linux,cma-default;
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+ };
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+
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+ framebuffer_region@9d400000 {
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+ reg = <0x0 0x9d400000 0x0 0x02400000>;
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+ no-map;
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+ };
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+
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+ ramoops@a0000000 {
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+ compatible = "ramoops";
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+ reg = <0x0 0xa0000000 0x0 0x400000>;
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+ console-size = <0x20000>;
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+ record-size = <0x20000>;
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+ ftrace-size = <0x0>;
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+ pmsg-size = <0x20000>;
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+ };
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+ };
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+};
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+
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+&blsp1_uart2 {
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+ status = "okay";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart_console_active>;
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+};
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diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi
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new file mode 100644
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index 000000000000..97db2017c8c4
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--- /dev/null
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+++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi
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@@ -0,0 +1,378 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+/* Copyright (c) 2018, Craig Tatlor.
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+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2020, Aleksey Minnekhanov <alexey.min@gmail.com>
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+ */
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+
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
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+
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+/ {
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+ model = "Qualcomm Technologies, Inc. SDM 660";
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+ compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp";
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+
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+ interrupt-parent = <&intc>;
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+
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ chosen { };
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+
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+ memory {
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+ device_type = "memory";
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+ /* We expect the bootloader to fill in the reg */
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+ reg = <0 0 0 0>;
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+ };
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+
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+ cpus {
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+ #address-cells = <2>;
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+ #size-cells = <0>;
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+
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+ CPU0: cpu@100 {
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+ device_type = "cpu";
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+ compatible = "arm,armv8";
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+ reg = <0x0 0x100>;
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+ enable-method = "psci";
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+ efficiency = <1126>;
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+ next-level-cache = <&L2_1>;
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+ L2_1: l2-cache {
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+ compatible = "arm,arch-cache";
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+ cache-level = <2>;
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+ };
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+ L1_I_100: l1-icache {
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+ compatible = "arm,arch-cache";
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+ };
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+ L1_D_100: l1-dcache {
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+ compatible = "arm,arch-cache";
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+ };
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+ };
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+
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+ CPU1: cpu@101 {
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+ device_type = "cpu";
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+ compatible = "arm,armv8";
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+ reg = <0x0 0x101>;
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+ enable-method = "psci";
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+ efficiency = <1126>;
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+ next-level-cache = <&L2_1>;
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+ L1_I_101: l1-icache {
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+ compatible = "arm,arch-cache";
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+ };
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+ L1_D_101: l1-dcache {
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+ compatible = "arm,arch-cache";
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+ };
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+ };
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+
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+ CPU2: cpu@102 {
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+ device_type = "cpu";
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+ compatible = "arm,armv8";
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+ reg = <0x0 0x102>;
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+ enable-method = "psci";
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+ efficiency = <1126>;
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+ next-level-cache = <&L2_1>;
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+ L1_I_102: l1-icache {
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+ compatible = "arm,arch-cache";
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+ };
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+ L1_D_102: l1-dcache {
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+ compatible = "arm,arch-cache";
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+ };
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+ };
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+
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+ CPU3: cpu@103 {
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+ device_type = "cpu";
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+ compatible = "arm,armv8";
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+ reg = <0x0 0x103>;
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+ enable-method = "psci";
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+ efficiency = <1126>;
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+ next-level-cache = <&L2_1>;
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+ L1_I_103: l1-icache {
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+ compatible = "arm,arch-cache";
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+ };
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+ L1_D_103: l1-dcache {
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+ compatible = "arm,arch-cache";
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+ };
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+ };
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+
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+ CPU4: cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,armv8";
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+ reg = <0x0 0x0>;
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+ enable-method = "psci";
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+ efficiency = <1024>;
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+ next-level-cache = <&L2_0>;
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+ L2_0: l2-cache {
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+ compatible = "arm,arch-cache";
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+ cache-level = <2>;
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+ };
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+ L1_I_0: l1-icache {
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+ compatible = "arm,arch-cache";
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+ };
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+ L1_D_0: l1-dcache {
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+ compatible = "arm,arch-cache";
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+ };
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+ };
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+
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+ CPU5: cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,armv8";
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+ reg = <0x0 0x1>;
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+ enable-method = "psci";
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+ efficiency = <1024>;
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+ next-level-cache = <&L2_0>;
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+ L1_I_1: l1-icache {
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+ compatible = "arm,arch-cache";
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+ };
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+ L1_D_1: l1-dcache {
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+ compatible = "arm,arch-cache";
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+ };
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+ };
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+
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+ CPU6: cpu@2 {
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+ device_type = "cpu";
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+ compatible = "arm,armv8";
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+ reg = <0x0 0x2>;
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+ enable-method = "psci";
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+ efficiency = <1024>;
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+ next-level-cache = <&L2_0>;
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+ L1_I_2: l1-icache {
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+ compatible = "arm,arch-cache";
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+ };
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+ L1_D_2: l1-dcache {
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+ compatible = "arm,arch-cache";
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+ };
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+ };
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+
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+ CPU7: cpu@3 {
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+ device_type = "cpu";
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+ compatible = "arm,armv8";
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+ reg = <0x0 0x3>;
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+ enable-method = "psci";
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+ efficiency = <1024>;
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+ next-level-cache = <&L2_0>;
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+ L1_I_3: l1-icache {
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+ compatible = "arm,arch-cache";
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+ };
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+ L1_D_3: l1-dcache {
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+ compatible = "arm,arch-cache";
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+ };
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+ };
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+
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+ cpu-map {
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+ cluster0 {
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+ core0 {
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+ cpu = <&CPU4>;
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+ };
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+
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+ core1 {
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+ cpu = <&CPU5>;
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+ };
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+
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+ core2 {
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+ cpu = <&CPU6>;
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+ };
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+
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+ core3 {
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+ cpu = <&CPU7>;
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+ };
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+ };
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+
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+ cluster1 {
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+ core0 {
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+ cpu = <&CPU0>;
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+ };
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+
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+ core1 {
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+ cpu = <&CPU1>;
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+ };
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+
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+ core2 {
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+ cpu = <&CPU2>;
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+ };
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+
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+ core3 {
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+ cpu = <&CPU3>;
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+ };
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+ };
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+ };
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+ };
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+
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+ psci {
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+ compatible = "arm,psci-1.0";
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+ method = "smc";
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+ };
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+
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+ firmware {
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+ scm {
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+ compatible = "qcom,scm";
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+ };
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+ };
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+
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+
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+ timer {
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+ compatible = "arm,armv8-timer";
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+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
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+ };
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+
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+ clocks {
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+ xo_board {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <19200000>;
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+ clock-output-names = "xo_board";
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+ };
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+
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+ sleep_clk {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <32764>;
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+ clock-output-names = "sleep_clk";
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+ };
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+ };
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+
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+ soc: soc {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0 0 0xffffffff>;
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+ compatible = "simple-bus";
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+
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+ intc: interrupt-controller@17a00000 {
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+ compatible = "arm,gic-v3";
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+ // ^^ sdm630 should propbably add "qcom,msm8996-gic-v3"
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+ reg = <0x17a00000 0x10000>,
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+ <0x17b00000 0x100000>;
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+ #interrupt-cells = <3>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ interrupt-controller;
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+ #redistributor-regions = <1>;
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+ redistributor-stride = <0x0 0x20000>;
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+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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+ timer@17920000 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ compatible = "arm,armv7-timer-mem";
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+ reg = <0x17920000 0x1000>;
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+
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+ frame@17921000 {
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+ frame-number = <0>;
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+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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+ reg = <0x17921000 0x1000>,
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+ <0x17922000 0x1000>;
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+ };
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+
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+ frame@17923000 {
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+ frame-number = <1>;
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+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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+ reg = <0x17923000 0x1000>;
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+ status = "disabled";
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+ };
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+
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+ frame@17924000 {
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+ frame-number = <2>;
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+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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+ reg = <0x17924000 0x1000>;
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+ status = "disabled";
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+ };
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+
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+ frame@17925000 {
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+ frame-number = <3>;
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+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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+ reg = <0x17925000 0x1000>;
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+ status = "disabled";
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+ };
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+
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+ frame@17926000 {
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+ frame-number = <4>;
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+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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+ reg = <0x17926000 0x1000>;
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+ status = "disabled";
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+ };
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+
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+ frame@17927000 {
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+ frame-number = <5>;
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+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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+ reg = <0x17927000 0x1000>;
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+ status = "disabled";
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+ };
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+
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+ frame@17928000 {
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+ frame-number = <6>;
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+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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+ reg = <0x17928000 0x1000>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ gcc: clock-controller@100000 {
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+ compatible = "qcom,gcc-sdm660";
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ #power-domain-cells = <1>;
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+ reg = <0x100000 0x94000>;
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+ };
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+
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+ tlmm: pinctrl@3100000 {
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+ compatible = "qcom,sdm660-pinctrl";
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+ reg = <0x3100000 0x400000>,
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+ <0x3500000 0x400000>,
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+ <0x3900000 0x400000>;
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+ reg-names = "south", "center", "north";
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+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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+ gpio-controller;
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+ gpio-ranges = <&tlmm 0 0 114>;
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+ gpio-reserved-ranges = <8 4>;
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+ #gpio-cells = <2>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+
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+ uart_console_active: uart_console_active {
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+ pinmux {
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+ pins = "gpio4", "gpio5";
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+ function = "blsp_uart2";
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+ };
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+
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+ pinconf {
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+ pins = "gpio4", "gpio5";
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+ drive-strength = <2>;
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+ bias-disable;
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+ };
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+ };
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+ };
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|
+
|
|
+ blsp1_uart2: serial@c170000 {
|
|
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
+ reg = <0xc170000 0x1000>;
|
|
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
|
|
+ <&gcc GCC_BLSP1_AHB_CLK>;
|
|
+ clock-names = "core", "iface";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spmi_bus: qcom,spmi@800f000 {
|
|
+ compatible = "qcom,spmi-pmic-arb";
|
|
+ reg = <0x800f000 0x1000>,
|
|
+ <0x8400000 0x1000000>,
|
|
+ <0x9400000 0x1000000>,
|
|
+ <0xa400000 0x220000>,
|
|
+ <0x800a000 0x3000>;
|
|
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
+ interrupt-names = "periph_irq";
|
|
+ interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ qcom,ee = <0>;
|
|
+ qcom,channel = <0>;
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <0>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <4>;
|
|
+ cell-index = <0>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
--
|
|
2.20.1
|
|
|