63e2807916
- switch sources to official repo https://source.denx.de/u-boot - use tag v2021.07 - extract patches from pine64-org - enable DMA transfers from eMMC and mSD (u-boot from Megi) [ci:skip-build] already built successfully in CI
64 lines
2.6 KiB
Diff
64 lines
2.6 KiB
Diff
From 8bd521470df1cb6324520babf9d3a2e96bc7b96e Mon Sep 17 00:00:00 2001
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From: Andre Przywara <andre.przywara@arm.com>
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Date: Wed, 5 May 2021 09:57:47 +0100
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Subject: [PATCH 03/29] mmc: sunxi: Fix MMC clock parent selection
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Most Allwinner SoCs which use the so called "new timing mode" in their
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MMC controllers actually use the double-rate PLL6/PERIPH0 clock as their
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parent input clock. This is interestingly enough compensated by a hidden
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"by 2" post-divider in the mod clock, so the divider and actual output
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rate stay the same.
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Even though for the H6 and H616 (but only for them!) we use the doubled
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input clock for the divider computation, we never accounted for the
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implicit post-divider, so the clock was only half the speed on those SoCs.
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Clean up the code around that selection, to always use the normal PLL6
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(PERIPH0(1x)) clock as an input. As the rate and divider are the same,
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that makes no difference.
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Explain the hardware differences in a comment.
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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---
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arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 2 +-
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drivers/mmc/sunxi_mmc.c | 10 +++++++---
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2 files changed, 8 insertions(+), 4 deletions(-)
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diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
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index 62abfc4ef6..e000f78ff4 100644
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--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
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+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
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@@ -326,7 +326,7 @@ struct sunxi_ccm_reg {
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#define CCM_MMC_CTRL_M(x) ((x) - 1)
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#define CCM_MMC_CTRL_N(x) ((x) << 8)
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#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
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-#define CCM_MMC_CTRL_PLL6X2 (0x1 << 24)
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+#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
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#define CCM_MMC_CTRL_PLL_PERIPH2X2 (0x2 << 24)
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#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
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/* H6 doesn't have these delays */
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diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
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index 869af993d3..bc68debdad 100644
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--- a/drivers/mmc/sunxi_mmc.c
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+++ b/drivers/mmc/sunxi_mmc.c
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@@ -124,10 +124,14 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
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#ifdef CONFIG_MACH_SUN9I
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pll = CCM_MMC_CTRL_PLL_PERIPH0;
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pll_hz = clock_get_pll4_periph0();
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-#elif defined(CONFIG_SUN50I_GEN_H6)
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- pll = CCM_MMC_CTRL_PLL6X2;
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- pll_hz = clock_get_pll6() * 2;
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#else
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+ /*
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+ * SoCs since the A64 (H5, H6, H616) actually use the doubled
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+ * rate of PLL6/PERIPH0 as an input clock, but compensate for
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+ * that with a fixed post-divider of 2 in the mod clock.
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+ * This cancels each other out, so for simplicity we just
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+ * pretend it's always PLL6 without a post divider here.
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+ */
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pll = CCM_MMC_CTRL_PLL6;
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pll_hz = clock_get_pll6();
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#endif
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--
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2.31.1
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