linux-postmarketos-exynos5: fix Mali T628 (MR 3217)

[ci:skip-build] Already built successfuly on CI in MR
This commit is contained in:
Anton Bambura 2022-06-09 06:23:03 +03:00 committed by Newbyte
parent 20c7501b50
commit e4c9eaf06e
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8 changed files with 486 additions and 1 deletions

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With this patch panfrost is able to drive T628 (r1p0) GPU on some
armv8 SoCs (in particular BE-M1000). Without the patch rendering
is horribly broken (desktop is completely unusable) and eventually
the GPU locks up (it takes from a few seconds to a couple of
minutes).
Using the second core group requires support in Mesa (and an UABI
change): the userspace should
1) set PANFROST_JD_DOESNT_NEED_COHERENCY_ON_GPU flag to opt-in
to allowing the job to run across all cores.
2) set PANFROST_RUN_ON_SECOND_CORE_GROUP flag to allow compute
jobs to be run on the second core group (at the moment Mesa
does not advertise compute support on anything older than
Mali T760)
But there's little point adding such flags until someone (myself)
steps up to do the Mesa work.
Signed-off-by: Alexey Sheplyakov <asheplyakov@basealt.ru>
Signed-off-by: Vadim V. Vlasov <vadim.vlasov@elpitech.ru>
Tested-by: Alexey Sheplyakov <asheplyakov@basealt.ru>
Co-developed-by: Steven Price <steven.price@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220115160658.582646-1-asheplyakov@basealt.ru
---
drivers/gpu/drm/panfrost/panfrost_gpu.c | 27 ++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c
index f8355de6e335..15cec831a99a 100644
--- a/drivers/gpu/drm/panfrost/panfrost_gpu.c
+++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c
@@ -320,19 +320,36 @@ void panfrost_gpu_power_on(struct panfrost_device *pfdev)
{
int ret;
u32 val;
+ u64 core_mask = U64_MAX;
panfrost_gpu_init_quirks(pfdev);
- /* Just turn on everything for now */
- gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present);
+ if (pfdev->features.l2_present != 1) {
+ /*
+ * Only support one core group now.
+ * ~(l2_present - 1) unsets all bits in l2_present except
+ * the bottom bit. (l2_present - 2) has all the bits in
+ * the first core group set. AND them together to generate
+ * a mask of cores in the first core group.
+ */
+ core_mask = ~(pfdev->features.l2_present - 1) &
+ (pfdev->features.l2_present - 2);
+ dev_info_once(pfdev->dev, "using only 1st core group (%lu cores from %lu)\n",
+ hweight64(core_mask),
+ hweight64(pfdev->features.shader_present));
+ }
+ gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present & core_mask);
ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO,
- val, val == pfdev->features.l2_present, 100, 20000);
+ val, val == (pfdev->features.l2_present & core_mask),
+ 100, 20000);
if (ret)
dev_err(pfdev->dev, "error powering up gpu L2");
- gpu_write(pfdev, SHADER_PWRON_LO, pfdev->features.shader_present);
+ gpu_write(pfdev, SHADER_PWRON_LO,
+ pfdev->features.shader_present & core_mask);
ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO,
- val, val == pfdev->features.shader_present, 100, 20000);
+ val, val == (pfdev->features.shader_present & core_mask),
+ 100, 20000);
if (ret)
dev_err(pfdev->dev, "error powering up gpu shader");

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From: Dongwon Kim @ 2021-06-10 21:36 UTC (permalink / raw)
To: dri-devel; +Cc: Dongwon Kim
Render clients should be able to create/destroy dumb object to import
and use it as render buffer in case the default DRM device is different
from the render device (i.e. kmsro).
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
---
drivers/gpu/drm/drm_ioctl.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 98ae00661656..f2f72e132741 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -685,9 +685,9 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
DRM_IOCTL_DEF(DRM_IOCTL_MODE_RMFB, drm_mode_rmfb_ioctl, 0),
DRM_IOCTL_DEF(DRM_IOCTL_MODE_PAGE_FLIP, drm_mode_page_flip_ioctl, DRM_MASTER),
DRM_IOCTL_DEF(DRM_IOCTL_MODE_DIRTYFB, drm_mode_dirtyfb_ioctl, DRM_MASTER),
- DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_DUMB, drm_mode_create_dumb_ioctl, 0),
+ DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_DUMB, drm_mode_create_dumb_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_MODE_MAP_DUMB, drm_mode_mmap_dumb_ioctl, 0),
- DRM_IOCTL_DEF(DRM_IOCTL_MODE_DESTROY_DUMB, drm_mode_destroy_dumb_ioctl, 0),
+ DRM_IOCTL_DEF(DRM_IOCTL_MODE_DESTROY_DUMB, drm_mode_destroy_dumb_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_GETPROPERTIES, drm_mode_obj_get_properties_ioctl, 0),
DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_SETPROPERTY, drm_mode_obj_set_property_ioctl, DRM_MASTER),
DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR2, drm_mode_cursor2_ioctl, DRM_MASTER),
--
2.20.1

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From 69abbee01268780b8ccb952555ce8362ad8a8b5e Mon Sep 17 00:00:00 2001
From: Pavel Golikov <Paullo612@ya.ru>
Date: Mon, 6 Jun 2022 17:57:53 +0300
Subject: [PATCH 1/2] ARM/dma-mapping: implement ->alloc_noncontiguous
Implement support for allocating a non-contiguous DMA region.
Implementation is based on one in ma-iommu driver.
Signed-off-by: Pavel Golikov <Paullo612@ya.ru>
---
arch/arm/mm/dma-mapping.c | 59 +++++++++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 4b61541853ea..bbccfba968fc 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1757,6 +1757,63 @@ static void arm_iommu_unmap_sg(struct device *dev,
__iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
}
+static struct sg_table *arm_iommu_alloc_noncontiguous(struct device *dev,
+ size_t size, enum dma_data_direction dir, gfp_t gfp,
+ unsigned long attrs)
+{
+ struct dma_sgt_handle *sh;
+ int count;
+
+ sh = kmalloc(sizeof(*sh), gfp);
+ if (!sh)
+ return NULL;
+
+ size = PAGE_ALIGN(size);
+ count = size >> PAGE_SHIFT;
+
+ /*
+ * Following is a work-around (a.k.a. hack) to prevent pages
+ * with __GFP_COMP being passed to split_page() which cannot
+ * handle them. The real problem is that this flag probably
+ * should be 0 on ARM as it is not supported on this
+ * platform; see CONFIG_HUGETLBFS.
+ */
+ gfp &= ~(__GFP_COMP);
+
+ sh->pages = __iommu_alloc_buffer(dev, size, gfp, attrs, false);
+ if (!sh->pages)
+ goto err_sh;
+
+ if (sg_alloc_table_from_pages(&sh->sgt, sh->pages, count, 0, size,
+ GFP_KERNEL))
+ goto err_buffer;
+
+ if (__iommu_map_sg(dev, sh->sgt.sgl, sh->sgt.orig_nents, dir, attrs,
+ false) < 1)
+ goto err_free_sg;
+
+ return &sh->sgt;
+
+err_free_sg:
+ sg_free_table(&sh->sgt);
+err_buffer:
+ __iommu_free_buffer(dev, sh->pages, size, attrs);
+err_sh:
+ kfree(sh);
+ return NULL;
+}
+
+static void arm_iommu_free_noncontiguous(struct device *dev, size_t size,
+ struct sg_table *sgt, enum dma_data_direction dir)
+{
+ struct dma_sgt_handle *sh = sgt_handle(sgt);
+
+ __iommu_unmap_sg(dev, sgt->sgl, sgt->orig_nents, dir, 0, false);
+ __iommu_free_buffer(dev, sh->pages, PAGE_ALIGN(size), 0);
+ sg_free_table(&sh->sgt);
+ kfree(sh);
+}
+
/**
* arm_iommu_sync_sg_for_cpu
* @dev: valid struct device pointer
@@ -1994,6 +2051,8 @@ static const struct dma_map_ops iommu_ops = {
.map_page = arm_iommu_map_page,
.unmap_page = arm_iommu_unmap_page,
+ .alloc_noncontiguous = arm_iommu_alloc_noncontiguous,
+ .free_noncontiguous = arm_iommu_free_noncontiguous,
.sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
.sync_single_for_device = arm_iommu_sync_single_for_device,
--
2.25.1

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@ -0,0 +1,36 @@
From 1280592e2b14185aeb92dd13b89cc43aac980bad Mon Sep 17 00:00:00 2001
From: Pavel Golikov <Paullo612@ya.ru>
Date: Mon, 6 Jun 2022 18:18:35 +0300
Subject: [PATCH 1/2] iommu/io-pgtable-arm: Fix coherency support for Mali LPAE
Mali T628r0p1 which may be found in Samsung Exynos 5422 SOC is
definitely not dma coherent, and it is not happy with PTE_SH_OS bit set
by default in commit 728da60da7c1 ("iommu/io-pgtable-arm: Support
coherency for Mali LPAE"). Use PTE_SH_IS by default for non dma
coherent Mali GPUs.
Signed-off-by: Pavel Golikov <Paullo612@ya.ru>
---
drivers/iommu/io-pgtable-arm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 94ff319ae8ac..9ac55085e141 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -457,9 +457,10 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
* "outside the GPU" (i.e. either the Inner or System domain in CPU
* terms, depending on coherency).
*/
- if (prot & IOMMU_CACHE && data->iop.fmt != ARM_MALI_LPAE)
+ if (prot & IOMMU_CACHE ||
+ (data->iop.fmt == ARM_MALI_LPAE && !data->iop.cfg.coherent_walk))
pte |= ARM_LPAE_PTE_SH_IS;
- else
+ else if (data->iop.fmt == ARM_MALI_LPAE)
pte |= ARM_LPAE_PTE_SH_OS;
if (prot & IOMMU_NOEXEC)
--
2.25.1

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@ -0,0 +1,36 @@
From f2a9d492a55c3e762af0aced746613e36a2e3849 Mon Sep 17 00:00:00 2001
From: Pavel Golikov <Paullo612@ya.ru>
Date: Mon, 6 Jun 2022 18:00:28 +0300
Subject: [PATCH 2/2] media: s5p-mfc: Allow cache hints for queues
Passing V4L2_MEMORY_FLAG_NON_COHERENT from userspace significantly
improves video rendering performance on Exynos 5422 (Odroid XU4).
Signed-off-by: Pavel Golikov <Paullo612@ya.ru>
---
drivers/media/platform/s5p-mfc/s5p_mfc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
index f6732f031e96..bbfae7b00961 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
@@ -861,6 +861,7 @@ static int s5p_mfc_open(struct file *file)
q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
q->mem_ops = &vb2_dma_contig_memops;
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
+ q->allow_cache_hints = 1;
ret = vb2_queue_init(q);
if (ret) {
mfc_err("Failed to initialize videobuf2 queue(capture)\n");
@@ -896,6 +897,7 @@ static int s5p_mfc_open(struct file *file)
q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
q->mem_ops = &vb2_dma_contig_memops;
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
+ q->allow_cache_hints = 1;
ret = vb2_queue_init(q);
if (ret) {
mfc_err("Failed to initialize videobuf2 queue(output)\n");
--
2.25.1

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@ -0,0 +1,169 @@
From 9002a4c51191dc2c47a85b65011f9aabfa8af22a Mon Sep 17 00:00:00 2001
From: Pavel Golikov <Paullo612@ya.ru>
Date: Mon, 6 Jun 2022 18:32:57 +0300
Subject: [PATCH 2/2] soc: samsung: pm_domains: Bring back old driver
implementation
Using new implementation decreases Mali GPU performance significantly
(with both KBase and Panfrost drivers).
Signed-off-by: Pavel Golikov <Paullo612@ya.ru>
---
drivers/soc/samsung/pm_domains.c | 97 ++++++++++++++++----------------
1 file changed, 49 insertions(+), 48 deletions(-)
diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c
index d07f3c9d6903..1022d40eb700 100644
--- a/drivers/soc/samsung/pm_domains.c
+++ b/drivers/soc/samsung/pm_domains.c
@@ -16,7 +16,7 @@
#include <linux/delay.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
-#include <linux/pm_runtime.h>
+#include <linux/sched.h>
struct exynos_pm_domain_config {
/* Value for LOCAL_PWR_CFG and STATUS fields for each domain */
@@ -72,15 +72,15 @@ static int exynos_pd_power_off(struct generic_pm_domain *domain)
return exynos_pd_power(domain, false);
}
-static const struct exynos_pm_domain_config exynos4210_cfg = {
+static const struct exynos_pm_domain_config exynos4210_cfg __initconst = {
.local_pwr_cfg = 0x7,
};
-static const struct exynos_pm_domain_config exynos5433_cfg = {
+static const struct exynos_pm_domain_config exynos5433_cfg __initconst = {
.local_pwr_cfg = 0xf,
};
-static const struct of_device_id exynos_pm_domain_of_match[] = {
+static const struct of_device_id exynos_pm_domain_of_match[] __initconst = {
{
.compatible = "samsung,exynos4210-pd",
.data = &exynos4210_cfg,
@@ -91,7 +91,7 @@ static const struct of_device_id exynos_pm_domain_of_match[] = {
{ },
};
-static const char *exynos_get_domain_name(struct device_node *node)
+static __init const char *exynos_get_domain_name(struct device_node *node)
{
const char *name;
@@ -100,44 +100,60 @@ static const char *exynos_get_domain_name(struct device_node *node)
return kstrdup_const(name, GFP_KERNEL);
}
-static int exynos_pd_probe(struct platform_device *pdev)
+static __init int exynos4_pm_init_power_domain(void)
{
- const struct exynos_pm_domain_config *pm_domain_cfg;
- struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
- struct of_phandle_args child, parent;
- struct exynos_pm_domain *pd;
- int on, ret;
+ struct device_node *np;
+ const struct of_device_id *match;
- pm_domain_cfg = of_device_get_match_data(dev);
- pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
- if (!pd)
- return -ENOMEM;
+ for_each_matching_node_and_match(np, exynos_pm_domain_of_match, &match) {
+ const struct exynos_pm_domain_config *pm_domain_cfg;
+ struct exynos_pm_domain *pd;
+ int on;
- pd->pd.name = exynos_get_domain_name(np);
- if (!pd->pd.name)
- return -ENOMEM;
+ pm_domain_cfg = match->data;
- pd->base = of_iomap(np, 0);
- if (!pd->base) {
- kfree_const(pd->pd.name);
- return -ENODEV;
- }
+ pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+ if (!pd) {
+ of_node_put(np);
+ return -ENOMEM;
+ }
+ pd->pd.name = exynos_get_domain_name(np);
+ if (!pd->pd.name) {
+ kfree(pd);
+ of_node_put(np);
+ return -ENOMEM;
+ }
- pd->pd.power_off = exynos_pd_power_off;
- pd->pd.power_on = exynos_pd_power_on;
- pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg;
+ pd->base = of_iomap(np, 0);
+ if (!pd->base) {
+ pr_warn("%s: failed to map memory\n", __func__);
+ kfree_const(pd->pd.name);
+ kfree(pd);
+ continue;
+ }
+
+ pd->pd.power_off = exynos_pd_power_off;
+ pd->pd.power_on = exynos_pd_power_on;
+ pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg;
- on = readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg;
+ on = readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg;
+
+ pm_genpd_init(&pd->pd, NULL, !on);
+ of_genpd_add_provider_simple(np, &pd->pd);
+ }
- pm_genpd_init(&pd->pd, NULL, !on);
- ret = of_genpd_add_provider_simple(np, &pd->pd);
+ /* Assign the child power domains to their parents */
+ for_each_matching_node(np, exynos_pm_domain_of_match) {
+ struct of_phandle_args child, parent;
- if (ret == 0 && of_parse_phandle_with_args(np, "power-domains",
- "#power-domain-cells", 0, &parent) == 0) {
child.np = np;
child.args_count = 0;
+ if (of_parse_phandle_with_args(np, "power-domains",
+ "#power-domain-cells", 0,
+ &parent) != 0)
+ continue;
+
if (of_genpd_add_subdomain(&parent, &child))
pr_warn("%pOF failed to add subdomain: %pOF\n",
parent.np, child.np);
@@ -146,21 +162,6 @@ static int exynos_pd_probe(struct platform_device *pdev)
parent.np, child.np);
}
- pm_runtime_enable(dev);
- return ret;
-}
-
-static struct platform_driver exynos_pd_driver = {
- .probe = exynos_pd_probe,
- .driver = {
- .name = "exynos-pd",
- .of_match_table = exynos_pm_domain_of_match,
- .suppress_bind_attrs = true,
- }
-};
-
-static __init int exynos4_pm_init_power_domain(void)
-{
- return platform_driver_register(&exynos_pd_driver);
+ return 0;
}
core_initcall(exynos4_pm_init_power_domain);
--
2.25.1

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@ -0,0 +1,32 @@
From e160a761378551f32b395d3dc054d688ec056caa Mon Sep 17 00:00:00 2001
From: Anton Bambura <jenneron@protonmail.com>
Date: Thu, 9 Jun 2022 05:41:59 +0300
Subject: [PATCH] ARM: dts: exynos: peach-pi: enable GPU
Enable GPU for this device.
Signed-off-by: Anton Bambura <jenneron@protonmail.com>
Tested-by: Valentine Iourine <iourine@iourine.msk.su>
---
arch/arm/boot/dts/exynos5800-peach-pi.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 77013ee58..f3481dedf 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -198,6 +198,11 @@ &fimd {
samsung,invert-vclk;
};
+&gpu {
+ status = "okay";
+ mali-supply = <&buck4_reg>;
+};
+
&hdmi {
status = "okay";
hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
--
2.36.1

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@ -4,7 +4,7 @@
pkgname=linux-postmarketos-exynos5
pkgver=5.16.1
pkgrel=2
pkgrel=3
pkgdesc="Mainline kernel fork for Samsung Exynos5 devices"
arch="armv7"
_carch="arm"
@ -69,6 +69,13 @@ source="
0029-ARM-dts-exynos-peach-pi-use-num-interpolated-steps-f.patch
0030-HACK-ARM-dts-exynos-peach-pi-disable-HDMI-audio.patch
0031-ARM-dts-exynos-peach-pi-add-jack-detection.patch
0032-v2-drm-panfrost-initial-dual-core-group-GPUs-support.patch
0033-drm-set-DRM_RENDER_ALLOW-flag-on.patch
0034-ARM-dma-mapping-implement-alloc_noncontiguous.patch
0035-iommu-io-pgtable-arm-Fix-coherency-support-for-Mali-.patch
0036-media-s5p-mfc-Allow-cache-hints-for-queues.patch
0037-soc-samsung-pm_domains-Bring-back-old-driver-impleme.patch
0038-ARM-dts-exynos-peach-pi-enable-GPU.patch
"
builddir="$srcdir/linux-${_kernver//_/-}"
@ -131,4 +138,11 @@ a3a6cfec604951daab4017a222db9b873805ce94517a1e5a599a091b9d5832ec1948a113bbd655ca
1d29e33d5f3fc192822bb5bf43e8102963ed316c3846f6681e7698ccb85c65a6e8461bd246f61604d1f794c56171ee206b62ab0fea1b5e7c6dd0fbf49d6fb77a 0029-ARM-dts-exynos-peach-pi-use-num-interpolated-steps-f.patch
5e0bc7073adcd5b89e2475cb9387f994bea335eb89a255090890a8b85612085d317779b551044c6cfc5bf6779e624ce01e0d1074f2126a6bcff0570f6916a782 0030-HACK-ARM-dts-exynos-peach-pi-disable-HDMI-audio.patch
75223ced245df537b6a0356641956e3eec79fafc48ebad961d8188e23dc730d1ccf534442630804361d26560c7f58da950c38ce04292fe72fd5329c6a858a4bd 0031-ARM-dts-exynos-peach-pi-add-jack-detection.patch
65d09d5c7f754d1512ad18f62e154ca2577db2fabec68921b44b6725ce340490c61bb9068a957a23a8b8bc5dde045131f0878ffb667d09f48a1610c44eea1685 0032-v2-drm-panfrost-initial-dual-core-group-GPUs-support.patch
e7f08c665bdd4f686b60ea953242aa1f7580d7fafaec9e4c0cad008c6613a91d9682d64f24570a2a0cc00aca5589698173237fde713246385384738a1fe57bdf 0033-drm-set-DRM_RENDER_ALLOW-flag-on.patch
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