linux-postmarketos-exynos5: fix Mali T628 (MR 3217)
[ci:skip-build] Already built successfuly on CI in MR
This commit is contained in:
parent
20c7501b50
commit
e4c9eaf06e
8 changed files with 486 additions and 1 deletions
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@ -0,0 +1,75 @@
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With this patch panfrost is able to drive T628 (r1p0) GPU on some
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armv8 SoCs (in particular BE-M1000). Without the patch rendering
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is horribly broken (desktop is completely unusable) and eventually
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the GPU locks up (it takes from a few seconds to a couple of
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minutes).
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Using the second core group requires support in Mesa (and an UABI
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change): the userspace should
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1) set PANFROST_JD_DOESNT_NEED_COHERENCY_ON_GPU flag to opt-in
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to allowing the job to run across all cores.
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2) set PANFROST_RUN_ON_SECOND_CORE_GROUP flag to allow compute
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jobs to be run on the second core group (at the moment Mesa
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does not advertise compute support on anything older than
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Mali T760)
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But there's little point adding such flags until someone (myself)
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steps up to do the Mesa work.
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Signed-off-by: Alexey Sheplyakov <asheplyakov@basealt.ru>
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Signed-off-by: Vadim V. Vlasov <vadim.vlasov@elpitech.ru>
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Tested-by: Alexey Sheplyakov <asheplyakov@basealt.ru>
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Co-developed-by: Steven Price <steven.price@arm.com>
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Signed-off-by: Steven Price <steven.price@arm.com>
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Link: https://patchwork.freedesktop.org/patch/msgid/20220115160658.582646-1-asheplyakov@basealt.ru
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---
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drivers/gpu/drm/panfrost/panfrost_gpu.c | 27 ++++++++++++++++++++-----
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1 file changed, 22 insertions(+), 5 deletions(-)
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diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c
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index f8355de6e335..15cec831a99a 100644
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--- a/drivers/gpu/drm/panfrost/panfrost_gpu.c
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+++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c
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@@ -320,19 +320,36 @@ void panfrost_gpu_power_on(struct panfrost_device *pfdev)
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{
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int ret;
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u32 val;
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+ u64 core_mask = U64_MAX;
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panfrost_gpu_init_quirks(pfdev);
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- /* Just turn on everything for now */
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- gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present);
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+ if (pfdev->features.l2_present != 1) {
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+ /*
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+ * Only support one core group now.
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+ * ~(l2_present - 1) unsets all bits in l2_present except
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+ * the bottom bit. (l2_present - 2) has all the bits in
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+ * the first core group set. AND them together to generate
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+ * a mask of cores in the first core group.
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+ */
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+ core_mask = ~(pfdev->features.l2_present - 1) &
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+ (pfdev->features.l2_present - 2);
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+ dev_info_once(pfdev->dev, "using only 1st core group (%lu cores from %lu)\n",
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+ hweight64(core_mask),
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+ hweight64(pfdev->features.shader_present));
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+ }
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+ gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present & core_mask);
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ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO,
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- val, val == pfdev->features.l2_present, 100, 20000);
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+ val, val == (pfdev->features.l2_present & core_mask),
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+ 100, 20000);
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if (ret)
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dev_err(pfdev->dev, "error powering up gpu L2");
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- gpu_write(pfdev, SHADER_PWRON_LO, pfdev->features.shader_present);
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+ gpu_write(pfdev, SHADER_PWRON_LO,
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+ pfdev->features.shader_present & core_mask);
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ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO,
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- val, val == pfdev->features.shader_present, 100, 20000);
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+ val, val == (pfdev->features.shader_present & core_mask),
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+ 100, 20000);
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if (ret)
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dev_err(pfdev->dev, "error powering up gpu shader");
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@ -0,0 +1,30 @@
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From: Dongwon Kim @ 2021-06-10 21:36 UTC (permalink / raw)
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To: dri-devel; +Cc: Dongwon Kim
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Render clients should be able to create/destroy dumb object to import
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and use it as render buffer in case the default DRM device is different
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from the render device (i.e. kmsro).
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Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
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---
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drivers/gpu/drm/drm_ioctl.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
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index 98ae00661656..f2f72e132741 100644
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--- a/drivers/gpu/drm/drm_ioctl.c
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+++ b/drivers/gpu/drm/drm_ioctl.c
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@@ -685,9 +685,9 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
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DRM_IOCTL_DEF(DRM_IOCTL_MODE_RMFB, drm_mode_rmfb_ioctl, 0),
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DRM_IOCTL_DEF(DRM_IOCTL_MODE_PAGE_FLIP, drm_mode_page_flip_ioctl, DRM_MASTER),
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DRM_IOCTL_DEF(DRM_IOCTL_MODE_DIRTYFB, drm_mode_dirtyfb_ioctl, DRM_MASTER),
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- DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_DUMB, drm_mode_create_dumb_ioctl, 0),
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+ DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_DUMB, drm_mode_create_dumb_ioctl, DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF(DRM_IOCTL_MODE_MAP_DUMB, drm_mode_mmap_dumb_ioctl, 0),
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- DRM_IOCTL_DEF(DRM_IOCTL_MODE_DESTROY_DUMB, drm_mode_destroy_dumb_ioctl, 0),
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+ DRM_IOCTL_DEF(DRM_IOCTL_MODE_DESTROY_DUMB, drm_mode_destroy_dumb_ioctl, DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_GETPROPERTIES, drm_mode_obj_get_properties_ioctl, 0),
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DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_SETPROPERTY, drm_mode_obj_set_property_ioctl, DRM_MASTER),
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DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR2, drm_mode_cursor2_ioctl, DRM_MASTER),
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--
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2.20.1
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@ -0,0 +1,93 @@
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From 69abbee01268780b8ccb952555ce8362ad8a8b5e Mon Sep 17 00:00:00 2001
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From: Pavel Golikov <Paullo612@ya.ru>
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Date: Mon, 6 Jun 2022 17:57:53 +0300
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Subject: [PATCH 1/2] ARM/dma-mapping: implement ->alloc_noncontiguous
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Implement support for allocating a non-contiguous DMA region.
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Implementation is based on one in ma-iommu driver.
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Signed-off-by: Pavel Golikov <Paullo612@ya.ru>
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---
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arch/arm/mm/dma-mapping.c | 59 +++++++++++++++++++++++++++++++++++++++
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1 file changed, 59 insertions(+)
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diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
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index 4b61541853ea..bbccfba968fc 100644
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--- a/arch/arm/mm/dma-mapping.c
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+++ b/arch/arm/mm/dma-mapping.c
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@@ -1757,6 +1757,63 @@ static void arm_iommu_unmap_sg(struct device *dev,
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__iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
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}
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+static struct sg_table *arm_iommu_alloc_noncontiguous(struct device *dev,
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+ size_t size, enum dma_data_direction dir, gfp_t gfp,
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+ unsigned long attrs)
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+{
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+ struct dma_sgt_handle *sh;
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+ int count;
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+
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+ sh = kmalloc(sizeof(*sh), gfp);
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+ if (!sh)
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+ return NULL;
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+
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+ size = PAGE_ALIGN(size);
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+ count = size >> PAGE_SHIFT;
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+
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+ /*
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+ * Following is a work-around (a.k.a. hack) to prevent pages
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+ * with __GFP_COMP being passed to split_page() which cannot
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+ * handle them. The real problem is that this flag probably
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+ * should be 0 on ARM as it is not supported on this
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+ * platform; see CONFIG_HUGETLBFS.
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+ */
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+ gfp &= ~(__GFP_COMP);
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+
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+ sh->pages = __iommu_alloc_buffer(dev, size, gfp, attrs, false);
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+ if (!sh->pages)
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+ goto err_sh;
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+
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+ if (sg_alloc_table_from_pages(&sh->sgt, sh->pages, count, 0, size,
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+ GFP_KERNEL))
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+ goto err_buffer;
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+
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+ if (__iommu_map_sg(dev, sh->sgt.sgl, sh->sgt.orig_nents, dir, attrs,
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+ false) < 1)
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+ goto err_free_sg;
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+
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+ return &sh->sgt;
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+
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+err_free_sg:
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+ sg_free_table(&sh->sgt);
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+err_buffer:
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+ __iommu_free_buffer(dev, sh->pages, size, attrs);
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+err_sh:
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+ kfree(sh);
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+ return NULL;
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+}
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+
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+static void arm_iommu_free_noncontiguous(struct device *dev, size_t size,
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+ struct sg_table *sgt, enum dma_data_direction dir)
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+{
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+ struct dma_sgt_handle *sh = sgt_handle(sgt);
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+
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+ __iommu_unmap_sg(dev, sgt->sgl, sgt->orig_nents, dir, 0, false);
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+ __iommu_free_buffer(dev, sh->pages, PAGE_ALIGN(size), 0);
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+ sg_free_table(&sh->sgt);
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+ kfree(sh);
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+}
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+
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/**
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* arm_iommu_sync_sg_for_cpu
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* @dev: valid struct device pointer
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@@ -1994,6 +2051,8 @@ static const struct dma_map_ops iommu_ops = {
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.map_page = arm_iommu_map_page,
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.unmap_page = arm_iommu_unmap_page,
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+ .alloc_noncontiguous = arm_iommu_alloc_noncontiguous,
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+ .free_noncontiguous = arm_iommu_free_noncontiguous,
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.sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
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.sync_single_for_device = arm_iommu_sync_single_for_device,
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--
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2.25.1
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@ -0,0 +1,36 @@
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From 1280592e2b14185aeb92dd13b89cc43aac980bad Mon Sep 17 00:00:00 2001
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From: Pavel Golikov <Paullo612@ya.ru>
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Date: Mon, 6 Jun 2022 18:18:35 +0300
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Subject: [PATCH 1/2] iommu/io-pgtable-arm: Fix coherency support for Mali LPAE
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Mali T628r0p1 which may be found in Samsung Exynos 5422 SOC is
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definitely not dma coherent, and it is not happy with PTE_SH_OS bit set
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by default in commit 728da60da7c1 ("iommu/io-pgtable-arm: Support
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coherency for Mali LPAE"). Use PTE_SH_IS by default for non dma
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coherent Mali GPUs.
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Signed-off-by: Pavel Golikov <Paullo612@ya.ru>
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---
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drivers/iommu/io-pgtable-arm.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
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index 94ff319ae8ac..9ac55085e141 100644
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--- a/drivers/iommu/io-pgtable-arm.c
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+++ b/drivers/iommu/io-pgtable-arm.c
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@@ -457,9 +457,10 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
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* "outside the GPU" (i.e. either the Inner or System domain in CPU
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* terms, depending on coherency).
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*/
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- if (prot & IOMMU_CACHE && data->iop.fmt != ARM_MALI_LPAE)
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+ if (prot & IOMMU_CACHE ||
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+ (data->iop.fmt == ARM_MALI_LPAE && !data->iop.cfg.coherent_walk))
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pte |= ARM_LPAE_PTE_SH_IS;
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- else
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+ else if (data->iop.fmt == ARM_MALI_LPAE)
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pte |= ARM_LPAE_PTE_SH_OS;
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if (prot & IOMMU_NOEXEC)
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--
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2.25.1
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@ -0,0 +1,36 @@
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From f2a9d492a55c3e762af0aced746613e36a2e3849 Mon Sep 17 00:00:00 2001
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From: Pavel Golikov <Paullo612@ya.ru>
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Date: Mon, 6 Jun 2022 18:00:28 +0300
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Subject: [PATCH 2/2] media: s5p-mfc: Allow cache hints for queues
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Passing V4L2_MEMORY_FLAG_NON_COHERENT from userspace significantly
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improves video rendering performance on Exynos 5422 (Odroid XU4).
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Signed-off-by: Pavel Golikov <Paullo612@ya.ru>
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---
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drivers/media/platform/s5p-mfc/s5p_mfc.c | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
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index f6732f031e96..bbfae7b00961 100644
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--- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
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+++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
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@@ -861,6 +861,7 @@ static int s5p_mfc_open(struct file *file)
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q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
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q->mem_ops = &vb2_dma_contig_memops;
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q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
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+ q->allow_cache_hints = 1;
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ret = vb2_queue_init(q);
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if (ret) {
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mfc_err("Failed to initialize videobuf2 queue(capture)\n");
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@@ -896,6 +897,7 @@ static int s5p_mfc_open(struct file *file)
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q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
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q->mem_ops = &vb2_dma_contig_memops;
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q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
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+ q->allow_cache_hints = 1;
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ret = vb2_queue_init(q);
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if (ret) {
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mfc_err("Failed to initialize videobuf2 queue(output)\n");
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--
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2.25.1
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@ -0,0 +1,169 @@
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From 9002a4c51191dc2c47a85b65011f9aabfa8af22a Mon Sep 17 00:00:00 2001
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From: Pavel Golikov <Paullo612@ya.ru>
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Date: Mon, 6 Jun 2022 18:32:57 +0300
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Subject: [PATCH 2/2] soc: samsung: pm_domains: Bring back old driver
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implementation
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Using new implementation decreases Mali GPU performance significantly
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(with both KBase and Panfrost drivers).
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Signed-off-by: Pavel Golikov <Paullo612@ya.ru>
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---
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drivers/soc/samsung/pm_domains.c | 97 ++++++++++++++++----------------
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1 file changed, 49 insertions(+), 48 deletions(-)
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diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c
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index d07f3c9d6903..1022d40eb700 100644
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--- a/drivers/soc/samsung/pm_domains.c
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+++ b/drivers/soc/samsung/pm_domains.c
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@@ -16,7 +16,7 @@
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#include <linux/delay.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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-#include <linux/pm_runtime.h>
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+#include <linux/sched.h>
|
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struct exynos_pm_domain_config {
|
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/* Value for LOCAL_PWR_CFG and STATUS fields for each domain */
|
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@@ -72,15 +72,15 @@ static int exynos_pd_power_off(struct generic_pm_domain *domain)
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return exynos_pd_power(domain, false);
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}
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-static const struct exynos_pm_domain_config exynos4210_cfg = {
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+static const struct exynos_pm_domain_config exynos4210_cfg __initconst = {
|
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.local_pwr_cfg = 0x7,
|
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};
|
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-static const struct exynos_pm_domain_config exynos5433_cfg = {
|
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+static const struct exynos_pm_domain_config exynos5433_cfg __initconst = {
|
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.local_pwr_cfg = 0xf,
|
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};
|
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|
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-static const struct of_device_id exynos_pm_domain_of_match[] = {
|
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+static const struct of_device_id exynos_pm_domain_of_match[] __initconst = {
|
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{
|
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.compatible = "samsung,exynos4210-pd",
|
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.data = &exynos4210_cfg,
|
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@@ -91,7 +91,7 @@ static const struct of_device_id exynos_pm_domain_of_match[] = {
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{ },
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};
|
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|
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-static const char *exynos_get_domain_name(struct device_node *node)
|
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+static __init const char *exynos_get_domain_name(struct device_node *node)
|
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{
|
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const char *name;
|
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|
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@@ -100,44 +100,60 @@ static const char *exynos_get_domain_name(struct device_node *node)
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return kstrdup_const(name, GFP_KERNEL);
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}
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-static int exynos_pd_probe(struct platform_device *pdev)
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+static __init int exynos4_pm_init_power_domain(void)
|
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{
|
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- const struct exynos_pm_domain_config *pm_domain_cfg;
|
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- struct device *dev = &pdev->dev;
|
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- struct device_node *np = dev->of_node;
|
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- struct of_phandle_args child, parent;
|
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- struct exynos_pm_domain *pd;
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- int on, ret;
|
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+ struct device_node *np;
|
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+ const struct of_device_id *match;
|
||||
|
||||
- pm_domain_cfg = of_device_get_match_data(dev);
|
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- pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
|
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- if (!pd)
|
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- return -ENOMEM;
|
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+ for_each_matching_node_and_match(np, exynos_pm_domain_of_match, &match) {
|
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+ const struct exynos_pm_domain_config *pm_domain_cfg;
|
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+ struct exynos_pm_domain *pd;
|
||||
+ int on;
|
||||
|
||||
- pd->pd.name = exynos_get_domain_name(np);
|
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- if (!pd->pd.name)
|
||||
- return -ENOMEM;
|
||||
+ pm_domain_cfg = match->data;
|
||||
|
||||
- pd->base = of_iomap(np, 0);
|
||||
- if (!pd->base) {
|
||||
- kfree_const(pd->pd.name);
|
||||
- return -ENODEV;
|
||||
- }
|
||||
+ pd = kzalloc(sizeof(*pd), GFP_KERNEL);
|
||||
+ if (!pd) {
|
||||
+ of_node_put(np);
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+ pd->pd.name = exynos_get_domain_name(np);
|
||||
+ if (!pd->pd.name) {
|
||||
+ kfree(pd);
|
||||
+ of_node_put(np);
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
|
||||
- pd->pd.power_off = exynos_pd_power_off;
|
||||
- pd->pd.power_on = exynos_pd_power_on;
|
||||
- pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg;
|
||||
+ pd->base = of_iomap(np, 0);
|
||||
+ if (!pd->base) {
|
||||
+ pr_warn("%s: failed to map memory\n", __func__);
|
||||
+ kfree_const(pd->pd.name);
|
||||
+ kfree(pd);
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ pd->pd.power_off = exynos_pd_power_off;
|
||||
+ pd->pd.power_on = exynos_pd_power_on;
|
||||
+ pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg;
|
||||
|
||||
- on = readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg;
|
||||
+ on = readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg;
|
||||
+
|
||||
+ pm_genpd_init(&pd->pd, NULL, !on);
|
||||
+ of_genpd_add_provider_simple(np, &pd->pd);
|
||||
+ }
|
||||
|
||||
- pm_genpd_init(&pd->pd, NULL, !on);
|
||||
- ret = of_genpd_add_provider_simple(np, &pd->pd);
|
||||
+ /* Assign the child power domains to their parents */
|
||||
+ for_each_matching_node(np, exynos_pm_domain_of_match) {
|
||||
+ struct of_phandle_args child, parent;
|
||||
|
||||
- if (ret == 0 && of_parse_phandle_with_args(np, "power-domains",
|
||||
- "#power-domain-cells", 0, &parent) == 0) {
|
||||
child.np = np;
|
||||
child.args_count = 0;
|
||||
|
||||
+ if (of_parse_phandle_with_args(np, "power-domains",
|
||||
+ "#power-domain-cells", 0,
|
||||
+ &parent) != 0)
|
||||
+ continue;
|
||||
+
|
||||
if (of_genpd_add_subdomain(&parent, &child))
|
||||
pr_warn("%pOF failed to add subdomain: %pOF\n",
|
||||
parent.np, child.np);
|
||||
@@ -146,21 +162,6 @@ static int exynos_pd_probe(struct platform_device *pdev)
|
||||
parent.np, child.np);
|
||||
}
|
||||
|
||||
- pm_runtime_enable(dev);
|
||||
- return ret;
|
||||
-}
|
||||
-
|
||||
-static struct platform_driver exynos_pd_driver = {
|
||||
- .probe = exynos_pd_probe,
|
||||
- .driver = {
|
||||
- .name = "exynos-pd",
|
||||
- .of_match_table = exynos_pm_domain_of_match,
|
||||
- .suppress_bind_attrs = true,
|
||||
- }
|
||||
-};
|
||||
-
|
||||
-static __init int exynos4_pm_init_power_domain(void)
|
||||
-{
|
||||
- return platform_driver_register(&exynos_pd_driver);
|
||||
+ return 0;
|
||||
}
|
||||
core_initcall(exynos4_pm_init_power_domain);
|
||||
--
|
||||
2.25.1
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
From e160a761378551f32b395d3dc054d688ec056caa Mon Sep 17 00:00:00 2001
|
||||
From: Anton Bambura <jenneron@protonmail.com>
|
||||
Date: Thu, 9 Jun 2022 05:41:59 +0300
|
||||
Subject: [PATCH] ARM: dts: exynos: peach-pi: enable GPU
|
||||
|
||||
Enable GPU for this device.
|
||||
|
||||
Signed-off-by: Anton Bambura <jenneron@protonmail.com>
|
||||
Tested-by: Valentine Iourine <iourine@iourine.msk.su>
|
||||
---
|
||||
arch/arm/boot/dts/exynos5800-peach-pi.dts | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
|
||||
index 77013ee58..f3481dedf 100644
|
||||
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
|
||||
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
|
||||
@@ -198,6 +198,11 @@ &fimd {
|
||||
samsung,invert-vclk;
|
||||
};
|
||||
|
||||
+&gpu {
|
||||
+ status = "okay";
|
||||
+ mali-supply = <&buck4_reg>;
|
||||
+};
|
||||
+
|
||||
&hdmi {
|
||||
status = "okay";
|
||||
hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
|
||||
--
|
||||
2.36.1
|
||||
|
|
@ -4,7 +4,7 @@
|
|||
|
||||
pkgname=linux-postmarketos-exynos5
|
||||
pkgver=5.16.1
|
||||
pkgrel=2
|
||||
pkgrel=3
|
||||
pkgdesc="Mainline kernel fork for Samsung Exynos5 devices"
|
||||
arch="armv7"
|
||||
_carch="arm"
|
||||
|
@ -69,6 +69,13 @@ source="
|
|||
0029-ARM-dts-exynos-peach-pi-use-num-interpolated-steps-f.patch
|
||||
0030-HACK-ARM-dts-exynos-peach-pi-disable-HDMI-audio.patch
|
||||
0031-ARM-dts-exynos-peach-pi-add-jack-detection.patch
|
||||
0032-v2-drm-panfrost-initial-dual-core-group-GPUs-support.patch
|
||||
0033-drm-set-DRM_RENDER_ALLOW-flag-on.patch
|
||||
0034-ARM-dma-mapping-implement-alloc_noncontiguous.patch
|
||||
0035-iommu-io-pgtable-arm-Fix-coherency-support-for-Mali-.patch
|
||||
0036-media-s5p-mfc-Allow-cache-hints-for-queues.patch
|
||||
0037-soc-samsung-pm_domains-Bring-back-old-driver-impleme.patch
|
||||
0038-ARM-dts-exynos-peach-pi-enable-GPU.patch
|
||||
"
|
||||
builddir="$srcdir/linux-${_kernver//_/-}"
|
||||
|
||||
|
@ -131,4 +138,11 @@ a3a6cfec604951daab4017a222db9b873805ce94517a1e5a599a091b9d5832ec1948a113bbd655ca
|
|||
1d29e33d5f3fc192822bb5bf43e8102963ed316c3846f6681e7698ccb85c65a6e8461bd246f61604d1f794c56171ee206b62ab0fea1b5e7c6dd0fbf49d6fb77a 0029-ARM-dts-exynos-peach-pi-use-num-interpolated-steps-f.patch
|
||||
5e0bc7073adcd5b89e2475cb9387f994bea335eb89a255090890a8b85612085d317779b551044c6cfc5bf6779e624ce01e0d1074f2126a6bcff0570f6916a782 0030-HACK-ARM-dts-exynos-peach-pi-disable-HDMI-audio.patch
|
||||
75223ced245df537b6a0356641956e3eec79fafc48ebad961d8188e23dc730d1ccf534442630804361d26560c7f58da950c38ce04292fe72fd5329c6a858a4bd 0031-ARM-dts-exynos-peach-pi-add-jack-detection.patch
|
||||
65d09d5c7f754d1512ad18f62e154ca2577db2fabec68921b44b6725ce340490c61bb9068a957a23a8b8bc5dde045131f0878ffb667d09f48a1610c44eea1685 0032-v2-drm-panfrost-initial-dual-core-group-GPUs-support.patch
|
||||
e7f08c665bdd4f686b60ea953242aa1f7580d7fafaec9e4c0cad008c6613a91d9682d64f24570a2a0cc00aca5589698173237fde713246385384738a1fe57bdf 0033-drm-set-DRM_RENDER_ALLOW-flag-on.patch
|
||||
4aa6d1d3e5aaab53a84ba6860acaeb365bafb5ff2b4effe99dd2c2d79df9809f9e930a926a640d36c846a36dc67f09f0edf4e37f9407877884fea4e27fc0d3a2 0034-ARM-dma-mapping-implement-alloc_noncontiguous.patch
|
||||
295e38324a801ed27223daff5d4764520ef06d959dea8eb5c332ed4842caab0d9024c4dc8a49fe2ee2e9d06ad1a14a24daad95388e04e115dda36abcf11a5d63 0035-iommu-io-pgtable-arm-Fix-coherency-support-for-Mali-.patch
|
||||
50edca62096a199b4556c2eb40aa2d3351d2465af5aa927e1f4d7836b261770f54395d54df9a537d1b93de84f00c1c6597f654ffeb2297efb2456343660c3301 0036-media-s5p-mfc-Allow-cache-hints-for-queues.patch
|
||||
855397c5dc6b090efe29079d5bfafdf9be44382bade020113d7d80fabc414f1ce7e8a51889ac5f7f269ef9d5f6541a3615e97386577eadc8fc9dc8fe323d5b0e 0037-soc-samsung-pm_domains-Bring-back-old-driver-impleme.patch
|
||||
5cd16bb932632e20cf952af15a448aebaa8466fa6d7b12c14904b042fa95cb789b6f0c49513608426392e91054c73b71fcffa3a12d0c9fda21259a5dae435a04 0038-ARM-dts-exynos-peach-pi-enable-GPU.patch
|
||||
"
|
||||
|
|
Loading…
Add table
Reference in a new issue