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linux-postmarketos-qcom-sc7180: upgrade to 6.6.28 (MR 4900)

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Nikita Travkin 2024-03-10 12:57:51 +05:00 committed by Stefan Hansson
parent 240365f5a7
commit ad28501092
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GPG key ID: 8A700086A9FE41FD
23 changed files with 1494 additions and 2070 deletions
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31
device/community/linux-postmarketos-qcom-sc7180/0001-drm-panel-edp-Add-enable-timings-for-N140HCA-EAC-pan.patch
View file

@ -1,31 +0,0 @@
From 659a3b8a7ff330a1007bf2844253451b6fdbe9c3 Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Tue, 1 Aug 2023 12:23:37 +0500
Subject: [PATCH 1/5] drm/panel-edp: Add enable timings for N140HCA-EAC panel
Add timings for InnoLux N140HCA-EAC. This panel is found on some laptops
such as Acer Aspire 1.
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20230801-aspire1-cmn-panel-v1-1-c3d88e389805@trvn.ru
---
drivers/gpu/drm/panel/panel-edp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c
index a163585a2a52..31ac50138c48 100644
--- a/drivers/gpu/drm/panel/panel-edp.c
+++ b/drivers/gpu/drm/panel/panel-edp.c
@@ -1887,6 +1887,7 @@ static const struct edp_panel_entry edp_panels[] = {
EDP_PANEL_ENTRY('C', 'M', 'N', 0x1152, &delay_200_500_e80_d50, "N116BCN-EA1"),
EDP_PANEL_ENTRY('C', 'M', 'N', 0x1154, &delay_200_500_e80_d50, "N116BCA-EA2"),
EDP_PANEL_ENTRY('C', 'M', 'N', 0x1247, &delay_200_500_e80_d50, "N120ACA-EA1"),
+ EDP_PANEL_ENTRY('C', 'M', 'N', 0x14d4, &delay_200_500_e80_d50, "N140HCA-EAC"),
EDP_PANEL_ENTRY('I', 'V', 'O', 0x057d, &delay_200_500_e200, "R140NWF5 RH"),
EDP_PANEL_ENTRY('I', 'V', 'O', 0x854b, &delay_200_500_p2e100, "R133NW4K-R0"),
--
2.41.0

10
device/community/linux-postmarketos-qcom-sc7180/0008-remoteproc-qcom-pas-Add-sc7180-adsp.patch → device/community/linux-postmarketos-qcom-sc7180/0001-remoteproc-qcom-pas-Add-sc7180-adsp.patch
View file

@ -1,7 +1,7 @@
From d3e05226627152fff5417c441407fa4a796b707b Mon Sep 17 00:00:00 2001
From 46ee4de1b5c5099e937ffa0dc044390e4455c3b3 Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Thu, 7 Sep 2023 15:02:35 +0500
Subject: [PATCH 08/17] remoteproc: qcom: pas: Add sc7180 adsp
Subject: [PATCH 1/8] remoteproc: qcom: pas: Add sc7180 adsp
sc7180 has a dedicated ADSP similar to the one found in sm8250.
Add it's compatible to the driver reusing the existing config so
@ -16,10 +16,10 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
1 file changed, 1 insertion(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 6afd0941e552..92aa60d81845 100644
index b5447dd2dd35..55fafc68200e 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -956,6 +956,7 @@ static const struct of_device_id adsp_of_match[] = {
@@ -1161,6 +1161,7 @@ static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init },
{ .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
{ .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
@ -28,5 +28,5 @@ index 6afd0941e552..92aa60d81845 100644
{ .compatible = "qcom,sc7280-mpss-pas", .data = &mpss_resource_init},
{ .compatible = "qcom,sc8180x-adsp-pas", .data = &sm8150_adsp_resource},
--
2.43.0
2.43.2

14
device/community/linux-postmarketos-qcom-sc7180/0009-arm64-dts-qcom-sc7180-Add-tertiary-mi2s-pinctrl.patch → device/community/linux-postmarketos-qcom-sc7180/0002-arm64-dts-qcom-sc7180-Add-tertiary-mi2s-pinctrl.patch
View file

@ -1,7 +1,7 @@
From 904af70e09880a072393d4871abe16f99cdde2eb Mon Sep 17 00:00:00 2001
From f997651c8dbcdbff191306117c4d4339d09e0924 Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Thu, 7 Sep 2023 15:02:36 +0500
Subject: [PATCH 09/17] arm64: dts: qcom: sc7180: Add tertiary mi2s pinctrl
Subject: [PATCH 2/8] arm64: dts: qcom: sc7180: Add tertiary mi2s pinctrl
Some devices use tertiary mi2s to connect external audio codec.
Add it near the other two i2s pinctrl definitions so the devices don't
@ -17,12 +17,12 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 64ae9f27ba80..6988140a5270 100644
index f7c528ecb224..db5d04181ac4 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1957,6 +1957,11 @@ pinmux {
function = "lpass_ext";
};
@@ -2042,6 +2042,11 @@ pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
pins = "gpio57";
function = "lpass_ext";
};
+
+ ter_mi2s_active: ter-mi2s-active-state {
@ -33,5 +33,5 @@ index 64ae9f27ba80..6988140a5270 100644
remoteproc_mpss: remoteproc@4080000 {
--
2.43.0
2.43.2

63
device/community/linux-postmarketos-qcom-sc7180/0002-drm-bridge-ti-sn65dsi86-Implement-wait_hpd_asserted.patch
View file

@ -1,63 +0,0 @@
From c093d7dee08532d3171fab9308939308441944ea Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Sat, 8 Apr 2023 13:20:14 +0500
Subject: [PATCH 2/5] drm/bridge: ti-sn65dsi86: Implement wait_hpd_asserted
This bridge doesn't actually implement HPD due to it being way too slow
but instead expects the panel driver to wait enough to assume HPD is
asserted. However some panels (such as the generic 'edp-panel') expect
the bridge to deal with the delay and pass maximum delay to the aux
instead.
In order to support such panels, add a dummy implementation of wait
that would just sleep the maximum delay and assume no failure has
happened.
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20230408082014.235425-1-nikita@trvn.ru
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index b89f7f7ca188..60930d35ea50 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@ -631,6 +631,24 @@ static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
return len;
}
+static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
+{
+ /*
+ * The HPD in this chip is a bit useless (See comment in
+ * ti_sn65dsi86_enable_comms) so if our driver is expected to wait
+ * for HPD, we just assume it's asserted after the wait_us delay.
+ *
+ * In case we are asked to wait forever (wait_us=0) take conservative
+ * 500ms delay.
+ */
+ if (wait_us == 0)
+ wait_us = 500000;
+
+ usleep_range(wait_us, wait_us + 1000);
+
+ return 0;
+}
+
static int ti_sn_aux_probe(struct auxiliary_device *adev,
const struct auxiliary_device_id *id)
{
@@ -640,6 +658,7 @@ static int ti_sn_aux_probe(struct auxiliary_device *adev,
pdata->aux.name = "ti-sn65dsi86-aux";
pdata->aux.dev = &adev->dev;
pdata->aux.transfer = ti_sn_aux_transfer;
+ pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted;
drm_dp_aux_init(&pdata->aux);
ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);
--
2.41.0

12
device/community/linux-postmarketos-qcom-sc7180/0010-arm64-dts-qcom-sc7180-Add-ADSP.patch → device/community/linux-postmarketos-qcom-sc7180/0003-arm64-dts-qcom-sc7180-Add-ADSP.patch
View file

@ -1,7 +1,7 @@
From 73db0fa78b569523c6a5fa8e68ddfbe83a07be6c Mon Sep 17 00:00:00 2001
From 419d22eeba6b335ba58d8dd9d064b871a37cb1fb Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Thu, 7 Sep 2023 15:02:37 +0500
Subject: [PATCH 10/17] arm64: dts: qcom: sc7180: Add ADSP
Subject: [PATCH 3/8] arm64: dts: qcom: sc7180: Add ADSP
sc7180 has an ADSP remoteproc that exclusively controls the audio
hardware on devices that use Qualcomm firmware.
@ -18,10 +18,10 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
1 file changed, 122 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 6988140a5270..b9d6c95191ae 100644
index db5d04181ac4..3683419ee8f5 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -19,6 +19,8 @@
@@ -20,6 +20,8 @@
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@ -30,7 +30,7 @@ index 6988140a5270..b9d6c95191ae 100644
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -3635,6 +3637,126 @@ wifi: wifi@18800000 {
@@ -3781,6 +3783,126 @@ wifi: wifi@18800000 {
status = "disabled";
};
@ -158,5 +158,5 @@ index 6988140a5270..b9d6c95191ae 100644
compatible = "qcom,sc7180-lpasscorecc";
reg = <0 0x62d00000 0 0x50000>,
--
2.43.0
2.43.2

76
device/community/linux-postmarketos-qcom-sc7180/0003-arm64-dts-qcom-sc7180-Don-t-enable-lpass-clocks-by-d.patch
View file

@ -1,76 +0,0 @@
From 9b72464591d389f422b5e4485aa8c97afd79356a Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Mon, 15 May 2023 14:37:41 +0500
Subject: [PATCH 3/5] arm64: dts: qcom: sc7180: Don't enable lpass clocks by
default
lpass clocks are usually blocked from HLOS by the firmware and
instead are managed by the ADSP. Mark them as reserved and explicitly
enable in the CrOS boards that have special, cooperative firmware.
The IDP board gets lpass clocks disabled as it doesn't make use of sound
anyway and might use Qualcomm firmware that blocks those clocks. [1]
[1] https://lore.kernel.org/all/ZBJhmDd3zK%2FAiwBD@google.com/
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230515093744.289045-2-nikita@trvn.ru
---
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 8 ++++++++
arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index eae22e6e97c1..6508628fd5ba 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -777,6 +777,10 @@ alc5682: codec@1a {
};
};
+&lpasscc {
+ status = "okay";
+};
+
&lpass_cpu {
status = "okay";
@@ -802,6 +806,10 @@ hdmi@5 {
};
};
+&lpass_hm {
+ status = "okay";
+};
+
&mdp {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 6f0ee4e13ef1..a7cd017b3ece 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -3576,6 +3576,8 @@ lpasscc: clock-controller@62d00000 {
power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
#clock-cells = <1>;
#power-domain-cells = <1>;
+
+ status = "reserved"; /* Controlled by ADSP */
};
lpass_cpu: lpass@62d87000 {
@@ -3621,6 +3623,8 @@ lpass_hm: clock-controller@63000000 {
clock-names = "iface", "bi_tcxo";
#clock-cells = <1>;
#power-domain-cells = <1>;
+
+ status = "reserved"; /* Controlled by ADSP */
};
};
--
2.41.0

73
device/community/linux-postmarketos-qcom-sc7180/0012-ASoC-qcom-sc7180-Add-support-for-qdsp6-baked-sound.patch → device/community/linux-postmarketos-qcom-sc7180/0004-ASoC-qcom-sc7180-Add-support-for-qdsp6-baked-sound.patch
View file

@ -1,7 +1,7 @@
From 98378d3ecfeb0741b313ff607a2c883ebee26da3 Mon Sep 17 00:00:00 2001
From 86b2a5a727c07a83acea7946a132dddc27549299 Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Thu, 19 Oct 2023 19:14:13 +0500
Subject: [PATCH 12/17] ASoC: qcom: sc7180: Add support for qdsp6 baked sound
Date: Fri, 20 Oct 2023 20:33:47 +0500
Subject: [PATCH 4/8] ASoC: qcom: sc7180: Add support for qdsp6 baked sound
Some sc7180 devices use audio adsp to play sound. The setup for this
adsp is similar to the dirrect lpass usage but requires the use of
@ -19,31 +19,36 @@ trivially expandable to the other devices that will be added in the
future.
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Link: https://lore.kernel.org/r/20231020-sc7180-qdsp-sndcard-v1-2-157706b7d06f@trvn.ru
Signed-off-by: Mark Brown <broonie@kernel.org>
---
sound/soc/qcom/sc7180.c | 194 +++++++++++++++++++++++++++++++++++-----
1 file changed, 172 insertions(+), 22 deletions(-)
sound/soc/qcom/sc7180.c | 195 +++++++++++++++++++++++++++++++++++-----
1 file changed, 173 insertions(+), 22 deletions(-)
diff --git a/sound/soc/qcom/sc7180.c b/sound/soc/qcom/sc7180.c
index 57c5f35dfcc5..c4f58ecd3896 100644
index d1fd40e3f7a9..a198fcda2955 100644
--- a/sound/soc/qcom/sc7180.c
+++ b/sound/soc/qcom/sc7180.c
@@ -15,6 +15,7 @@
#include <sound/pcm.h>
#include <sound/soc.h>
#include <uapi/linux/input-event-codes.h>
+#include "qdsp6/q6afe.h"
@@ -5,6 +5,7 @@
// sc7180.c -- ALSA SoC Machine driver for SC7180
#include "../codecs/rt5682.h"
#include <dt-bindings/sound/sc7180-lpass.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
@@ -20,8 +21,10 @@
#include "../codecs/rt5682s.h"
@@ -22,6 +23,7 @@
#include "common.h"
#include "lpass.h"
+#include "qdsp6/q6afe.h"
#define DEFAULT_MCLK_RATE 19200000
+#define MI2S_BCLK_RATE 1536000
#define RT5682_PLL1_FREQ (48000 * 512)
#define DRIVER_NAME "SC7180"
@@ -134,12 +136,28 @@ static int sc7180_init(struct snd_soc_pcm_runtime *rtd)
@@ -134,12 +137,28 @@ static int sc7180_init(struct snd_soc_pcm_runtime *rtd)
return 0;
}
@ -53,7 +58,7 @@ index 57c5f35dfcc5..c4f58ecd3896 100644
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_soc_card *card = rtd->card;
- struct sc7180_snd_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+
+ switch (cpu_dai->id) {
+ case PRIMARY_MI2S_RX:
@ -73,10 +78,10 @@ index 57c5f35dfcc5..c4f58ecd3896 100644
+
+static int sc7180_startup_realtek_codec(struct snd_soc_pcm_runtime *rtd)
+{
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
int pll_id, pll_source, pll_in, pll_out, clk_id, ret;
@@ -155,8 +173,40 @@ static int sc7180_snd_startup(struct snd_pcm_substream *substream)
@@ -155,8 +174,40 @@ static int sc7180_snd_startup(struct snd_pcm_substream *substream)
clk_id = RT5682S_SCLK_S_PLL2;
pll_out = RT5682_PLL1_FREQ;
pll_in = DEFAULT_MCLK_RATE;
@ -111,13 +116,13 @@ index 57c5f35dfcc5..c4f58ecd3896 100644
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_card *card = rtd->card;
+ struct sc7180_snd_data *data = snd_soc_card_get_drvdata(card);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+ int ret;
+
switch (cpu_dai->id) {
case MI2S_PRIMARY:
if (++data->pri_mi2s_clk_count == 1) {
@@ -166,30 +216,66 @@ static int sc7180_snd_startup(struct snd_pcm_substream *substream)
@@ -166,30 +217,66 @@ static int sc7180_snd_startup(struct snd_pcm_substream *substream)
SNDRV_PCM_STREAM_PLAYBACK);
}
@ -153,8 +158,8 @@ index 57c5f35dfcc5..c4f58ecd3896 100644
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_card *card = rtd->card;
+ struct sc7180_snd_data *data = snd_soc_card_get_drvdata(card);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+ struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
+ int ret;
+
+ switch (cpu_dai->id) {
@ -186,8 +191,8 @@ index 57c5f35dfcc5..c4f58ecd3896 100644
- case MI2S_SECONDARY:
+ case TERTIARY_MI2S_RX:
+ snd_soc_dai_set_sysclk(cpu_dai,
+ Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
+ MI2S_BCLK_RATE,
+ Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
+ MI2S_BCLK_RATE,
+ SNDRV_PCM_STREAM_PLAYBACK);
+
+ snd_soc_dai_set_fmt(codec_dai,
@ -201,7 +206,7 @@ index 57c5f35dfcc5..c4f58ecd3896 100644
break;
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
@@ -247,6 +333,42 @@ static void sc7180_snd_shutdown(struct snd_pcm_substream *substream)
@@ -247,6 +334,42 @@ static void sc7180_snd_shutdown(struct snd_pcm_substream *substream)
}
}
@ -210,7 +215,7 @@ index 57c5f35dfcc5..c4f58ecd3896 100644
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_card *card = rtd->card;
+ struct sc7180_snd_data *data = snd_soc_card_get_drvdata(card);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+
+ switch (cpu_dai->id) {
+ case PRIMARY_MI2S_RX:
@ -228,8 +233,8 @@ index 57c5f35dfcc5..c4f58ecd3896 100644
+ break;
+ case TERTIARY_MI2S_RX:
+ snd_soc_dai_set_sysclk(cpu_dai,
+ Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
+ 0,
+ Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
+ 0,
+ SNDRV_PCM_STREAM_PLAYBACK);
+ break;
+ case DISPLAY_PORT_RX:
@ -243,8 +248,8 @@ index 57c5f35dfcc5..c4f58ecd3896 100644
+
static int sc7180_adau7002_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
@@ -295,11 +417,30 @@ static int sc7180_adau7002_snd_startup(struct snd_pcm_substream *substream)
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
@@ -295,11 +418,30 @@ static int sc7180_adau7002_snd_startup(struct snd_pcm_substream *substream)
return 0;
}
@ -275,7 +280,7 @@ index 57c5f35dfcc5..c4f58ecd3896 100644
static const struct snd_soc_ops sc7180_adau7002_ops = {
.startup = sc7180_adau7002_snd_startup,
};
@@ -355,7 +496,7 @@ static int sc7180_snd_platform_probe(struct platform_device *pdev)
@@ -355,7 +497,7 @@ static int sc7180_snd_platform_probe(struct platform_device *pdev)
struct snd_soc_dai_link *link;
int ret;
int i;
@ -284,7 +289,7 @@ index 57c5f35dfcc5..c4f58ecd3896 100644
/* Allocate the private data */
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
@@ -391,6 +532,8 @@ static int sc7180_snd_platform_probe(struct platform_device *pdev)
@@ -391,6 +533,8 @@ static int sc7180_snd_platform_probe(struct platform_device *pdev)
no_headphone = true;
card->dapm_widgets = sc7180_adau7002_snd_widgets;
card->num_dapm_widgets = ARRAY_SIZE(sc7180_adau7002_snd_widgets);
@ -293,7 +298,7 @@ index 57c5f35dfcc5..c4f58ecd3896 100644
}
ret = qcom_snd_parse_of(card);
@@ -401,6 +544,12 @@ static int sc7180_snd_platform_probe(struct platform_device *pdev)
@@ -401,6 +545,12 @@ static int sc7180_snd_platform_probe(struct platform_device *pdev)
if (no_headphone) {
link->ops = &sc7180_adau7002_ops;
link->init = sc7180_adau7002_init;
@ -306,7 +311,7 @@ index 57c5f35dfcc5..c4f58ecd3896 100644
} else {
link->ops = &sc7180_ops;
link->init = sc7180_init;
@@ -413,6 +562,7 @@ static int sc7180_snd_platform_probe(struct platform_device *pdev)
@@ -413,6 +563,7 @@ static int sc7180_snd_platform_probe(struct platform_device *pdev)
static const struct of_device_id sc7180_snd_device_id[] = {
{.compatible = "google,sc7180-trogdor"},
{.compatible = "google,sc7180-coachz"},
@ -315,5 +320,5 @@ index 57c5f35dfcc5..c4f58ecd3896 100644
};
MODULE_DEVICE_TABLE(of, sc7180_snd_device_id);
--
2.43.0
2.43.2

66
device/community/linux-postmarketos-qcom-sc7180/0004-arm64-dts-qcom-sc7180-Drop-redundant-disable-in-mdp.patch
View file

@ -1,66 +0,0 @@
From d03ea6cf66d36e55b0a57643c1f294b0e828a784 Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Mon, 15 May 2023 14:37:42 +0500
Subject: [PATCH 4/5] arm64: dts: qcom: sc7180: Drop redundant disable in mdp
mdss is useless without a display controller which makes explicitly
enabling mdp redundant. Have it enabled by default to drop the extra
node for all users.
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230515093744.289045-3-nikita@trvn.ru
---
arch/arm64/boot/dts/qcom/sc7180-idp.dts | 4 ----
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 4 ----
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 --
3 files changed, 10 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index 9dee131b1e24..d3c4b5804a69 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -333,10 +333,6 @@ &dsi_phy {
vdds-supply = <&vreg_l4a_0p8>;
};
-&mdp {
- status = "okay";
-};
-
&mdss {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index 6508628fd5ba..f4db4ccf48e5 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -810,10 +810,6 @@ &lpass_hm {
status = "okay";
};
-&mdp {
- status = "okay";
-};
-
&mdss {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index a7cd017b3ece..3f02f1ce6f1e 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2937,8 +2937,6 @@ mdp: display-controller@ae01000 {
interrupt-parent = <&mdss>;
interrupts = <0>;
- status = "disabled";
-
ports {
#address-cells = <1>;
#size-cells = <0>;
--
2.41.0

889
device/community/linux-postmarketos-qcom-sc7180/0005-arm64-dts-qcom-Add-Acer-Aspire-1.patch
View file

@ -1,889 +0,0 @@
From f190c467210f639ca33f072f31dd4e2f1c2bcd8b Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Mon, 15 May 2023 14:37:44 +0500
Subject: [PATCH 5/5] arm64: dts: qcom: Add Acer Aspire 1
Acer Aspire 1 is a WoA laptop based on Snapdragon 7c gen1 platform.
The laptop design is similar to trogdor in the choice of primary
components but the specifics on usage of those differ slightly.
Add the devicetree for the laptop with support for most of the
hardware present.
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230515093744.289045-5-nikita@trvn.ru
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/sc7180-acer-aspire1.dts | 845 ++++++++++++++++++
2 files changed, 846 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index d7669a7cee9f..cf482aaf7156 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -54,6 +54,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7180-acer-aspire1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb
diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
new file mode 100644
index 000000000000..2a80f4090085
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
@@ -0,0 +1,845 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "sc7180.dtsi"
+
+#include "pm6150.dtsi"
+#include "pm6150l.dtsi"
+
+/delete-node/ &tz_mem;
+/delete-node/ &ipa_fw_mem;
+
+/ {
+ model = "Acer Aspire 1";
+ compatible = "acer,aspire1", "qcom,sc7180";
+ chassis-type = "laptop";
+
+ aliases {
+ bluetooth0 = &bluetooth;
+ hsuart0 = &uart3;
+ serial0 = &uart8;
+ wifi0 = &wifi;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ zap_mem: zap-shader@80840000 {
+ reg = <0x0 0x80840000 0 0x2000>;
+ no-map;
+ };
+
+ venus_mem: venus@85b00000 {
+ reg = <0x0 0x85b00000 0 0x500000>;
+ no-map;
+ };
+
+ mpss_mem: mpss@86000000 {
+ reg = <0x0 0x86000000 0x0 0x2000000>;
+ no-map;
+ };
+
+ adsp_mem: adsp@8e400000 {
+ reg = <0x0 0x8e400000 0x0 0x2800000>;
+ no-map;
+ };
+
+ wlan_mem: wlan@93900000 {
+ reg = <0x0 0x93900000 0x0 0x200000>;
+ no-map;
+ };
+ };
+
+ max98357a: audio-codec {
+ compatible = "maxim,max98357a";
+ sdmode-gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&amp_sd_mode_default>;
+ pinctrl-names = "default";
+
+ #sound-dai-cells = <0>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&sn65dsi86_bridge 1000000>;
+ enable-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&soc_bkoff_default>;
+ pinctrl-names = "default";
+ };
+
+ reg_brij_1p2: bridge-1p2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "brij_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ gpio = <&tlmm 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&reg_edp_1p2_en_default>;
+ pinctrl-names = "default";
+ };
+
+ reg_brij_1p8: bridge-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "brij_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ vin-supply = <&vreg_l8c_1p8>;
+
+ gpio = <&tlmm 20 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&reg_edp_1p8_en_default>;
+ pinctrl-names = "default";
+ };
+
+ reg_codec_3p3: codec-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "codec_3p3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 83 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&reg_audio_en_default>;
+ pinctrl-names = "default";
+ };
+
+ reg_lcm_3p3: panel-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "lcm_3p3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 26 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&reg_lcm_en_default>;
+ pinctrl-names = "default";
+ };
+
+ reg_tp_3p3: touchpad-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "tp_3p3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&reg_tp_en_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&dsi0 {
+ vdda-supply = <&vreg_l3c_1p2>;
+ status = "okay";
+};
+
+&dsi0_out {
+ remote-endpoint = <&sn65dsi86_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&dsi_phy {
+ vdds-supply = <&vreg_l4a_0p8>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ /* embedded-controller@76 */
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ /*
+ * NOTE: DSDT defines two possible touchpads, other one is
+ *
+ * reg = <0x15>;
+ * hid-descr-addr = <0x1>;
+ */
+
+ touchpad@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+ hid-descr-addr = <0x20>;
+
+ vdd-supply = <&reg_tp_3p3>;
+
+ interrupts-extended = <&tlmm 94 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&hid_touchpad_default>;
+ pinctrl-names = "default";
+
+ wakeup-source;
+ };
+
+ keyboard@3a {
+ compatible = "hid-over-i2c";
+ reg = <0x3a>;
+ hid-descr-addr = <0x1>;
+
+ interrupts-extended = <&tlmm 33 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&hid_keyboard_default>;
+ pinctrl-names = "default";
+
+ wakeup-source;
+ };
+};
+
+&i2c9 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ alc5682: codec@1a {
+ compatible = "realtek,rt5682i";
+ reg = <0x1a>;
+
+ #sound-dai-cells = <1>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <28 IRQ_TYPE_EDGE_BOTH>;
+
+ pinctrl-0 = <&codec_irq_default>;
+ pinctrl-names = "default";
+
+ AVDD-supply = <&vreg_l15a_1p8>;
+ MICVDD-supply = <&reg_codec_3p3>;
+ VBAT-supply = <&reg_codec_3p3>;
+
+ realtek,dmic1-data-pin = <1>;
+ realtek,dmic1-clk-pin = <1>;
+ realtek,jd-src = <1>;
+ };
+};
+
+&i2c10 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ sn65dsi86_bridge: bridge@2c {
+ compatible = "ti,sn65dsi86";
+ reg = <0x2c>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #pwm-cells = <1>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+
+ enable-gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
+ suspend-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&bridge_en_default>,
+ <&edp_bridge_irq_default>,
+ <&bridge_suspend_default>;
+ pinctrl-names = "default";
+
+ vpll-supply = <&reg_brij_1p8>;
+ vccio-supply = <&reg_brij_1p8>;
+ vcca-supply = <&reg_brij_1p2>;
+ vcc-supply = <&reg_brij_1p2>;
+
+ clocks = <&rpmhcc RPMH_LN_BB_CLK3>;
+ clock-names = "refclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sn65dsi86_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ sn65dsi86_out: endpoint {
+ data-lanes = <0 1>;
+ remote-endpoint = <&panel_in_edp>;
+ };
+ };
+ };
+
+ aux-bus {
+ panel: panel {
+ compatible = "edp-panel";
+ power-supply = <&reg_lcm_3p3>;
+ backlight = <&backlight>;
+ hpd-absent-delay-ms = <200>;
+
+ port {
+ panel_in_edp: endpoint {
+ remote-endpoint = <&sn65dsi86_out>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ memory-region = <&zap_mem>;
+ firmware-name = "qcom/sc7180/acer/aspire1/qcdxkmsuc7180.mbn";
+ };
+};
+
+&mdss {
+ status = "okay";
+};
+
+&pm6150_adc {
+ thermistor@4e {
+ reg = <ADC5_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ charger-thermistor@4f {
+ reg = <ADC5_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm6150_adc_tm {
+ status = "okay";
+
+ charger-thermistor@0 {
+ reg = <0>;
+ io-channels = <&pm6150_adc ADC5_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ thermistor@1 {
+ reg = <1>;
+ io-channels = <&pm6150_adc ADC5_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
+&pm6150_pon {
+ status = "disabled";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/sc7180/acer/aspire1/qcmpss7180_nm.mbn";
+ status = "okay";
+};
+
+&sdhc_1 {
+ pinctrl-0 = <&sdc1_default>;
+ pinctrl-1 = <&sdc1_sleep>;
+ pinctrl-names = "default", "sleep";
+ vmmc-supply = <&vreg_l19a_2p9>;
+ vqmmc-supply = <&vreg_l12a_1p8>;
+
+ status = "okay";
+};
+
+&uart3 {
+ /delete-property/interrupts;
+ interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 41 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-1 = <&qup_uart3_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+
+ bluetooth: bluetooth {
+ compatible = "qcom,wcn3991-bt";
+ vddio-supply = <&vreg_l10a_1p8>;
+ vddxo-supply = <&vreg_l1c_1p8>;
+ vddrf-supply = <&vreg_l2c_1p3>;
+ vddch0-supply = <&vreg_l10c_3p3>;
+ max-speed = <3200000>;
+ };
+};
+
+&uart8 {
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb_hub_2_x: hub@1 {
+ compatible = "usbbda,5411";
+ reg = <1>;
+ peer-hub = <&usb_hub_3_x>;
+ };
+
+ usb_hub_3_x: hub@2 {
+ compatible = "usbbda,411";
+ reg = <2>;
+ peer-hub = <&usb_hub_2_x>;
+ };
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l4a_0p8>;
+ vdda-pll-supply = <&vreg_l11a_1p8>;
+ vdda-phy-dpdm-supply = <&vreg_l17a_3p0>;
+ qcom,imp-res-offset-value = <8>;
+ qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_15_PERCENT>;
+ qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
+ qcom,bias-ctrl-value = <0x22>;
+ qcom,charge-ctrl-value = <3>;
+ qcom,hsdisc-trim-value = <0>;
+
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&vreg_l3c_1p2>;
+ vdda-pll-supply = <&vreg_l4a_0p8>;
+
+ status = "okay";
+};
+
+&venus {
+ firmware-name = "qcom/sc7180/acer/aspire1/qcvss7180.mbn";
+};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&vreg_l9a_0p6>;
+ vdd-1.8-xo-supply = <&vreg_l1c_1p8>;
+ vdd-1.3-rfa-supply = <&vreg_l2c_1p3>;
+ vdd-3.3-ch0-supply = <&vreg_l10c_3p3>;
+ vdd-3.3-ch1-supply = <&vreg_l11c_3p3>;
+
+ status = "okay";
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm6150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vreg_s1a_1p1: smps1 {
+ regulator-min-microvolt = <1128000>;
+ regulator-max-microvolt = <1128000>;
+ };
+
+ vreg_l4a_0p8: ldo4 {
+ regulator-min-microvolt = <824000>;
+ regulator-max-microvolt = <928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9a_0p6: ldo9 {
+ regulator-min-microvolt = <488000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10a_1p8: ldo10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vreg_l11a_1p8: ldo11 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13a_1p8: ldo13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15a_1p8: ldo15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16a_2p7: ldo16 {
+ regulator-min-microvolt = <2496000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17a_3p0: ldo17 {
+ regulator-min-microvolt = <2920000>;
+ regulator-max-microvolt = <3232000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18a_2p8: ldo18 {
+ regulator-min-microvolt = <2496000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l19a_2p9: ldo19 {
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm6150l-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vreg_s8c_1p3: smps8 {
+ regulator-min-microvolt = <1120000>;
+ regulator-max-microvolt = <1408000>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-min-microvolt = <1616000>;
+ regulator-max-microvolt = <1984000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_1p3: ldo2 {
+ regulator-min-microvolt = <1168000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_1p2: ldo3 {
+ regulator-min-microvolt = <1144000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c_1p8: ldo4 {
+ regulator-min-microvolt = <1648000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l5c_1p8: ldo5 {
+ regulator-min-microvolt = <1648000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l6c_2p9: ldo6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7c_3p0: ldo7 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p9: ldo9 {
+ regulator-min-microvolt = <2952000>;
+ regulator-max-microvolt = <2952000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10c_3p3: ldo10 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_3p3: ldo11 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob: bob {
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+};
+
+&qup_i2c2_default {
+ drive-strength = <2>;
+
+ /* Has external pullup */
+ bias-disable;
+};
+
+&qup_i2c4_default {
+ drive-strength = <2>;
+
+ /* Has external pullup */
+ bias-disable;
+};
+
+&qup_i2c9_default {
+ drive-strength = <2>;
+
+ /* Has external pullup */
+ bias-disable;
+};
+
+&qup_i2c10_default {
+ drive-strength = <2>;
+
+ /* Has external pullup */
+ bias-disable;
+};
+
+&tlmm {
+ /*
+ * The TZ seem to protect those because some boards can have
+ * fingerprint sensor connected to this range. Not connected
+ * on this board
+ */
+ gpio-reserved-ranges = <58 5>;
+
+ amp_sd_mode_default: amp-sd-mode-deault-state {
+ pins = "gpio23";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ bridge_en_default: bridge-en-default-state {
+ pins = "gpio51";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ bridge_suspend_default: bridge-suspend-default-state {
+ pins = "gpio22";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ codec_irq_default: codec-irq-deault-state {
+ pins = "gpio28";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ edp_bridge_irq_default: edp-bridge-irq-default-state {
+ pins = "gpio11";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ hid_keyboard_default: hid-keyboard-default-state {
+ pins = "gpio33";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ hid_touchpad_default: hid-touchpad-default-state {
+ pins = "gpio94";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart3_sleep: qup-uart3-sleep-state {
+ cts-pins {
+ /*
+ * Configure a pull-down on CTS to match the pull of
+ * the Bluetooth module.
+ */
+ pins = "gpio38";
+ function = "gpio";
+ bias-pull-down;
+ };
+
+ rts-pins {
+ /*
+ * Configure pull-down on RTS. As RTS is active low
+ * signal, pull it low to indicate the BT SoC that it
+ * can wakeup the system anytime from suspend state by
+ * pulling RX low (by sending wakeup bytes).
+ */
+ pins = "gpio39";
+ function = "gpio";
+ bias-pull-down;
+ };
+
+ tx-pins {
+ /*
+ * Configure pull-up on TX when it isn't actively driven
+ * to prevent BT SoC from receiving garbage during sleep.
+ */
+ pins = "gpio40";
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ rx-pins {
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module
+ * is floating which may cause spurious wakeups.
+ */
+ pins = "gpio41";
+ function = "gpio";
+ bias-pull-up;
+ };
+ };
+
+ reg_edp_1p2_en_default: reg-edp-1p2-en-deault-state {
+ pins = "gpio19";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ reg_edp_1p8_en_default: reg-edp-1p8-en-deault-state {
+ pins = "gpio20";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ reg_lcm_en_default: reg-lcm-en-deault-state {
+ pins = "gpio26";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ reg_audio_en_default: reg-audio-en-deault-state {
+ pins = "gpio83";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ reg_tp_en_default: reg-tp-en-deault-state {
+ pins = "gpio25";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ soc_bkoff_default: soc-bkoff-deault-state {
+ pins = "gpio10";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ sdc1_default: sdc1-default-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_sleep: sdc1-sleep-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+};
--
2.41.0

14
device/community/linux-postmarketos-qcom-sc7180/0013-arm64-dts-qcom-pm6150-Add-resin-and-rtc-nodes.patch → device/community/linux-postmarketos-qcom-sc7180/0005-arm64-dts-qcom-pm6150-Add-resin-and-rtc-nodes.patch
View file

@ -1,7 +1,7 @@
From 389f71369f7a62199ff0af56ef9a23c1c86570e1 Mon Sep 17 00:00:00 2001
From 18dfe3c57801796fb6ca2a17f63893e48298eaa4 Mon Sep 17 00:00:00 2001
From: David Wronek <davidwronek@gmail.com>
Date: Thu, 24 Aug 2023 11:15:05 +0200
Subject: [PATCH 13/17] arm64: dts: qcom: pm6150: Add resin and rtc nodes
Subject: [PATCH 5/8] arm64: dts: qcom: pm6150: Add resin and rtc nodes
Add support for the RTC which is the same as on other PMICs and add the
resin child node to the PM6150 PON device, both disabled by default.
@ -16,10 +16,10 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi
index 8a4972e6a24c..d1dccfdfb3cd 100644
index 7d4d1f2767ed..ddbaf7280b03 100644
--- a/arch/arm64/boot/dts/qcom/pm6150.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi
@@ -51,6 +51,14 @@ pm6150_pwrkey: pwrkey {
@@ -53,6 +53,14 @@ pm6150_pwrkey: pwrkey {
bias-pull-up;
linux,code = <KEY_POWER>;
};
@ -34,7 +34,7 @@ index 8a4972e6a24c..d1dccfdfb3cd 100644
};
pm6150_temp: temp-alarm@2400 {
@@ -86,6 +94,14 @@ pm6150_adc_tm: adc-tm@3500 {
@@ -88,6 +96,14 @@ pm6150_adc_tm: adc-tm@3500 {
status = "disabled";
};
@ -46,9 +46,9 @@ index 8a4972e6a24c..d1dccfdfb3cd 100644
+ status = "disabled";
+ };
+
pm6150_gpio: gpios@c000 {
pm6150_gpios: gpio@c000 {
compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
--
2.43.0
2.43.2

10
device/community/linux-postmarketos-qcom-sc7180/0014-arm64-dts-qcom-acer-aspire1-Enable-RTC.patch → device/community/linux-postmarketos-qcom-sc7180/0006-arm64-dts-qcom-acer-aspire1-Enable-RTC.patch
View file

@ -1,7 +1,7 @@
From f6bbe959dd47e534f2a006561be68cfb1bbf27c4 Mon Sep 17 00:00:00 2001
From 2384f0140ed50ef2ee57fd575e69dc91fe13652b Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Tue, 5 Dec 2023 16:48:10 +0500
Subject: [PATCH 14/17] arm64: dts: qcom: acer-aspire1: Enable RTC
Subject: [PATCH 6/8] arm64: dts: qcom: acer-aspire1: Enable RTC
pm6150 has a read-only RTC that can be used to keep the time with some
extra userspace tools. Enable it.
@ -15,10 +15,10 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
index 2a80f4090085..ab8ec7958584 100644
index 3342cb048038..00b442696618 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
@@ -349,6 +349,10 @@ &pm6150_pon {
@@ -364,6 +364,10 @@ &pm6150_pon {
status = "disabled";
};
@ -30,5 +30,5 @@ index 2a80f4090085..ab8ec7958584 100644
status = "okay";
};
--
2.43.0
2.43.2

36
device/community/linux-postmarketos-qcom-sc7180/0006-media-venus-core-Set-up-secure-memory-ranges-for-SC7.patch
View file

@ -1,36 +0,0 @@
From 720541f67f730e31c7b19b21b6c7eb92bfd9b6c2 Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Fri, 16 Jun 2023 01:36:58 +0200
Subject: [PATCH 06/17] media: venus: core: Set up secure memory ranges for
SC7180
Not all SC7180 devices ship with ChromeOS firmware. WoA devices use
Android-like TZ, which uses PAS for image authentication. That requires
the predefined virtual address ranges to be passed via scm calls.
Define them to enable Venus on non-CrOS SC7180 devices.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Stanimir Varbanov <stanimir.k.varbanov@gmail.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
---
drivers/media/platform/qcom/venus/core.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platform/qcom/venus/core.c
index 990a1519f968..1d9e416e5322 100644
--- a/drivers/media/platform/qcom/venus/core.c
+++ b/drivers/media/platform/qcom/venus/core.c
@@ -762,6 +762,10 @@ static const struct venus_resources sc7180_res = {
.vmem_size = 0,
.vmem_addr = 0,
.dma_mask = 0xe0000000 - 1,
+ .cp_start = 0,
+ .cp_size = 0x70800000,
+ .cp_nonpixel_start = 0x1000000,
+ .cp_nonpixel_size = 0x24800000,
.fwname = "qcom/venus-5.4/venus.mdt",
};
--
2.43.0

12
device/community/linux-postmarketos-qcom-sc7180/0016-arm64-dts-qcom-acer-aspire1-Add-sound.patch → device/community/linux-postmarketos-qcom-sc7180/0007-arm64-dts-qcom-acer-aspire1-Add-sound.patch
View file

@ -1,7 +1,7 @@
From d081eaf8adc96ae9ba68ffe3f69f3057ead4bc63 Mon Sep 17 00:00:00 2001
From bf688cd32b158a962bbce6103b3f43dda5d80a5a Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Tue, 5 Dec 2023 16:48:12 +0500
Subject: [PATCH 16/17] arm64: dts: qcom: acer-aspire1: Add sound
Subject: [PATCH 7/8] arm64: dts: qcom: acer-aspire1: Add sound
This laptop has two i2s speakers; an i2s audio codec for the headset
jack; two DMIC microphones in the lid and the displayport audio channel.
@ -23,7 +23,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
1 file changed, 153 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
index 7bde69f39c8a..58f694d8e762 100644
index 00b442696618..5afcb8212f49 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
@@ -3,6 +3,7 @@
@ -148,7 +148,7 @@ index 7bde69f39c8a..58f694d8e762 100644
reg_tp_3p3: touchpad-regulator {
compatible = "regulator-fixed";
regulator-name = "tp_3p3";
@@ -366,6 +474,45 @@ &pm6150_rtc {
@@ -368,6 +476,45 @@ &pm6150_rtc {
status = "okay";
};
@ -194,7 +194,7 @@ index 7bde69f39c8a..58f694d8e762 100644
&qupv3_id_0 {
status = "okay";
};
@@ -374,6 +521,12 @@ &qupv3_id_1 {
@@ -376,6 +523,12 @@ &qupv3_id_1 {
status = "okay";
};
@ -208,5 +208,5 @@ index 7bde69f39c8a..58f694d8e762 100644
firmware-name = "qcom/sc7180/acer/aspire1/qcmpss7180_nm.mbn";
status = "okay";
--
2.43.0
2.43.2

387
device/community/linux-postmarketos-qcom-sc7180/0007-arm64-dts-qcom-sc7180-Split-up-TF-A-related-PSCI-con.patch
View file

@ -1,387 +0,0 @@
From 0fed0e8058be5fdf261092e6b42f0f8ef3c37040 Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Tue, 8 Aug 2023 15:10:13 +0500
Subject: [PATCH 07/17] arm64: dts: qcom: sc7180: Split up TF-A related PSCI
configuration
When initially submitted, the sc7180 support only targeted CROS devices
that make use of alternative TF-A firmware and not the official Qualcomm
firmware. The PSCI implementations in those firmwares differ however so
devices that use qcom firmware, like WoA laptops such as aspire1 need
different setup.
This commit adjusts the SoC dtsi to the OSI mode PSCI setup, common to
the Qualcomm firmware and introduces new sc7180-firmware-tfa.dtsi that
overrides the PSCI setup for the PC mode and uses TF-A specific
psci-suspend-param. This dtsi is added to all boards that appear to use
TF-A.
Link: https://lore.kernel.org/r/20230808-sc7180-tfa-fw-v1-1-666d5d8467e5@trvn.ru
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
---
.../boot/dts/qcom/sc7180-firmware-tfa.dtsi | 107 +++++++++++++++
arch/arm64/boot/dts/qcom/sc7180-idp.dts | 1 +
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 +
arch/arm64/boot/dts/qcom/sc7180.dtsi | 127 +++++++++++++-----
4 files changed, 206 insertions(+), 30 deletions(-)
create mode 100644 arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi b/arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi
new file mode 100644
index 000000000000..ee35a454dbf6
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Devices that use SC7180 with TrustedFirmware-A
+ * need PSCI PC mode instead of the OSI mode provided
+ * by Qualcomm firmware.
+ */
+
+&CPU0 {
+ /delete-property/ power-domains;
+ /delete-property/ power-domain-names;
+
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
+};
+
+&CPU1 {
+ /delete-property/ power-domains;
+ /delete-property/ power-domain-names;
+
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
+};
+
+&CPU2 {
+ /delete-property/ power-domains;
+ /delete-property/ power-domain-names;
+
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
+};
+
+&CPU3 {
+ /delete-property/ power-domains;
+ /delete-property/ power-domain-names;
+
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
+};
+
+&CPU4 {
+ /delete-property/ power-domains;
+ /delete-property/ power-domain-names;
+
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
+};
+
+&CPU5 {
+ /delete-property/ power-domains;
+ /delete-property/ power-domain-names;
+
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
+};
+
+&CPU6 {
+ /delete-property/ power-domains;
+ /delete-property/ power-domain-names;
+
+ cpu-idle-states = <&BIG_CPU_SLEEP_0
+ &BIG_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
+};
+
+&CPU7 {
+ /delete-property/ power-domains;
+ /delete-property/ power-domain-names;
+
+ cpu-idle-states = <&BIG_CPU_SLEEP_0
+ &BIG_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
+};
+
+/delete-node/ &domain_idle_states;
+
+&idle_states {
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "cluster-power-down";
+ arm,psci-suspend-param = <0x40003444>;
+ entry-latency-us = <3263>;
+ exit-latency-us = <6562>;
+ min-residency-us = <9926>;
+ local-timer-stop;
+ };
+};
+
+/delete-node/ &CPU_PD0;
+/delete-node/ &CPU_PD1;
+/delete-node/ &CPU_PD2;
+/delete-node/ &CPU_PD3;
+/delete-node/ &CPU_PD4;
+/delete-node/ &CPU_PD5;
+/delete-node/ &CPU_PD6;
+/delete-node/ &CPU_PD7;
+/delete-node/ &CLUSTER_PD;
+
+&apps_rsc {
+ /delete-property/ power-domains;
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index d3c4b5804a69..c224fc93f1ee 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -11,6 +11,7 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include "sc7180.dtsi"
+#include "sc7180-firmware-tfa.dtsi"
#include "pm6150.dtsi"
#include "pm6150l.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index f4db4ccf48e5..38d327fa1394 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/sound/sc7180-lpass.h>
#include "sc7180.dtsi"
+#include "sc7180-firmware-tfa.dtsi"
/* PMICs depend on spmi_bus label and so must come after sc7180.dtsi */
#include "pm6150.dtsi"
#include "pm6150l.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 19f39a5b3b56..64ae9f27ba80 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -133,9 +133,8 @@ CPU0: cpu@0 {
compatible = "qcom,kryo468";
reg = <0x0 0x0>;
enable-method = "psci";
- cpu-idle-states = <&LITTLE_CPU_SLEEP_0
- &LITTLE_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
operating-points-v2 = <&cpu0_opp_table>;
@@ -158,9 +157,8 @@ CPU1: cpu@100 {
compatible = "qcom,kryo468";
reg = <0x0 0x100>;
enable-method = "psci";
- cpu-idle-states = <&LITTLE_CPU_SLEEP_0
- &LITTLE_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ power-domains = <&CPU_PD1>;
+ power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_100>;
@@ -180,9 +178,8 @@ CPU2: cpu@200 {
compatible = "qcom,kryo468";
reg = <0x0 0x200>;
enable-method = "psci";
- cpu-idle-states = <&LITTLE_CPU_SLEEP_0
- &LITTLE_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ power-domains = <&CPU_PD2>;
+ power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_200>;
@@ -202,9 +199,8 @@ CPU3: cpu@300 {
compatible = "qcom,kryo468";
reg = <0x0 0x300>;
enable-method = "psci";
- cpu-idle-states = <&LITTLE_CPU_SLEEP_0
- &LITTLE_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ power-domains = <&CPU_PD3>;
+ power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_300>;
@@ -224,9 +220,8 @@ CPU4: cpu@400 {
compatible = "qcom,kryo468";
reg = <0x0 0x400>;
enable-method = "psci";
- cpu-idle-states = <&LITTLE_CPU_SLEEP_0
- &LITTLE_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ power-domains = <&CPU_PD4>;
+ power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_400>;
@@ -246,9 +241,8 @@ CPU5: cpu@500 {
compatible = "qcom,kryo468";
reg = <0x0 0x500>;
enable-method = "psci";
- cpu-idle-states = <&LITTLE_CPU_SLEEP_0
- &LITTLE_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ power-domains = <&CPU_PD5>;
+ power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_500>;
@@ -268,9 +262,8 @@ CPU6: cpu@600 {
compatible = "qcom,kryo468";
reg = <0x0 0x600>;
enable-method = "psci";
- cpu-idle-states = <&BIG_CPU_SLEEP_0
- &BIG_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ power-domains = <&CPU_PD6>;
+ power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <480>;
next-level-cache = <&L2_600>;
@@ -290,9 +283,8 @@ CPU7: cpu@700 {
compatible = "qcom,kryo468";
reg = <0x0 0x700>;
enable-method = "psci";
- cpu-idle-states = <&BIG_CPU_SLEEP_0
- &BIG_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ power-domains = <&CPU_PD7>;
+ power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <480>;
next-level-cache = <&L2_700>;
@@ -343,7 +335,7 @@ core7 {
};
};
- idle-states {
+ idle_states: idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
@@ -385,15 +377,34 @@ BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
min-residency-us = <5555>;
local-timer-stop;
};
+ };
- CLUSTER_SLEEP_0: cluster-sleep-0 {
- compatible = "arm,idle-state";
+ domain_idle_states: domain-idle-states {
+ CLUSTER_SLEEP_PC: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ idle-state-name = "cluster-l3-power-collapse";
+ arm,psci-suspend-param = <0x41000044>;
+ entry-latency-us = <2752>;
+ exit-latency-us = <3048>;
+ min-residency-us = <6118>;
+ };
+
+ CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
+ compatible = "domain-idle-state";
+ idle-state-name = "cluster-cx-retention";
+ arm,psci-suspend-param = <0x41001244>;
+ entry-latency-us = <3638>;
+ exit-latency-us = <4562>;
+ min-residency-us = <8467>;
+ };
+
+ CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
+ compatible = "domain-idle-state";
idle-state-name = "cluster-power-down";
- arm,psci-suspend-param = <0x40003444>;
+ arm,psci-suspend-param = <0x4100b244>;
entry-latency-us = <3263>;
exit-latency-us = <6562>;
- min-residency-us = <9926>;
- local-timer-stop;
+ min-residency-us = <9826>;
};
};
};
@@ -643,6 +654,61 @@ ipa_smp2p_in: ipa-modem-to-ap {
psci {
compatible = "arm,psci-1.0";
method = "smc";
+
+ CPU_PD0: cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+ };
+
+ CPU_PD1: cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+ };
+
+ CPU_PD2: cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+ };
+
+ CPU_PD3: cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+ };
+
+ CPU_PD4: cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+ };
+
+ CPU_PD5: cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+ };
+
+ CPU_PD6: cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
+ };
+
+ CPU_PD7: cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
+ };
+
+ CLUSTER_PD: cpu-cluster0 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_SLEEP_PC
+ &CLUSTER_SLEEP_CX_RET
+ &CLUSTER_AOSS_SLEEP>;
+ };
};
soc: soc@0 {
@@ -3452,6 +3518,7 @@ apps_rsc: rsc@18200000 {
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
+ power-domains = <&CLUSTER_PD>;
rpmhcc: clock-controller {
compatible = "qcom,sc7180-rpmh-clk";
--
2.43.0

116
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@ -0,0 +1,116 @@
From 5da7f1f071d5d0db4978e946263ab783657d0d57 Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Sat, 2 Mar 2024 14:37:30 +0500
Subject: [PATCH 08/11] platform: Add ARM64 platform directory
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Some ARM64 based laptops and computers require vendor/board specific
drivers for their embedded controllers. Even though usually the most
important functionality of those devices is implemented inside ACPI,
unfortunately Linux doesn't currently have great support for ACPI on
platforms like Qualcomm Snapdragon that are used in most ARM64 laptops
today. Instead Linux relies on Device Tree for Qualcomm based devices
and it's significantly easier to reimplement the EC functionality in
a dedicated driver than to make use of ACPI code.
This commit introduces a new platform/arm64 subdirectory to give a
place to such drivers for EC-like devices.
A new MAINTAINERS entry is added for this directory. Patches to files in
this directory will be taken up by the platform-drivers-x86 team (i.e.
Hans de Goede and Ilpo Järvinen) with additional review from Bryan
O'Donoghue to represent ARM64 maintainers.
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
---
MAINTAINERS | 10 ++++++++++
drivers/platform/Kconfig | 2 ++
drivers/platform/Makefile | 1 +
drivers/platform/arm64/Kconfig | 19 +++++++++++++++++++
drivers/platform/arm64/Makefile | 6 ++++++
5 files changed, 38 insertions(+)
create mode 100644 drivers/platform/arm64/Kconfig
create mode 100644 drivers/platform/arm64/Makefile
diff --git a/MAINTAINERS b/MAINTAINERS
index 40312bb550f0..396be95d4f9a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3007,6 +3007,16 @@ F: drivers/mmc/host/sdhci-of-arasan.c
N: zynq
N: xilinx
+ARM64 PLATFORM DRIVERS
+M: Hans de Goede <hdegoede@redhat.com>
+M: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
+R: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+L: platform-driver-x86@vger.kernel.org
+S: Maintained
+Q: https://patchwork.kernel.org/project/platform-driver-x86/list/
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git
+F: drivers/platform/arm64/
+
ARM64 PORT (AARCH64 ARCHITECTURE)
M: Catalin Marinas <catalin.marinas@arm.com>
M: Will Deacon <will@kernel.org>
diff --git a/drivers/platform/Kconfig b/drivers/platform/Kconfig
index 868b20361769..81a298517df2 100644
--- a/drivers/platform/Kconfig
+++ b/drivers/platform/Kconfig
@@ -14,3 +14,5 @@ source "drivers/platform/olpc/Kconfig"
source "drivers/platform/surface/Kconfig"
source "drivers/platform/x86/Kconfig"
+
+source "drivers/platform/arm64/Kconfig"
diff --git a/drivers/platform/Makefile b/drivers/platform/Makefile
index 41640172975a..fbbe4f77aa5d 100644
--- a/drivers/platform/Makefile
+++ b/drivers/platform/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_OLPC_EC) += olpc/
obj-$(CONFIG_GOLDFISH) += goldfish/
obj-$(CONFIG_CHROME_PLATFORMS) += chrome/
obj-$(CONFIG_SURFACE_PLATFORMS) += surface/
+obj-$(CONFIG_ARM64) += arm64/
diff --git a/drivers/platform/arm64/Kconfig b/drivers/platform/arm64/Kconfig
new file mode 100644
index 000000000000..644b83ede093
--- /dev/null
+++ b/drivers/platform/arm64/Kconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# EC-like Drivers for aarch64 based devices.
+#
+
+menuconfig ARM64_PLATFORM_DEVICES
+ bool "ARM64 Platform-Specific Device Drivers"
+ depends on ARM64 || COMPILE_TEST
+ default y
+ help
+ Say Y here to get to see options for platform-specific device drivers
+ for arm64 based devices, primarily EC-like device drivers.
+ This option alone does not add any kernel code.
+
+ If you say N, all options in this submenu will be skipped and disabled.
+
+if ARM64_PLATFORM_DEVICES
+
+endif # ARM64_PLATFORM_DEVICES
diff --git a/drivers/platform/arm64/Makefile b/drivers/platform/arm64/Makefile
new file mode 100644
index 000000000000..f91cdc7155e2
--- /dev/null
+++ b/drivers/platform/arm64/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Makefile for linux/drivers/platform/arm64
+#
+# This dir should only include drivers for EC-like devices.
+#
--
2.44.0

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device/community/linux-postmarketos-qcom-sc7180/0009-platform-arm64-Add-Acer-Aspire-1-embedded-controller.patch Normal file
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@ -0,0 +1,652 @@
From 309a0174fb1000b308271bd0009d1cfba263f939 Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Sat, 9 Jul 2022 00:39:42 +0500
Subject: [PATCH 09/11] platform: arm64: Add Acer Aspire 1 embedded controller
driver
Acer Aspire 1 is a Snapdragon 7c based laptop. It uses an embedded
controller to perform a set of various functions, such as:
- Battery and charger monitoring;
- Keyboard layout control (i.e. fn_lock settings);
- USB Type-C DP alt mode HPD notifications;
- Laptop lid status.
Unfortunately, while all this functionality is implemented in ACPI, it's
currently not possible to use ACPI to boot Linux on such Qualcomm
devices. To allow Linux to still support the features provided by EC,
this driver reimplments the relevant ACPI parts. This allows us to boot
the laptop with Device Tree and retain all the features.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
---
MAINTAINERS | 6 +
drivers/platform/arm64/Kconfig | 16 +
drivers/platform/arm64/Makefile | 2 +
drivers/platform/arm64/acer-aspire1-ec.c | 561 +++++++++++++++++++++++
4 files changed, 585 insertions(+)
create mode 100644 drivers/platform/arm64/acer-aspire1-ec.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 396be95d4f9a..bc5620bfbb32 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -261,6 +261,12 @@ L: linux-acenic@sunsite.dk
S: Maintained
F: drivers/net/ethernet/alteon/acenic*
+ACER ASPIRE 1 EMBEDDED CONTROLLER DRIVER
+M: Nikita Travkin <nikita@trvn.ru>
+S: Maintained
+F: Documentation/devicetree/bindings/platform/acer,aspire1-ec.yaml
+F: drivers/platform/arm64/acer-aspire1-ec.c
+
ACER ASPIRE ONE TEMPERATURE AND FAN DRIVER
M: Peter Kaestle <peter@piie.net>
L: platform-driver-x86@vger.kernel.org
diff --git a/drivers/platform/arm64/Kconfig b/drivers/platform/arm64/Kconfig
index 644b83ede093..07d47879a9e3 100644
--- a/drivers/platform/arm64/Kconfig
+++ b/drivers/platform/arm64/Kconfig
@@ -16,4 +16,20 @@ menuconfig ARM64_PLATFORM_DEVICES
if ARM64_PLATFORM_DEVICES
+config EC_ACER_ASPIRE1
+ tristate "Acer Aspire 1 Emedded Controller driver"
+ depends on I2C
+ depends on DRM
+ depends on POWER_SUPPLY
+ depends on INPUT
+ help
+ Say Y here to enable the EC driver for the (Snapdragon-based)
+ Acer Aspire 1 laptop. The EC handles battery and charging
+ monitoring as well as some misc functions like the lid sensor
+ and USB Type-C DP HPD events.
+
+ This driver provides battery and AC status support for the mentioned
+ laptop where this information is not properly exposed via the
+ standard ACPI devices.
+
endif # ARM64_PLATFORM_DEVICES
diff --git a/drivers/platform/arm64/Makefile b/drivers/platform/arm64/Makefile
index f91cdc7155e2..4fcc9855579b 100644
--- a/drivers/platform/arm64/Makefile
+++ b/drivers/platform/arm64/Makefile
@@ -4,3 +4,5 @@
#
# This dir should only include drivers for EC-like devices.
#
+
+obj-$(CONFIG_EC_ACER_ASPIRE1) += acer-aspire1-ec.o
diff --git a/drivers/platform/arm64/acer-aspire1-ec.c b/drivers/platform/arm64/acer-aspire1-ec.c
new file mode 100644
index 000000000000..75a7c2821771
--- /dev/null
+++ b/drivers/platform/arm64/acer-aspire1-ec.c
@@ -0,0 +1,561 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2024, Nikita Travkin <nikita@trvn.ru> */
+
+#include <asm-generic/unaligned.h>
+#include <drm/drm_bridge.h>
+#include <linux/bits.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/power_supply.h>
+#include <linux/usb/typec_mux.h>
+
+#define MILLI_TO_MICRO 1000
+
+#define ASPIRE_EC_EVENT 0x05
+
+#define ASPIRE_EC_EVENT_WATCHDOG 0x20
+#define ASPIRE_EC_EVENT_KBD_BKL_ON 0x57
+#define ASPIRE_EC_EVENT_KBD_BKL_OFF 0x58
+#define ASPIRE_EC_EVENT_LID_CLOSE 0x9b
+#define ASPIRE_EC_EVENT_LID_OPEN 0x9c
+#define ASPIRE_EC_EVENT_BKL_UNBLANKED 0x9d
+#define ASPIRE_EC_EVENT_BKL_BLANKED 0x9e
+#define ASPIRE_EC_EVENT_FG_INF_CHG 0x85
+#define ASPIRE_EC_EVENT_FG_STA_CHG 0xc6
+#define ASPIRE_EC_EVENT_HPD_DIS 0xa3
+#define ASPIRE_EC_EVENT_HPD_CON 0xa4
+
+#define ASPIRE_EC_FG_DYNAMIC 0x07
+#define ASPIRE_EC_FG_STATIC 0x08
+
+#define ASPIRE_EC_FG_FLAG_PRESENT BIT(0)
+#define ASPIRE_EC_FG_FLAG_FULL BIT(1)
+#define ASPIRE_EC_FG_FLAG_DISCHARGING BIT(2)
+#define ASPIRE_EC_FG_FLAG_CHARGING BIT(3)
+
+#define ASPIRE_EC_RAM_READ 0x20
+#define ASPIRE_EC_RAM_WRITE 0x21
+
+#define ASPIRE_EC_RAM_WATCHDOG 0x19
+#define ASPIRE_EC_WATCHDOG_BIT BIT(6)
+
+#define ASPIRE_EC_RAM_KBD_MODE 0x43
+
+#define ASPIRE_EC_RAM_KBD_FN_EN BIT(0)
+#define ASPIRE_EC_RAM_KBD_MEDIA_ON_TOP BIT(5)
+#define ASPIRE_EC_RAM_KBD_ALWAYS_SET BIT(6)
+#define ASPIRE_EC_RAM_KBD_NUM_LAYER_EN BIT(7)
+
+#define ASPIRE_EC_RAM_KBD_MODE_2 0x60
+
+#define ASPIRE_EC_RAM_KBD_MEDIA_NOTIFY BIT(3)
+
+#define ASPIRE_EC_RAM_HPD_STATUS 0xf4
+#define ASPIRE_EC_HPD_CONNECTED 0x03
+
+#define ASPIRE_EC_RAM_LID_STATUS 0x4c
+#define ASPIRE_EC_LID_OPEN BIT(6)
+
+#define ASPIRE_EC_RAM_ADP 0x40
+#define ASPIRE_EC_AC_STATUS BIT(0)
+
+struct aspire_ec {
+ struct i2c_client *client;
+ struct power_supply *bat_psy;
+ struct power_supply *adp_psy;
+ struct input_dev *idev;
+
+ bool bridge_configured;
+ struct drm_bridge bridge;
+ struct work_struct work;
+};
+
+static int aspire_ec_ram_read(struct i2c_client *client, u8 off, u8 *data, u8 data_len)
+{
+ i2c_smbus_write_byte_data(client, ASPIRE_EC_RAM_READ, off);
+ i2c_smbus_read_i2c_block_data(client, ASPIRE_EC_RAM_READ, data_len, data);
+ return 0;
+}
+
+static int aspire_ec_ram_write(struct i2c_client *client, u8 off, u8 data)
+{
+ u8 tmp[2] = {off, data};
+
+ i2c_smbus_write_i2c_block_data(client, ASPIRE_EC_RAM_WRITE, sizeof(tmp), tmp);
+ return 0;
+}
+
+static irqreturn_t aspire_ec_irq_handler(int irq, void *data)
+{
+ struct aspire_ec *ec = data;
+ int id;
+ u8 tmp;
+
+ /*
+ * The original ACPI firmware actually has a small sleep in the handler.
+ *
+ * It seems like in most cases it's not needed but when the device
+ * just exits suspend, our i2c driver has a brief time where data
+ * transfer is not possible yet. So this delay allows us to suppress
+ * quite a bunch of spurious error messages in dmesg. Thus it's kept.
+ */
+ usleep_range(15000, 30000);
+
+ id = i2c_smbus_read_byte_data(ec->client, ASPIRE_EC_EVENT);
+ if (id < 0) {
+ dev_err(&ec->client->dev, "Failed to read event id: %pe\n", ERR_PTR(id));
+ return IRQ_HANDLED;
+ }
+
+ switch (id) {
+ case 0x0: /* No event */
+ break;
+
+ case ASPIRE_EC_EVENT_WATCHDOG:
+ /*
+ * Here acpi responds to the event and clears some bit.
+ * Notify (\_SB.I2C3.BAT1, 0x81) // Information Change
+ * Notify (\_SB.I2C3.ADP1, 0x80) // Status Change
+ */
+ aspire_ec_ram_read(ec->client, ASPIRE_EC_RAM_WATCHDOG, &tmp, sizeof(tmp));
+ tmp &= ~ASPIRE_EC_WATCHDOG_BIT;
+ aspire_ec_ram_write(ec->client, ASPIRE_EC_RAM_WATCHDOG, tmp);
+ break;
+
+ case ASPIRE_EC_EVENT_LID_CLOSE:
+ /* Notify (\_SB.LID0, 0x80) // Status Change */
+ input_report_switch(ec->idev, SW_LID, 1);
+ input_sync(ec->idev);
+ break;
+
+ case ASPIRE_EC_EVENT_LID_OPEN:
+ /* Notify (\_SB.LID0, 0x80) // Status Change */
+ input_report_switch(ec->idev, SW_LID, 0);
+ input_sync(ec->idev);
+ break;
+
+ case ASPIRE_EC_EVENT_FG_INF_CHG:
+ /* Notify (\_SB.I2C3.BAT1, 0x81) // Information Change */
+ fallthrough;
+ case ASPIRE_EC_EVENT_FG_STA_CHG:
+ /* Notify (\_SB.I2C3.BAT1, 0x80) // Status Change */
+ power_supply_changed(ec->bat_psy);
+ power_supply_changed(ec->adp_psy);
+ break;
+
+ case ASPIRE_EC_EVENT_HPD_DIS:
+ if (ec->bridge_configured)
+ drm_bridge_hpd_notify(&ec->bridge, connector_status_disconnected);
+ break;
+
+ case ASPIRE_EC_EVENT_HPD_CON:
+ if (ec->bridge_configured)
+ drm_bridge_hpd_notify(&ec->bridge, connector_status_connected);
+ break;
+
+ case ASPIRE_EC_EVENT_BKL_BLANKED:
+ case ASPIRE_EC_EVENT_BKL_UNBLANKED:
+ /* Display backlight blanked on FN+F6. No action needed. */
+ break;
+
+ case ASPIRE_EC_EVENT_KBD_BKL_ON:
+ case ASPIRE_EC_EVENT_KBD_BKL_OFF:
+ /*
+ * There is a keyboard backlight connector on Aspire 1 that is
+ * controlled by FN+F8. There is no kb backlight on the device though.
+ * Seems like this is used on other devices like Acer Spin 7.
+ * No action needed.
+ */
+ break;
+
+ default:
+ dev_warn(&ec->client->dev, "Unknown event id=0x%x\n", id);
+ }
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * Power supply.
+ */
+
+struct aspire_ec_bat_psy_static_data {
+ u8 unk1;
+ u8 flags;
+ __le16 unk2;
+ __le16 voltage_design;
+ __le16 capacity_full;
+ __le16 unk3;
+ __le16 serial;
+ u8 model_id;
+ u8 vendor_id;
+} __packed;
+
+static const char * const aspire_ec_bat_psy_battery_model[] = {
+ "AP18C4K",
+ "AP18C8K",
+ "AP19B8K",
+ "AP16M4J",
+ "AP16M5J",
+};
+
+static const char * const aspire_ec_bat_psy_battery_vendor[] = {
+ "SANYO",
+ "SONY",
+ "PANASONIC",
+ "SAMSUNG",
+ "SIMPLO",
+ "MOTOROLA",
+ "CELXPERT",
+ "LGC",
+ "GETAC",
+ "MURATA",
+};
+
+struct aspire_ec_bat_psy_dynamic_data {
+ u8 unk1;
+ u8 flags;
+ u8 unk2;
+ __le16 capacity_now;
+ __le16 voltage_now;
+ __le16 current_now;
+ __le16 unk3;
+ __le16 unk4;
+} __packed;
+
+static int aspire_ec_bat_psy_get_property(struct power_supply *psy,
+ enum power_supply_property psp,
+ union power_supply_propval *val)
+{
+ struct aspire_ec *ec = power_supply_get_drvdata(psy);
+ struct aspire_ec_bat_psy_static_data sdat;
+ struct aspire_ec_bat_psy_dynamic_data ddat;
+ int str_index = 0;
+
+ i2c_smbus_read_i2c_block_data(ec->client, ASPIRE_EC_FG_STATIC, sizeof(sdat), (u8 *)&sdat);
+ i2c_smbus_read_i2c_block_data(ec->client, ASPIRE_EC_FG_DYNAMIC, sizeof(ddat), (u8 *)&ddat);
+
+ switch (psp) {
+ case POWER_SUPPLY_PROP_STATUS:
+ val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
+ if (ddat.flags & ASPIRE_EC_FG_FLAG_CHARGING)
+ val->intval = POWER_SUPPLY_STATUS_CHARGING;
+ else if (ddat.flags & ASPIRE_EC_FG_FLAG_DISCHARGING)
+ val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
+ else if (ddat.flags & ASPIRE_EC_FG_FLAG_FULL)
+ val->intval = POWER_SUPPLY_STATUS_FULL;
+ break;
+
+ case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+ val->intval = get_unaligned_le16(&ddat.voltage_now) * MILLI_TO_MICRO;
+ break;
+
+ case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
+ val->intval = le16_to_cpu(sdat.voltage_design) * MILLI_TO_MICRO;
+ break;
+
+ case POWER_SUPPLY_PROP_CHARGE_NOW:
+ val->intval = get_unaligned_le16(&ddat.capacity_now) * MILLI_TO_MICRO;
+ break;
+
+ case POWER_SUPPLY_PROP_CHARGE_FULL:
+ val->intval = le16_to_cpu(sdat.capacity_full) * MILLI_TO_MICRO;
+ break;
+
+ case POWER_SUPPLY_PROP_CAPACITY:
+ val->intval = get_unaligned_le16(&ddat.capacity_now) * 100;
+ val->intval /= le16_to_cpu(sdat.capacity_full);
+ break;
+
+ case POWER_SUPPLY_PROP_CURRENT_NOW:
+ val->intval = (s16)get_unaligned_le16(&ddat.current_now) * MILLI_TO_MICRO;
+ break;
+
+ case POWER_SUPPLY_PROP_PRESENT:
+ val->intval = !!(ddat.flags & ASPIRE_EC_FG_FLAG_PRESENT);
+ break;
+
+ case POWER_SUPPLY_PROP_SCOPE:
+ val->intval = POWER_SUPPLY_SCOPE_SYSTEM;
+ break;
+
+ case POWER_SUPPLY_PROP_MODEL_NAME:
+ str_index = sdat.model_id - 1;
+
+ if (str_index >= 0 && str_index < ARRAY_SIZE(aspire_ec_bat_psy_battery_model))
+ val->strval = aspire_ec_bat_psy_battery_model[str_index];
+ else
+ val->strval = "Unknown";
+ break;
+
+ case POWER_SUPPLY_PROP_MANUFACTURER:
+ str_index = sdat.vendor_id - 3; /* ACPI uses 3 as an offset here. */
+
+ if (str_index >= 0 && str_index < ARRAY_SIZE(aspire_ec_bat_psy_battery_vendor))
+ val->strval = aspire_ec_bat_psy_battery_vendor[str_index];
+ else
+ val->strval = "Unknown";
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static enum power_supply_property aspire_ec_bat_psy_props[] = {
+ POWER_SUPPLY_PROP_STATUS,
+ POWER_SUPPLY_PROP_VOLTAGE_NOW,
+ POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
+ POWER_SUPPLY_PROP_CHARGE_NOW,
+ POWER_SUPPLY_PROP_CHARGE_FULL,
+ POWER_SUPPLY_PROP_CAPACITY,
+ POWER_SUPPLY_PROP_CURRENT_NOW,
+ POWER_SUPPLY_PROP_PRESENT,
+ POWER_SUPPLY_PROP_SCOPE,
+ POWER_SUPPLY_PROP_MODEL_NAME,
+ POWER_SUPPLY_PROP_MANUFACTURER,
+};
+
+static const struct power_supply_desc aspire_ec_bat_psy_desc = {
+ .name = "aspire-ec-bat",
+ .type = POWER_SUPPLY_TYPE_BATTERY,
+ .get_property = aspire_ec_bat_psy_get_property,
+ .properties = aspire_ec_bat_psy_props,
+ .num_properties = ARRAY_SIZE(aspire_ec_bat_psy_props),
+};
+
+static int aspire_ec_adp_psy_get_property(struct power_supply *psy,
+ enum power_supply_property psp,
+ union power_supply_propval *val)
+{
+ struct aspire_ec *ec = power_supply_get_drvdata(psy);
+ u8 tmp;
+
+ switch (psp) {
+ case POWER_SUPPLY_PROP_ONLINE:
+ aspire_ec_ram_read(ec->client, ASPIRE_EC_RAM_ADP, &tmp, sizeof(tmp));
+ val->intval = !!(tmp & ASPIRE_EC_AC_STATUS);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static enum power_supply_property aspire_ec_adp_psy_props[] = {
+ POWER_SUPPLY_PROP_ONLINE,
+};
+
+static const struct power_supply_desc aspire_ec_adp_psy_desc = {
+ .name = "aspire-ec-adp",
+ .type = POWER_SUPPLY_TYPE_MAINS,
+ .get_property = aspire_ec_adp_psy_get_property,
+ .properties = aspire_ec_adp_psy_props,
+ .num_properties = ARRAY_SIZE(aspire_ec_adp_psy_props),
+};
+
+/*
+ * USB-C DP Alt mode HPD.
+ */
+
+static int aspire_ec_bridge_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags)
+{
+ return flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR ? 0 : -EINVAL;
+}
+
+static void aspire_ec_bridge_update_hpd_work(struct work_struct *work)
+{
+ struct aspire_ec *ec = container_of(work, struct aspire_ec, work);
+ u8 tmp;
+
+ aspire_ec_ram_read(ec->client, ASPIRE_EC_RAM_HPD_STATUS, &tmp, sizeof(tmp));
+ if (tmp == ASPIRE_EC_HPD_CONNECTED)
+ drm_bridge_hpd_notify(&ec->bridge, connector_status_connected);
+ else
+ drm_bridge_hpd_notify(&ec->bridge, connector_status_disconnected);
+}
+
+static void aspire_ec_bridge_hpd_enable(struct drm_bridge *bridge)
+{
+ struct aspire_ec *ec = container_of(bridge, struct aspire_ec, bridge);
+
+ schedule_work(&ec->work);
+}
+
+static const struct drm_bridge_funcs aspire_ec_bridge_funcs = {
+ .hpd_enable = aspire_ec_bridge_hpd_enable,
+ .attach = aspire_ec_bridge_attach,
+};
+
+/*
+ * Sysfs attributes.
+ */
+
+static ssize_t fn_lock_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct aspire_ec *ec = i2c_get_clientdata(to_i2c_client(dev));
+ u8 tmp;
+
+ aspire_ec_ram_read(ec->client, ASPIRE_EC_RAM_KBD_MODE, &tmp, sizeof(tmp));
+
+ return sysfs_emit(buf, "%u\n", !(tmp & ASPIRE_EC_RAM_KBD_MEDIA_ON_TOP));
+}
+
+static ssize_t fn_lock_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct aspire_ec *ec = i2c_get_clientdata(to_i2c_client(dev));
+ u8 tmp;
+
+ bool state;
+ int ret;
+
+ ret = kstrtobool(buf, &state);
+ if (ret)
+ return ret;
+
+ aspire_ec_ram_read(ec->client, ASPIRE_EC_RAM_KBD_MODE, &tmp, sizeof(tmp));
+
+ if (state)
+ tmp &= ~ASPIRE_EC_RAM_KBD_MEDIA_ON_TOP;
+ else
+ tmp |= ASPIRE_EC_RAM_KBD_MEDIA_ON_TOP;
+
+ aspire_ec_ram_write(ec->client, ASPIRE_EC_RAM_KBD_MODE, tmp);
+
+ return count;
+}
+
+static DEVICE_ATTR_RW(fn_lock);
+
+static struct attribute *aspire_ec_attrs[] = {
+ &dev_attr_fn_lock.attr,
+ NULL
+};
+ATTRIBUTE_GROUPS(aspire_ec);
+
+static int aspire_ec_probe(struct i2c_client *client)
+{
+ struct power_supply_config psy_cfg = {0};
+ struct device *dev = &client->dev;
+ struct fwnode_handle *fwnode;
+ struct aspire_ec *ec;
+ int ret;
+ u8 tmp;
+
+ ec = devm_kzalloc(dev, sizeof(*ec), GFP_KERNEL);
+ if (!ec)
+ return -ENOMEM;
+
+ ec->client = client;
+ i2c_set_clientdata(client, ec);
+
+ /* Battery status reports */
+ psy_cfg.drv_data = ec;
+ ec->bat_psy = devm_power_supply_register(dev, &aspire_ec_bat_psy_desc, &psy_cfg);
+ if (IS_ERR(ec->bat_psy))
+ return dev_err_probe(dev, PTR_ERR(ec->bat_psy),
+ "Failed to register battery power supply\n");
+
+ ec->adp_psy = devm_power_supply_register(dev, &aspire_ec_adp_psy_desc, &psy_cfg);
+ if (IS_ERR(ec->adp_psy))
+ return dev_err_probe(dev, PTR_ERR(ec->adp_psy),
+ "Failed to register AC power supply\n");
+
+ /* Lid switch */
+ ec->idev = devm_input_allocate_device(dev);
+ if (!ec->idev)
+ return -ENOMEM;
+
+ ec->idev->name = "aspire-ec";
+ ec->idev->phys = "aspire-ec/input0";
+ input_set_capability(ec->idev, EV_SW, SW_LID);
+
+ ret = input_register_device(ec->idev);
+ if (ret)
+ return dev_err_probe(dev, ret, "Input device register failed\n");
+
+ /* Enable the keyboard fn keys */
+ tmp = ASPIRE_EC_RAM_KBD_FN_EN | ASPIRE_EC_RAM_KBD_ALWAYS_SET;
+ tmp |= ASPIRE_EC_RAM_KBD_MEDIA_ON_TOP;
+ aspire_ec_ram_write(client, ASPIRE_EC_RAM_KBD_MODE, tmp);
+
+ aspire_ec_ram_read(client, ASPIRE_EC_RAM_KBD_MODE_2, &tmp, sizeof(tmp));
+ tmp |= ASPIRE_EC_RAM_KBD_MEDIA_NOTIFY;
+ aspire_ec_ram_write(client, ASPIRE_EC_RAM_KBD_MODE_2, tmp);
+
+ /* External Type-C display attach reports */
+ fwnode = device_get_named_child_node(dev, "connector");
+ if (fwnode) {
+ INIT_WORK(&ec->work, aspire_ec_bridge_update_hpd_work);
+ ec->bridge.funcs = &aspire_ec_bridge_funcs;
+ ec->bridge.of_node = to_of_node(fwnode);
+ ec->bridge.ops = DRM_BRIDGE_OP_HPD;
+ ec->bridge.type = DRM_MODE_CONNECTOR_USB;
+
+ ret = devm_drm_bridge_add(dev, &ec->bridge);
+ if (ret) {
+ fwnode_handle_put(fwnode);
+ return dev_err_probe(dev, ret, "Failed to register drm bridge\n");
+ }
+
+ ec->bridge_configured = true;
+ }
+
+ ret = devm_request_threaded_irq(dev, client->irq, NULL,
+ aspire_ec_irq_handler, IRQF_ONESHOT,
+ dev_name(dev), ec);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to request irq\n");
+
+ return 0;
+}
+
+static int aspire_ec_resume(struct device *dev)
+{
+ struct aspire_ec *ec = i2c_get_clientdata(to_i2c_client(dev));
+ u8 tmp;
+
+ aspire_ec_ram_read(ec->client, ASPIRE_EC_RAM_LID_STATUS, &tmp, sizeof(tmp));
+ input_report_switch(ec->idev, SW_LID, !!(tmp & ASPIRE_EC_LID_OPEN));
+ input_sync(ec->idev);
+
+ return 0;
+}
+
+static const struct i2c_device_id aspire_ec_id[] = {
+ { "aspire1-ec", },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, aspire_ec_id);
+
+static const struct of_device_id aspire_ec_of_match[] = {
+ { .compatible = "acer,aspire1-ec", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, aspire_ec_of_match);
+
+static DEFINE_SIMPLE_DEV_PM_OPS(aspire_ec_pm_ops, NULL, aspire_ec_resume);
+
+static struct i2c_driver aspire_ec_driver = {
+ .driver = {
+ .name = "aspire-ec",
+ .of_match_table = aspire_ec_of_match,
+ .pm = pm_sleep_ptr(&aspire_ec_pm_ops),
+ .dev_groups = aspire_ec_groups,
+ },
+ .probe = aspire_ec_probe,
+ .id_table = aspire_ec_id,
+};
+module_i2c_driver(aspire_ec_driver);
+
+MODULE_DESCRIPTION("Acer Aspire 1 embedded controller");
+MODULE_AUTHOR("Nikita Travkin <nikita@trvn.ru>");
+MODULE_LICENSE("GPL");
--
2.44.0

94
device/community/linux-postmarketos-qcom-sc7180/0010-arm64-dts-qcom-acer-aspire1-Add-embedded-controller.patch Normal file
View file

@ -0,0 +1,94 @@
From 2379590f43baff3f0e80326f25df21cc98e8ae11 Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Sat, 9 Jul 2022 00:40:27 +0500
Subject: [PATCH 10/11] arm64: dts: qcom: acer-aspire1: Add embedded controller
The laptop contains an embedded controller that provides a set of
features:
- Battery and charger monitoring
- USB Type-C DP alt mode HPD monitoring
- Lid status detection
- Small amount of keyboard configuration*
[*] The keyboard is handled by the same EC but it has a dedicated i2c
bus and is already enabled. This port only provides fn key behavior
configuration.
Add the EC to the device tree and describe the relationship between the
EC-managed type-c port and the SoC DisplayPort.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
---
.../boot/dts/qcom/sc7180-acer-aspire1.dts | 40 ++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
index 5afcb8212f49..3f0d3e33894a 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
@@ -255,7 +255,25 @@ &i2c2 {
clock-frequency = <400000>;
status = "okay";
- /* embedded-controller@76 */
+ embedded-controller@76 {
+ compatible = "acer,aspire1-ec";
+ reg = <0x76>;
+
+ interrupts-extended = <&tlmm 30 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&ec_int_default>;
+ pinctrl-names = "default";
+
+ connector {
+ compatible = "usb-c-connector";
+
+ port {
+ ec_dp_in: endpoint {
+ remote-endpoint = <&mdss_dp_out>;
+ };
+ };
+ };
+ };
};
&i2c4 {
@@ -419,6 +437,19 @@ &mdss {
status = "okay";
};
+&mdss_dp {
+ data-lanes = <0 1>;
+
+ vdda-1p2-supply = <&vreg_l3c_1p2>;
+ vdda-0p9-supply = <&vreg_l4a_0p8>;
+
+ status = "okay";
+};
+
+&mdss_dp_out {
+ remote-endpoint = <&ec_dp_in>;
+};
+
&mdss_dsi0 {
vdda-supply = <&vreg_l3c_1p2>;
status = "okay";
@@ -857,6 +888,13 @@ codec_irq_default: codec-irq-deault-state {
bias-disable;
};
+ ec_int_default: ec-int-default-state {
+ pins = "gpio30";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
edp_bridge_irq_default: edp-bridge-irq-default-state {
pins = "gpio11";
function = "gpio";
--
2.44.0

103
device/community/linux-postmarketos-qcom-sc7180/0011-ASoC-qcom-sc7180-Map-missing-jack-kcontrols.patch
View file

@ -1,103 +0,0 @@
From 8b12f09d1ba7f704e1ff0435d891556aae675b22 Mon Sep 17 00:00:00 2001
From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Date: Wed, 2 Aug 2023 20:57:30 +0300
Subject: [PATCH 11/17] ASoC: qcom: sc7180: Map missing jack kcontrols
This driver does not properly map jack pins to kcontrols that PulseAudio
and PipeWire need to handle jack detection events. The RT5682 and
RT5682s codecs used here can detect Headphone and Headset Mic
connections. Expose each to userspace as a kcontrol.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Link: https://lore.kernel.org/r/20230802175737.263412-21-alpernebiyasak@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
sound/soc/qcom/sc7180.c | 40 +++++++++++++++++++++++++++++++++-------
1 file changed, 33 insertions(+), 7 deletions(-)
diff --git a/sound/soc/qcom/sc7180.c b/sound/soc/qcom/sc7180.c
index f5f7c64b23a2..57c5f35dfcc5 100644
--- a/sound/soc/qcom/sc7180.c
+++ b/sound/soc/qcom/sc7180.c
@@ -42,6 +42,17 @@ static void sc7180_jack_free(struct snd_jack *jack)
snd_soc_component_set_jack(component, NULL, NULL);
}
+static struct snd_soc_jack_pin sc7180_jack_pins[] = {
+ {
+ .pin = "Headphone Jack",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ {
+ .pin = "Headset Mic",
+ .mask = SND_JACK_MICROPHONE,
+ },
+};
+
static int sc7180_headset_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
@@ -51,13 +62,14 @@ static int sc7180_headset_init(struct snd_soc_pcm_runtime *rtd)
struct snd_jack *jack;
int rval;
- rval = snd_soc_card_jack_new(
- card, "Headset Jack",
- SND_JACK_HEADSET |
- SND_JACK_HEADPHONE |
- SND_JACK_BTN_0 | SND_JACK_BTN_1 |
- SND_JACK_BTN_2 | SND_JACK_BTN_3,
- &pdata->hs_jack);
+ rval = snd_soc_card_jack_new_pins(card, "Headset Jack",
+ SND_JACK_HEADSET |
+ SND_JACK_HEADPHONE |
+ SND_JACK_BTN_0 | SND_JACK_BTN_1 |
+ SND_JACK_BTN_2 | SND_JACK_BTN_3,
+ &pdata->hs_jack,
+ sc7180_jack_pins,
+ ARRAY_SIZE(sc7180_jack_pins));
if (rval < 0) {
dev_err(card->dev, "Unable to add Headset Jack\n");
@@ -297,6 +309,11 @@ static const struct snd_soc_dapm_widget sc7180_snd_widgets[] = {
SND_SOC_DAPM_MIC("Headset Mic", NULL),
};
+static const struct snd_kcontrol_new sc7180_snd_controls[] = {
+ SOC_DAPM_PIN_SWITCH("Headphone Jack"),
+ SOC_DAPM_PIN_SWITCH("Headset Mic"),
+};
+
static const struct snd_soc_dapm_widget sc7180_adau7002_snd_widgets[] = {
SND_SOC_DAPM_MIC("DMIC", NULL),
};
@@ -320,6 +337,11 @@ static const struct snd_soc_dapm_widget sc7180_snd_dual_mic_widgets[] = {
SND_SOC_DAPM_MUX("Dmic Mux", SND_SOC_NOPM, 0, 0, &sc7180_dmic_mux_control),
};
+static const struct snd_kcontrol_new sc7180_snd_dual_mic_controls[] = {
+ SOC_DAPM_PIN_SWITCH("Headphone Jack"),
+ SOC_DAPM_PIN_SWITCH("Headset Mic"),
+};
+
static const struct snd_soc_dapm_route sc7180_snd_dual_mic_audio_route[] = {
{"Dmic Mux", "Front Mic", "DMIC"},
{"Dmic Mux", "Rear Mic", "DMIC"},
@@ -348,10 +370,14 @@ static int sc7180_snd_platform_probe(struct platform_device *pdev)
card->dev = dev;
card->dapm_widgets = sc7180_snd_widgets;
card->num_dapm_widgets = ARRAY_SIZE(sc7180_snd_widgets);
+ card->controls = sc7180_snd_controls;
+ card->num_controls = ARRAY_SIZE(sc7180_snd_controls);
if (of_property_read_bool(dev->of_node, "dmic-gpios")) {
card->dapm_widgets = sc7180_snd_dual_mic_widgets,
card->num_dapm_widgets = ARRAY_SIZE(sc7180_snd_dual_mic_widgets),
+ card->controls = sc7180_snd_dual_mic_controls,
+ card->num_controls = ARRAY_SIZE(sc7180_snd_dual_mic_controls),
card->dapm_routes = sc7180_snd_dual_mic_audio_route,
card->num_dapm_routes = ARRAY_SIZE(sc7180_snd_dual_mic_audio_route),
data->dmic_sel = devm_gpiod_get(&pdev->dev, "dmic", GPIOD_OUT_LOW);
--
2.43.0

78
device/community/linux-postmarketos-qcom-sc7180/0011-HACK-clk-Delay-disabling-unused-clocks-by-10s.patch Normal file
View file

@ -0,0 +1,78 @@
From c3fccf1615be6548b50274851557f579b6320b5b Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Mon, 11 Mar 2024 14:53:04 +0500
Subject: [PATCH] HACK: clk: Delay disabling unused clocks by 10s
There is a forever-lasting problem with qcom clocks that causes display
subsystem crash due to "disp_cc_mdss_mdp_clk status stuck at 'off'" if
the clocks were cleaned up before msm claimed this one.
Delay disabling unused clocks by 10 seconds to work around this.
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
---
drivers/clk/clk.c | 24 ++++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 50228cb0c559..f0647ecca9ac 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1347,7 +1347,7 @@ static void clk_core_disable_unprepare(struct clk_core *core)
clk_core_unprepare_lock(core);
}
-static void __init clk_unprepare_unused_subtree(struct clk_core *core)
+static void clk_unprepare_unused_subtree(struct clk_core *core)
{
struct clk_core *child;
@@ -1377,7 +1377,7 @@ static void __init clk_unprepare_unused_subtree(struct clk_core *core)
clk_pm_runtime_put(core);
}
-static void __init clk_disable_unused_subtree(struct clk_core *core)
+static void clk_disable_unused_subtree(struct clk_core *core)
{
struct clk_core *child;
unsigned long flags;
@@ -1431,15 +1431,10 @@ static int __init clk_ignore_unused_setup(char *__unused)
}
__setup("clk_ignore_unused", clk_ignore_unused_setup);
-static int __init clk_disable_unused(void)
+static void clk_disable_unused_work_function(struct work_struct *work)
{
struct clk_core *core;
- if (clk_ignore_unused) {
- pr_warn("clk: Not disabling unused clocks\n");
- return 0;
- }
-
pr_info("clk: Disabling unused clocks\n");
clk_prepare_lock();
@@ -1457,6 +1452,19 @@ static int __init clk_disable_unused(void)
clk_unprepare_unused_subtree(core);
clk_prepare_unlock();
+}
+static DECLARE_DELAYED_WORK(clk_disable_unused_work,
+ clk_disable_unused_work_function);
+
+static int __init clk_disable_unused(void)
+{
+ if (clk_ignore_unused) {
+ pr_warn("clk: Not disabling unused clocks\n");
+ return 0;
+ }
+
+ schedule_delayed_work(&clk_disable_unused_work,
+ msecs_to_jiffies(10000));
return 0;
}
--
2.44.0

60
device/community/linux-postmarketos-qcom-sc7180/0015-arm64-dts-qcom-acer-aspire1-Correct-audio-codec-defi.patch
View file

@ -1,60 +0,0 @@
From 28eac7fe663108b43c15d25566b03e8ccb71466c Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Tue, 5 Dec 2023 16:48:11 +0500
Subject: [PATCH 15/17] arm64: dts: qcom: acer-aspire1: Correct audio codec
definition
When initially added, a mistake was made in the definition of the codec.
Despite the fact that the DMIC line is connected on the side of the
codec chip, and relevant passive components, including 0-ohm resistors
connecting the dmics, are present, the dmic line is still cut in
another place on the board, which was overlooked.
Correct this by replacing the dmic configuration with a comment
describing this hardware detail.
While at it, also add missing regulators definitions. This is not a
functional change as all the relevant regulators were already added via
the other rail supplies.
Fixes: 4a9f8f8f2ada ("arm64: dts: qcom: Add Acer Aspire 1")
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Link: https://lore.kernel.org/r/20231205-aspire1-sound-v2-2-443b7ac0a06f@trvn.ru
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
.../arm64/boot/dts/qcom/sc7180-acer-aspire1.dts | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
index ab8ec7958584..7bde69f39c8a 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
@@ -224,9 +224,22 @@ alc5682: codec@1a {
AVDD-supply = <&vreg_l15a_1p8>;
MICVDD-supply = <&reg_codec_3p3>;
VBAT-supply = <&reg_codec_3p3>;
+ DBVDD-supply = <&vreg_l15a_1p8>;
+ LDO1-IN-supply = <&vreg_l15a_1p8>;
+
+ /*
+ * NOTE: The board has a path from this codec to the
+ * DMIC microphones in the lid, however some of the option
+ * resistors are absent and the microphones are connected
+ * to the SoC instead.
+ *
+ * If the resistors were to be changed by the user to
+ * connect the codec, the following could be used:
+ *
+ * realtek,dmic1-data-pin = <1>;
+ * realtek,dmic1-clk-pin = <1>;
+ */
- realtek,dmic1-data-pin = <1>;
- realtek,dmic1-clk-pin = <1>;
realtek,jd-src = <1>;
};
};
--
2.43.0

34
device/community/linux-postmarketos-qcom-sc7180/0017-HACK-arm64-dts-qcom-acer-aspire1-Enable-DisplayPort-.patch
View file

@ -1,34 +0,0 @@
From a69329189d779cadf5687ae294a6b62a714f7360 Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Wed, 20 Dec 2023 12:30:04 +0500
Subject: [PATCH 17/17] HACK: arm64: dts: qcom: acer-aspire1: Enable
DisplayPort block
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
---
arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
index 58f694d8e762..bca950645a97 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
@@ -434,6 +434,15 @@ &mdss {
status = "okay";
};
+&mdss_dp {
+ data-lanes = <0 1>;
+
+ vdda-1p2-supply = <&vreg_l3c_1p2>;
+ vdda-0p9-supply = <&vreg_l4a_0p8>;
+
+ status = "okay";
+};
+
&pm6150_adc {
thermistor@4e {
reg = <ADC5_AMUX_THM2_100K_PU>;
--
2.43.0

64
device/community/linux-postmarketos-qcom-sc7180/APKBUILD
View file

@ -1,7 +1,7 @@
# Maintainer: Jenneron <jenneron@protonmail.com>
pkgname=linux-postmarketos-qcom-sc7180
pkgver=6.1.39
pkgrel=7
pkgver=6.6.28
pkgrel=0
pkgdesc="Mainline kernel fork for Qualcomm Snapdragon 7c devices"
arch="aarch64"
_carch="arm64"
@ -34,23 +34,17 @@ case $pkgver in
esac
source="
https://cdn.kernel.org/pub/linux/kernel/v${_kernver%%.*}.x/linux-${pkgver//_/-}.tar.xz
0001-drm-panel-edp-Add-enable-timings-for-N140HCA-EAC-pan.patch
0002-drm-bridge-ti-sn65dsi86-Implement-wait_hpd_asserted.patch
0003-arm64-dts-qcom-sc7180-Don-t-enable-lpass-clocks-by-d.patch
0004-arm64-dts-qcom-sc7180-Drop-redundant-disable-in-mdp.patch
0005-arm64-dts-qcom-Add-Acer-Aspire-1.patch
0006-media-venus-core-Set-up-secure-memory-ranges-for-SC7.patch
0007-arm64-dts-qcom-sc7180-Split-up-TF-A-related-PSCI-con.patch
0008-remoteproc-qcom-pas-Add-sc7180-adsp.patch
0009-arm64-dts-qcom-sc7180-Add-tertiary-mi2s-pinctrl.patch
0010-arm64-dts-qcom-sc7180-Add-ADSP.patch
0011-ASoC-qcom-sc7180-Map-missing-jack-kcontrols.patch
0012-ASoC-qcom-sc7180-Add-support-for-qdsp6-baked-sound.patch
0013-arm64-dts-qcom-pm6150-Add-resin-and-rtc-nodes.patch
0014-arm64-dts-qcom-acer-aspire1-Enable-RTC.patch
0015-arm64-dts-qcom-acer-aspire1-Correct-audio-codec-defi.patch
0016-arm64-dts-qcom-acer-aspire1-Add-sound.patch
0017-HACK-arm64-dts-qcom-acer-aspire1-Enable-DisplayPort-.patch
0001-remoteproc-qcom-pas-Add-sc7180-adsp.patch
0002-arm64-dts-qcom-sc7180-Add-tertiary-mi2s-pinctrl.patch
0003-arm64-dts-qcom-sc7180-Add-ADSP.patch
0004-ASoC-qcom-sc7180-Add-support-for-qdsp6-baked-sound.patch
0005-arm64-dts-qcom-pm6150-Add-resin-and-rtc-nodes.patch
0006-arm64-dts-qcom-acer-aspire1-Enable-RTC.patch
0007-arm64-dts-qcom-acer-aspire1-Add-sound.patch
0008-platform-Add-ARM64-platform-directory.patch
0009-platform-arm64-Add-Acer-Aspire-1-embedded-controller.patch
0010-arm64-dts-qcom-acer-aspire1-Add-embedded-controller.patch
0011-HACK-clk-Delay-disabling-unused-clocks-by-10s.patch
$_config
"
builddir="$srcdir/linux-${_kernver//_/-}"
@ -81,23 +75,17 @@ package() {
}
sha512sums="
20d468ae89b57dda82d7c7b814c3d8b1b510e1623775b09a8a0b0a8a0431461e0a1d2df2bfa01f3102932c8eef91405546898b50ec3e6f30015098bb39722b41 linux-6.1.39.tar.xz
eee1c168ef24ecff55d01358f806f6aa31bb470d4ce547b812bda64bf78f916834e210d83aaf45955c44577981de5b12c196bff5f7236c7959e7f3df2985d035 0001-drm-panel-edp-Add-enable-timings-for-N140HCA-EAC-pan.patch
f1c85f9e7b2dbebba54eca7080589ee35be501854510fd54f1fb3db07b8cfb62276cb9359a40096ac0a98bd01bc587de89dbf227aad6b371f64b78b5c806e583 0002-drm-bridge-ti-sn65dsi86-Implement-wait_hpd_asserted.patch
03b638baea7703227c398ba37824eeb17a96138aced4cc1e0769a265eb38788ac1fd150166a0af9e22f1364d053f20219b2b269310d01c32c4089682939021bf 0003-arm64-dts-qcom-sc7180-Don-t-enable-lpass-clocks-by-d.patch
82761a3c53167dfb02091fb5305dca67b52872db3ecb14a42d782ba1346f046160d47a379fd88f0e3cb7ee91aa35a2eebe89304edb618df3895e2d469c9c8863 0004-arm64-dts-qcom-sc7180-Drop-redundant-disable-in-mdp.patch
639784302e28afc562fc6d9673b12fbce49f11b5e2400ed5c460d5e157e7196092f33e1c67a1ee6bf8ad5b4dbb81f2f0263439662a1b68ea49c9201f63afe153 0005-arm64-dts-qcom-Add-Acer-Aspire-1.patch
b09b67143e1adc26cb24954a31f3633aaf9624354ba27e69af685503a6621c6c7bad0b5b9c08535548e3e2885ccba7798542b97c4d217ab970ee504ba250595d 0006-media-venus-core-Set-up-secure-memory-ranges-for-SC7.patch
04d746c6b5595097eec2a4bf37df06266a29080bedf7708bd54eb7b98a0b9a6d5581aef45070799b7d10ba94cd11d0ceb09486547e24bf2a597964e9e5566bc1 0007-arm64-dts-qcom-sc7180-Split-up-TF-A-related-PSCI-con.patch
3f9c5b34f6869a9332ca8f260b385d0d7a5c4453d3fe682d864f53d44dceee9bd6bb370e75a60ce61c87b4224347f8cc8647c9d03f2bc2293d8e53ef327e2cc5 0008-remoteproc-qcom-pas-Add-sc7180-adsp.patch
fe389611f991ba9de9e4662b2ed35a6790bbc18bb99fdc12eb281e5a4d5559ada3952a4024145007e9b8fbd3ed5fb862f56ad27f0ff36874decf24090d995f57 0009-arm64-dts-qcom-sc7180-Add-tertiary-mi2s-pinctrl.patch
5fa7a4914ecd6e4ea47dce438cc1100f2747b082c71477859745147df801aede57ef6f1c54680a2c6ca85b61b791faa77210bd216bbe849681b2c558b6c6f152 0010-arm64-dts-qcom-sc7180-Add-ADSP.patch
57c6f29b445ecd92f5fb1d5ca0a2783bccc1fbd3b1e51016db84370b75214fd70c832207f7c59cc00814db686d0ce03f33013138378c25aa18b8646148a296ac 0011-ASoC-qcom-sc7180-Map-missing-jack-kcontrols.patch
08f1e646e1a387f1c5d01c954c87bdebd6fb13aa555eb3430331ffcfae0d6b61697ea4d35fb33b01bda801c92e9308f3a73ddf5b83a3074c009b2cce468f4d42 0012-ASoC-qcom-sc7180-Add-support-for-qdsp6-baked-sound.patch
5e7dabdca52cf329b9a7fe77e6781cce07febda84592a93ea435b94e2707b6a8f3ae63a144070f5e203de4cd2608428cf9ec0c59fc2284bdd5b25bc995064264 0013-arm64-dts-qcom-pm6150-Add-resin-and-rtc-nodes.patch
5c9d7bd7a97b704f512ea398c183778e7aba04d513f14c55dc70ba7a3677613805241f48409ec3af08f62d96c23bd197e0ead0a42c877ad91f7bc32c00b1b606 0014-arm64-dts-qcom-acer-aspire1-Enable-RTC.patch
19441571468c89576da2087bfcfb8eaca253c67b41bd201ba123dafa33e5e6f424c9719b8fddf61cfce4d27f1b138718f200931eafc5edab5cb4da5b225ba410 0015-arm64-dts-qcom-acer-aspire1-Correct-audio-codec-defi.patch
d6ecbd07481bf9852d330f1fbe004e0f70a45251956a37b730e4cbb3b7e3c03b34c9979749ab8857d39171382e87159cc54125fad7a0a02a33d4b502892fce9a 0016-arm64-dts-qcom-acer-aspire1-Add-sound.patch
43cc38c2074a474a4386ab070bcc7b966527a607bc0adb345ce6d13f79b7714e46747ed2624831ae6ed48cf3b4ef387e4cc84247c3b7d13e69a7d1e64f7efe6f 0017-HACK-arm64-dts-qcom-acer-aspire1-Enable-DisplayPort-.patch
7c3ba7a612c58472d75d30658c143065c1e508484b83ff1594001243ca066881c5d9b50210174637261831cab5c770320fcf6d8cd03a5e9fd0fdc7cdefd8abff config-postmarketos-qcom-sc7180.aarch64
fdf6def06de85656f8aa010edfb8b2f7f71cdeef9a70b5b35511833fbcf0e4fbfafb6224acfdf475975bc4bc8f05d0291745af5a6ae752a70cbd09ae2d3d17a8 linux-6.6.28.tar.xz
ac68e3e441c90ebc88d75cabcbb54d836256876932689f74a4d492a19c5aab9e207930ff14ba24f2298af44f662616ef34c9b8147a7ebada2db9c11eab55f3f2 0001-remoteproc-qcom-pas-Add-sc7180-adsp.patch
8f8aad35c408b2c29a8ddd2bc71c8542bef73e9b386c010257004e67bccf82fc1ffe9ca8df0b12d6930a776fdb288a365ddceb7d4bbc7031777bef6fdf3534a1 0002-arm64-dts-qcom-sc7180-Add-tertiary-mi2s-pinctrl.patch
a4d8bbf39575e61d228b3b66fa692b207c1ee011e6030fdd097936a1ad28b1d5b01816d989adcb809d05f107aaf9024ccd077e6daa9c65aa2ff23907ee1f0566 0003-arm64-dts-qcom-sc7180-Add-ADSP.patch
30130ae6e49bc0386fd7b34e69961e208806673b2bf2b7bb9abe428766013116baa924536346bceee60db886565c7e2f9c48c8ba2e691381aae544df730b780a 0004-ASoC-qcom-sc7180-Add-support-for-qdsp6-baked-sound.patch
80479f5b598628f48302aa4c224f173cbe02ebb6a9e14a555b9bf06163a40442cdc8e77c7a6e14684a21df0e61627cfa3345cef385d6d3e11c1d412cc924d85a 0005-arm64-dts-qcom-pm6150-Add-resin-and-rtc-nodes.patch
6628e979e9ba579ff3f259f8d2917318342f4cc855a06ac70dc2a81bf3c9e3a6729b1ebee28591db1374afc7a0aabbbf2f2e8b915c735f070528f6ddfd905631 0006-arm64-dts-qcom-acer-aspire1-Enable-RTC.patch
9200a97d795d97e42e89af9cb47fc750ef2784d883327b6e8ca0ad77634c8af20b531f8917c3584c369fd2f36142cea73f51d416e78a99e80c48ae99165bdf18 0007-arm64-dts-qcom-acer-aspire1-Add-sound.patch
1cc7105a6b4aa112f8203416a11cda56a39dfa957679021f7bf38f9503eab51c99cb53aed391cb7cb6ec853b705f0d5032ea5932f8c342152aca916681b507d3 0008-platform-Add-ARM64-platform-directory.patch
08c6cace24a207f4a64a85b17e97646f62a8590b502cd5b6945489d0aeded352e21f0e1b0ec541ae2e61ec7fd4f6bc1e5bf1d5d32f2c6616eb41d39d66f0bab5 0009-platform-arm64-Add-Acer-Aspire-1-embedded-controller.patch
69cfb699990ea7994089016b29cc248cb03483ad3f7620cbba63a779b2ed8928e6fde68484d29b6b8dfd1a8a6fa8d84c441f30180c7a257520ced442dab33876 0010-arm64-dts-qcom-acer-aspire1-Add-embedded-controller.patch
c5edcd74f898b08bc663766668632d351aea40426b3563d53a4b8c6856dd82627f4794d60450e41171c990ebb3649056b36ef432c14c8783168e8060a2e3b094 0011-HACK-clk-Delay-disabling-unused-clocks-by-10s.patch
2ca01552118f2eedc9ac3818612008c58fe54a0838096a95489ee3380ac43be210d39371b1633af059a9b78f9bd3937e12a861cb72fa1bcac277ffa55bac2606 config-postmarketos-qcom-sc7180.aarch64
"

670
device/community/linux-postmarketos-qcom-sc7180/config-postmarketos-qcom-sc7180.aarch64
View file

File diff suppressed because it is too large Load diff