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linux-postmarketos-mediatek-mt8183: upgrade to 6.1.28 (MR 4089)

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Anton Bambura 2023-05-17 01:17:01 +03:00 committed by Newbyte
parent 3c629c64e3
commit 9c8ccba142
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GPG key ID: 990600ED1DB95E02
34 changed files with 1247 additions and 2716 deletions
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92
device/testing/linux-postmarketos-mediatek-mt8183/0003-arm64-dts-mt8183-Add-kukui-jacuzzi-makomo-board.patch
View file

@ -1,92 +0,0 @@
From 873c0534790f2f367c5a1851d16c37c3368bcd7f Mon Sep 17 00:00:00 2001
From: Hsin-Yi Wang <hsinyi@chromium.org>
Date: Mon, 13 Dec 2021 15:23:53 +0800
Subject: [PATCH 3/5] arm64: dts: mt8183: Add kukui-jacuzzi-makomo board
Makomo is known as Lenovo 100e Gen 2.
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
arch/arm64/boot/dts/mediatek/Makefile | 2 ++
.../mt8183-kukui-jacuzzi-makomo-sku0.dts | 24 +++++++++++++++++++
.../mt8183-kukui-jacuzzi-makomo-sku1.dts | 24 +++++++++++++++++++
3 files changed, 50 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index cb8d563d079f..57b33de22981 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -26,6 +26,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku0.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts
new file mode 100644
index 000000000000..51bf2893ec03
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-fennel.dtsi"
+#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
+
+/ {
+ model = "Google makomo sku0 board";
+ compatible = "google,makomo-rev4-sku0", "google,makomo-rev5-sku0",
+ "google,makomo", "mediatek,mt8183";
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_FENNEL14";
+};
+
+&mmc1_pins_uhs {
+ pins_clk {
+ drive-strength = <MTK_DRIVE_6mA>;
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts
new file mode 100644
index 000000000000..c3b7e9bb0c89
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-fennel.dtsi"
+#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi"
+
+/ {
+ model = "Google makomo sku1 board";
+ compatible = "google,makomo-rev4-sku1", "google,makomo-rev5-sku1",
+ "google,makomo", "mediatek,mt8183";
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_FENNEL14";
+};
+
+&mmc1_pins_uhs {
+ pins_clk {
+ drive-strength = <MTK_DRIVE_6mA>;
+ };
+};
--
2.39.1

41
device/testing/linux-postmarketos-mediatek-mt8183/0005-dt-bindings-arm64-dts-mediatek-Add-mt8183-kukui-jacu.patch
View file

@ -1,41 +0,0 @@
From 01a91263c79ec7730e3c6eb4ed71436f2e14639d Mon Sep 17 00:00:00 2001
From: Hsin-Yi Wang <hsinyi@chromium.org>
Date: Mon, 13 Dec 2021 15:23:55 +0800
Subject: [PATCH 5/5] dt-bindings: arm64: dts: mediatek: Add
mt8183-kukui-jacuzzi-makomo
Makomo is known as Lenovo 100e Gen 2 Chromebook.
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
.../devicetree/bindings/arm/mediatek.yaml | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index 1fdb9a91635d..f13c7c66cfbb 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -203,6 +203,20 @@ properties:
- google,kodama-sku32
- const: google,kodama
- const: mediatek,mt8183
+ - description: Google Makomo (Lenovo 100e Gen 2)
+ items:
+ - enum:
+ - const: google,makomo-rev4-sku0
+ - const: google,makomo-rev5-sku0
+ - const: google,makomo
+ - const: mediatek,mt8183
+ - description: Google Makomo (Lenovo 100e Gen 2)
+ items:
+ - enum:
+ - const: google,makomo-rev4-sku1
+ - const: google,makomo-rev5-sku1
+ - const: google,makomo
+ - const: mediatek,mt8183
- description: Google Willow (Acer Chromebook 311 C722/C722T)
items:
- enum:
--
2.39.1

26
device/testing/linux-postmarketos-mediatek-mt8183/0001-drm-panel-Add-inx-Himax8279d-MIPI-DSI-LCD-panel-driv.patch → device/testing/linux-postmarketos-mediatek-mt8183/01-RESEND-v2-1-2-drm-panel-Add-inx-Himax8279d-MIPI-DSI-LCD-panel-driver.patch
View file

@ -1,18 +1,5 @@
From ae92d9b9f1bd0b7c26fb49bc8256356ae3734e97 Mon Sep 17 00:00:00 2001
From: xiazhengqiao <xiazhengqiao@huaqin.corp-partner.google.com>
Date: Mon, 8 Nov 2021 18:06:08 +0800
Subject: [PATCH 1/5] drm/panel: Add inx Himax8279d MIPI-DSI LCD panel driver
Add STARRY 2081101QFH032011-53G 10.1" WUXGA TFT LCD panel
Signed-off-by: xiazhengqiao <xiazhengqiao@huaqin.corp-partner.google.com>
Tested-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile | 1 +
.../gpu/drm/panel/panel-innolux-himax8279d.c | 515 ++++++++++++++++++
3 files changed, 525 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-innolux-himax8279d.c
based on: https://patchwork.freedesktop.org/patch/482097/
adjusted for v6.1: inx_panel_remove returns void now in drivers/gpu/drm/panel/panel-innolux-himax8279d.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index ddf5f38e8731..375a67f69230 100644
@ -51,7 +38,7 @@ new file mode 100644
index 000000000000..6840449548e4
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-innolux-himax8279d.c
@@ -0,0 +1,515 @@
@@ -0,0 +1,513 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021, Huaqin Telecom Technology Co., Ltd
@ -528,7 +515,7 @@ index 000000000000..6840449548e4
+ drm_panel_unprepare(&inx->base);
+}
+
+static int inx_panel_remove(struct mipi_dsi_device *dsi)
+static void inx_panel_remove(struct mipi_dsi_device *dsi)
+{
+ struct inx_panel *inx = mipi_dsi_get_drvdata(dsi);
+ int ret;
@ -541,8 +528,6 @@ index 000000000000..6840449548e4
+
+ if (inx->base.dev)
+ drm_panel_remove(&inx->base);
+
+ return 0;
+}
+
+static const struct of_device_id inx_of_match[] = {
@ -567,6 +552,3 @@ index 000000000000..6840449548e4
+MODULE_AUTHOR("Zhengqiao Xia <xiazhengqiao@huaqin.corp-partner.google.com>");
+MODULE_DESCRIPTION("INNOLUX HIMAX8279D 1200x1920 video mode panel driver");
+MODULE_LICENSE("GPL v2");
--
2.39.1

36
device/testing/linux-postmarketos-mediatek-mt8183/0002-arm64-dts-mt8183-Add-katsu-board.patch → device/testing/linux-postmarketos-mediatek-mt8183/03-v2-1-4-arm64-dts-mt8183-Add-katsu-board.patch
View file

@ -1,35 +1,8 @@
From 61ddff1482c49b9720849647937a22e47b225c4f Mon Sep 17 00:00:00 2001
From: Hsin-Yi Wang <hsinyi@chromium.org>
Date: Mon, 13 Dec 2021 15:23:52 +0800
Subject: [PATCH 2/5] arm64: dts: mt8183: Add katsu board
based on: https://patchwork.kernel.org/project/linux-mediatek/patch/20211213162856.235130-1-hsinyi@chromium.org/
Katsu is known as ASUS Chromebook Detachable CZ1.
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
arch/arm64/boot/dts/mediatek/Makefile | 2 +
.../dts/mediatek/mt8183-kukui-katsu-sku32.dts | 38 +++++++++++++++++
.../dts/mediatek/mt8183-kukui-katsu-sku38.dts | 42 +++++++++++++++++++
3 files changed, 82 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 8c1e18032f9f..cb8d563d079f 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -30,6 +30,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu-sku22.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku32.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku38.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts
new file mode 100644
index 000000000000..f923b8c3c49c
index 00000000000000..f923b8c3c49c36
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts
@@ -0,0 +1,38 @@
@ -73,7 +46,7 @@ index 000000000000..f923b8c3c49c
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts
new file mode 100644
index 000000000000..1ab14096a279
index 00000000000000..1ab14096a279c6
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts
@@ -0,0 +1,42 @@
@ -119,6 +92,3 @@ index 000000000000..1ab14096a279
+&sound {
+ compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p";
+};
--
2.39.1

62
device/testing/linux-postmarketos-mediatek-mt8183/04-v2-2-4-arm64-dts-mt8183-Add-kukui-jacuzzi-makomo-board.patch Normal file
View file

@ -0,0 +1,62 @@
based on: https://patchwork.kernel.org/project/linux-mediatek/patch/20211213162856.235130-2-hsinyi@chromium.org/
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts
new file mode 100644
index 00000000000000..51bf2893ec03b1
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-fennel.dtsi"
+#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
+
+/ {
+ model = "Google makomo sku0 board";
+ compatible = "google,makomo-rev4-sku0", "google,makomo-rev5-sku0",
+ "google,makomo", "mediatek,mt8183";
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_FENNEL14";
+};
+
+&mmc1_pins_uhs {
+ pins_clk {
+ drive-strength = <MTK_DRIVE_6mA>;
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts
new file mode 100644
index 00000000000000..c3b7e9bb0c8960
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-fennel.dtsi"
+#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi"
+
+/ {
+ model = "Google makomo sku1 board";
+ compatible = "google,makomo-rev4-sku1", "google,makomo-rev5-sku1",
+ "google,makomo", "mediatek,mt8183";
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_FENNEL14";
+};
+
+&mmc1_pins_uhs {
+ pins_clk {
+ drive-strength = <MTK_DRIVE_6mA>;
+ };
+};

19
device/testing/linux-postmarketos-mediatek-mt8183/0004-dt-bindings-arm64-dts-mediatek-Add-mt8183-kukui-kats.patch → device/testing/linux-postmarketos-mediatek-mt8183/05-v2-3-4-dt-bindings-arm64-dts-mediatek-Add-mt8183-kukui-katsu.patch
View file

@ -1,20 +1,10 @@
From 2201a9e503a183c00c46b68313583539f82c377a Mon Sep 17 00:00:00 2001
From: Hsin-Yi Wang <hsinyi@chromium.org>
Date: Mon, 13 Dec 2021 15:23:54 +0800
Subject: [PATCH 4/5] dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-katsu
Katsu is known as ASUS Chromebook Detachable CZ1.
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
Documentation/devicetree/bindings/arm/mediatek.yaml | 7 +++++++
1 file changed, 7 insertions(+)
based on: https://patchwork.kernel.org/project/linux-mediatek/patch/20211213162856.235130-3-hsinyi@chromium.org/
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index ab0593c77321..1fdb9a91635d 100644
index 723810cffce2e7..75bb06d1802a08 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -187,6 +187,13 @@ properties:
@@ -175,6 +175,13 @@ properties:
items:
- const: google,kappa
- const: mediatek,mt8183
@ -28,6 +18,3 @@ index ab0593c77321..1fdb9a91635d 100644
- description: Google Kodama (Lenovo 10e Chromebook Tablet)
items:
- enum:
--
2.39.1

25
device/testing/linux-postmarketos-mediatek-mt8183/06-v2-4-4-dt-bindings-arm64-dts-mediatek-Add-mt8183-kukui-jacuzzi-makomo.patch Normal file
View file

@ -0,0 +1,25 @@
based on: https://patchwork.kernel.org/project/linux-mediatek/patch/20211213162856.235130-4-hsinyi@chromium.org/
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index 75bb06d1802a08..828f5f3fde4e20 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -191,6 +191,18 @@ properties:
- google,kodama-sku32
- const: google,kodama
- const: mediatek,mt8183
+ - description: Google Makomo (Lenovo 100e Gen 2)
+ items:
+ - const: google,makomo-rev4-sku0
+ - const: google,makomo-rev5-sku0
+ - const: google,makomo
+ - const: mediatek,mt8183
+ - description: Google Makomo (Lenovo 100e Gen 2)
+ items:
+ - const: google,makomo-rev4-sku1
+ - const: google,makomo-rev5-sku1
+ - const: google,makomo
+ - const: mediatek,mt8183
- description: Google Willow (Acer Chromebook 311 C722/C722T)
items:
- enum:

161
device/testing/linux-postmarketos-mediatek-mt8183/07-1-2-arm64-dts-mt8183-Add-kukui-jacuzzi-cerise-board.patch Normal file
View file

@ -0,0 +1,161 @@
based on: https://patchwork.kernel.org/project/linux-mediatek/patch/20210604052312.1040707-1-hsinyi@chromium.org/
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise-rev3.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise-rev3.dts
new file mode 100644
index 0000000000000..2776d93561c96
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise-rev3.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-cerise.dtsi"
+
+/ {
+ model = "Google cerise board";
+ compatible = "google,cerise-rev3-sku0", "google,cerise", "mediatek,mt8183";
+};
+
+&mt6358codec {
+ mediatek,dmic-mode = <1>; /* one-wire */
+};
+
+&touchscreen {
+ status = "disabled";
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_CERISE";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dts
new file mode 100644
index 0000000000000..418b5024d1a7c
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-cerise.dtsi"
+
+/ {
+ model = "Google cerise board";
+ compatible = "google,cerise-sku0", "google,cerise", "mediatek,mt8183";
+};
+
+&mt6358codec {
+ mediatek,dmic-mode = <1>; /* one-wire */
+};
+
+&touchscreen {
+ status = "disabled";
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_CERISE";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dtsi
new file mode 100644
index 0000000000000..ec1561ac395ba
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi.dtsi"
+
+&mmc1_pins_uhs {
+ pins_clk {
+ drive-strength = <MTK_DRIVE_6mA>;
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern-rev3.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern-rev3.dts
new file mode 100644
index 0000000000000..05303c4ed7511
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern-rev3.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-cerise.dtsi"
+
+/ {
+ model = "Google stern board";
+ compatible = "google,cerise-rev3-sku1", "google,cerise", "mediatek,mt8183";
+};
+
+&mt6358codec {
+ mediatek,dmic-mode = <0>; /* two-wire */
+};
+
+&touchscreen {
+ status = "okay";
+
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+ interrupt-parent = <&pio>;
+ interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+
+ post-power-on-delay-ms = <10>;
+ hid-descr-addr = <0x0001>;
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_STERN";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern.dts
new file mode 100644
index 0000000000000..5be767bc873b8
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-cerise.dtsi"
+
+/ {
+ model = "Google stern board";
+ compatible = "google,cerise-sku1", "google,cerise", "mediatek,mt8183";
+};
+
+&mt6358codec {
+ mediatek,dmic-mode = <0>; /* two-wire */
+};
+
+&touchscreen {
+ status = "okay";
+
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+ interrupt-parent = <&pio>;
+ interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+
+ post-power-on-delay-ms = <10>;
+ hid-descr-addr = <0x0001>;
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_STERN";
+};

22
device/testing/linux-postmarketos-mediatek-mt8183/08-2-2-dt-bindings-arm64-dts-mediatek-Add-mt8183-kukui-jacuzzi-cerise.patch Normal file
View file

@ -0,0 +1,22 @@
based on: https://patchwork.kernel.org/project/linux-mediatek/patch/20210604052312.1040707-2-hsinyi@chromium.org/
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index 80a05f6fee85b..02c0653737648 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -126,6 +126,15 @@ properties:
items:
- const: google,burnet
- const: mediatek,mt8183
+ - description: Google Cerise (ASUS Chromebook CZ1) / Stern (ASUS Chromebook Flip CZ1)
+ items:
+ - enum:
+ - google,cerise-sku0
+ - google,cerise-sku1
+ - google,cerise-rev3-sku0
+ - google,cerise-rev3-sku1
+ - const: google,cerise
+ - const: mediatek,mt8183
- description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
items:
- enum:

30
device/testing/linux-postmarketos-mediatek-mt8183/09-add-new-dtbs-to-makefile.patch Normal file
View file

@ -0,0 +1,30 @@
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index af362a085a02..52d291eeff53 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -16,6 +16,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cerise.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cerise-rev3.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb
@@ -26,10 +28,16 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku0.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku1.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-stern.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-stern-rev3.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu-sku22.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku32.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku38.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb

82
device/testing/linux-postmarketos-mediatek-mt8183/APKBUILD
View file

@ -1,8 +1,9 @@
# Maintainer: BinaryCraft <keep.it.sns@gmail.com>
# Co-Maintainer: Jenneron <jenneron@protonmail.com>
# Based on https://github.com/hexdump0815/linux-mainline-mediatek-mt81xx-kernel
pkgname=linux-postmarketos-mediatek-mt8183
pkgver=5.18
pkgrel=4
pkgver=6.1.28
pkgrel=0
pkgdesc="Mainline kernel for mediatek mt8183"
arch="aarch64"
_flavor="${pkgname#linux-}"
@ -42,33 +43,23 @@ esac
source="
https://cdn.kernel.org/pub/linux/kernel/v${_kernver%%.*}.x/linux-$_kernver.tar.xz
0001-drm-panel-Add-inx-Himax8279d-MIPI-DSI-LCD-panel-driv.patch
0002-arm64-dts-mt8183-Add-katsu-board.patch
0003-arm64-dts-mt8183-Add-kukui-jacuzzi-makomo-board.patch
0004-dt-bindings-arm64-dts-mediatek-Add-mt8183-kukui-kats.patch
0005-dt-bindings-arm64-dts-mediatek-Add-mt8183-kukui-jacu.patch
mt8183-cadmium-improved-kukui.gpu.patch
mt8183-cadmium-kukui.move-gpu-opp-to-3.patch
mt8183-cadmium-improved-kukui.opp-multi-regulator.patch
mt8183-cadmium-kukui.panel-dts-rotation.patch
mt8183-cadmium-kukui.cci-1.patch
mt8183-cadmium-kukui.panel-dts-rotation_sku0.patch
mt8183-cadmium-kukui.cci-2.patch
01-RESEND-v2-1-2-drm-panel-Add-inx-Himax8279d-MIPI-DSI-LCD-panel-driver.patch
03-v2-1-4-arm64-dts-mt8183-Add-katsu-board.patch
04-v2-2-4-arm64-dts-mt8183-Add-kukui-jacuzzi-makomo-board.patch
05-v2-3-4-dt-bindings-arm64-dts-mediatek-Add-mt8183-kukui-katsu.patch
06-v2-4-4-dt-bindings-arm64-dts-mediatek-Add-mt8183-kukui-jacuzzi-makomo.patch
07-1-2-arm64-dts-mt8183-Add-kukui-jacuzzi-cerise-board.patch
08-2-2-dt-bindings-arm64-dts-mediatek-Add-mt8183-kukui-jacuzzi-cerise.patch
09-add-new-dtbs-to-makefile.patch
mt8183-cadmium-kukui.enable-ite.patch
mt8183-fix-audio-module-loading.patch
mt8183-fix-bluetooth.patch
mt8183-cadmium-kukui.cci-3.patch
mt8183-kukui-disable-unsupported-thermal-zones.patch
mt8183-cadmium-kukui.cci-4.patch
mt8183-kukui-jacuzzi-fennel14-rt1015p-sound.patch
mt8183-cadmium-kukui.cci-5.patch
mt8183-kukui-jacuzzi-fix-anx7625-01.patch
mt8183-cadmium-kukui.cci-6.patch
mt8183-kukui-jacuzzi-fix-anx7625-04.patch
mt8183-cadmium-kukui.cci-7.patch
mt8183-kukui-jacuzzi-fix-display-resume.patch
mt8183-cadmium-kukui.cci-8.patch
mt8183-kukui-jacuzzi-hack-dpms-resume.patch
mt8183-cadmium-kukui.gpu-vsram.patch
mt8183-panel-orientation.patch
mt81xx-fix-low-speed-usb-devices.patch
mt81xx-usb-02.patch
config-$_flavor.aarch64
"
builddir="$srcdir/linux-$_kernver"
@ -80,9 +71,8 @@ prepare() {
build() {
unset LDFLAGS
# V=1: workaround for pma#1990
make ARCH="$_carch" \
KBUILD_BUILD_VERSION="$((pkgrel + 1 ))-$_flavor" V=1
KBUILD_BUILD_VERSION="$((pkgrel + 1 ))-$_flavor"
}
package() {
@ -102,33 +92,23 @@ package() {
sha512sums="
dbbc9d1395898a498fa4947fceda1781344fa5d360240f753810daa4fa88e519833e2186c4e582a8f1836e6413e9e85f6563c7770523b704e8702d67622f98b5 linux-5.18.tar.xz
3c2b433fc1e3514f4d32e2ddd811f5536958857da55ab22f98278b91733b8b1a06945665df0deadaf57a0458d248dc659e1dcdf5a196ce49d7a3c704cb313878 0001-drm-panel-Add-inx-Himax8279d-MIPI-DSI-LCD-panel-driv.patch
c0b38b2d4b827cf34b8474d78f588528e1aa665ed091301c0bd970ae10aba642551d7eff9fbea4b7accf0906b41c00f4e1108e1c7573041fea4f2fcd13045c65 0002-arm64-dts-mt8183-Add-katsu-board.patch
385fe4f278f16af63ad416c195366974d0fad6ca3eaa63e4ccf052175f183ec0da263d4b5964273420bd4e1e5d1a0761f170f38e7c941ee617a8ccab84d6cf21 0003-arm64-dts-mt8183-Add-kukui-jacuzzi-makomo-board.patch
2748f1f3ec84de63a2d4a7a254cefdd88ccd52d70193d268f55df8a0b51b4d288ffa3153e16d15a27d60eaa4552132090901633b49d0b062f8a3b11447efe8f9 0004-dt-bindings-arm64-dts-mediatek-Add-mt8183-kukui-kats.patch
912519749bcdac4ee13178078e3bcef5a3a64d9527a368dd39e387224c21c01f3d54586728585f434147cbc507e5906c41e5f3597f2a975dca7468b0e7e96b90 0005-dt-bindings-arm64-dts-mediatek-Add-mt8183-kukui-jacu.patch
efbb379c2c0e14116a4a941993fb4df243dde9d7477177e903b283356ebaa57ee78a685632effbb43208f25a5e490779385a36dcb1b19e96eadb46547b2c85db mt8183-cadmium-improved-kukui.gpu.patch
e79b5b652bfb44e7fc293d08c3b5355a8f6456389c05c29167cfaf5bf45cf19555f2b2e50aca8e93e8876f64ed09d63e0483f5b8c492a47d9d2e3e72413c4e45 mt8183-cadmium-kukui.move-gpu-opp-to-3.patch
0252db7a1e3b6b041b351aaa17323e45e286b41b369945be483b4ce2be2fa6600124d12b8871e3bea50ca07949e12e90e9cc7c8a3a37ad19cd02677eb7bebd89 mt8183-cadmium-improved-kukui.opp-multi-regulator.patch
ca3584808a2b27854d50d2c8cd3ba3306334302803e5684b19b338473011f7aa210f326232e2dbd364b2a9c5ad68db0b8443fe9c0b141cd8b596ba36db336595 mt8183-cadmium-kukui.panel-dts-rotation.patch
34f72f57e7b1a5b4800c514a4443e2815dee6d14566990a75a9389aa1bec2f42c3dd7e4992ea4733d57e0515756f1f79d3298fab1ac66a9628dc3f8236dedf07 mt8183-cadmium-kukui.cci-1.patch
de3968b5a4ab7e9b60a81ebc9845849a3b2fd23cfea8ca91d953322f3d0f64c978361217fe8327e16622fcc4f05f979b21c798b55eb1b6fe22cee531a5321a16 mt8183-cadmium-kukui.panel-dts-rotation_sku0.patch
558611e9bbe11c99c4b70cb4d4882bc9a7b796575a553d3659953146f8c45c3c72b8e9cccd2606cacf17ff6501388fde01488e8eeae0706da51e74a356010474 mt8183-cadmium-kukui.cci-2.patch
7215e62df10847e8bce432880e0756e8a5f56eb8b8abb54f9e1eb8871ce7bd56d765be0f9a40a8dae4d135b2f9a0dab7f6b3d2691d73b0c47f05811194dee8bd linux-6.1.28.tar.xz
06e901fd36d4c3a8b51673ed6682a51229856259a4a0c83e65ed10a234c24a4a8828e9f6ed3101713470a25db10af9d5bab29c480b7f5c87af6bd7e81d8c0fe7 01-RESEND-v2-1-2-drm-panel-Add-inx-Himax8279d-MIPI-DSI-LCD-panel-driver.patch
4c7a89fd1e3e7b4589fe3c2addc7c4963cec7ebabf49413b1d6db92386b4b2ba7bf25c961aaa53fc344a4684871b4132806aa4b8c1a63e091651e548bab750ef 03-v2-1-4-arm64-dts-mt8183-Add-katsu-board.patch
a0742fa788d13c836d9dc8827c55a14e804ce77234627f2689fd511b14e5fba17b00f5a8cebd9ae4fa4c644d87cc98d4f18eba385ec4f57bb6fe07d3aff057fd 04-v2-2-4-arm64-dts-mt8183-Add-kukui-jacuzzi-makomo-board.patch
7d29cefe1e338868c6f31516dcff73ef1fdb5e50353ffd0874018bee1c9c116dea65b0bea6e9a5d31f416958ff025a685234e684557705f4675ad4710709e197 05-v2-3-4-dt-bindings-arm64-dts-mediatek-Add-mt8183-kukui-katsu.patch
53279b9019c4aa94488405a823c501734f536acc6f68c7d89f3f76fba04cde897c229ab59d22e97acd68f8ab9fc75ad39bb74fef777a1dbbdf1788bf19ae52c4 06-v2-4-4-dt-bindings-arm64-dts-mediatek-Add-mt8183-kukui-jacuzzi-makomo.patch
20be60004e19068e652010f18353f93a289b109a4b13cfa85184401a13f02417aea644e29accf5c21d6cf511044f2024e3872b211512d15e301ca34613ee0077 07-1-2-arm64-dts-mt8183-Add-kukui-jacuzzi-cerise-board.patch
27e1e536f446dc278ce8a9dd9bd64e5ec6678589b2ca276be7bab5e0a80f119052e9109e6834357a57bbffe30fda48e03d24531f53ad0225f42ad075142f3a37 08-2-2-dt-bindings-arm64-dts-mediatek-Add-mt8183-kukui-jacuzzi-cerise.patch
604fb37887786a2919e93648fb3fd002ce4b948b35a915931e3f2bf3f3a1451fad4f6e042cd0fd9aa7f11bba5864f1b95c9be9ab6aed57a63652c49a7a145a3e 09-add-new-dtbs-to-makefile.patch
4216543acf0ffea0c91b2b7c112cd333be838414f2902cea9f07f5811b96ab5da0e09954086966359316fe0632ac0af65add154b9df0aa11d05962429954e362 mt8183-cadmium-kukui.enable-ite.patch
b9a9e2f620d229ca8acf2df764d6406a304fd51f435929f78c4dfd7f52cd6f1f298f031bb6d7bb7fc8ea360dd8bbd4584bb298f9351100dfb20707de50076244 mt8183-fix-audio-module-loading.patch
d74da1231181835bec82015da1b3f5b08a1fe9c3c35dd712e285891094d94d9427ceac75d32f74be3a635e17d93ad82b37adf97db8176efc91aed17535023fc2 mt8183-fix-bluetooth.patch
0dab1f6e377de6f5593fe26078d8aaa65017fef405f99f33c172bc73f252138d0db394bec93bed4650aee74f57186f81b6c78fc408b345b47d80d3ea6acf95aa mt8183-cadmium-kukui.cci-3.patch
a5e99ea30bbdde3a5f0f9745306c9f58876a60489c3cbeacd783cf7e47a013d47c9fb77e4a9dbbd34ec6307d40e64a3623e3cece2f254f734979987f5a22e700 mt8183-kukui-disable-unsupported-thermal-zones.patch
000e2f5a84a2fd436f100b4325812cadaba2c9fb820ce26ca26961fb16e2941b13ca14c272d8575d05f1e4541a5d324f78a17dc421b54a551ea73067dd7044a4 mt8183-cadmium-kukui.cci-4.patch
9b8707de42635734031495da055c5860addeb656051540f1a14404b10aa8b501168d8b0e274b37bce989db3bc050e9beef722189556f6d782b92cc907731488d mt8183-kukui-jacuzzi-fennel14-rt1015p-sound.patch
538672cfd0401b1da7751b101b02639dea9f27e81f7f537b2f4b7b05d13878f61213a4933e74f8d3102fa93f13eca0faad19699d79568552a1b54969ac66b243 mt8183-cadmium-kukui.cci-5.patch
7e73fd6ac2efa90f64dce5f631475b726c68a059805ab9ceba216eaae672db07f18c5f8e06a32f78d25153c5e4ce6a3dafc0d124c0994d3cae61f074f8e84f53 mt8183-kukui-jacuzzi-fix-anx7625-01.patch
ba8eeb470e55a279d0cb42608443c99056da7bfbf4b1ca022a6449703cea4be5640e71edf110eaae9839d0fda1a6ca242e4a152cb8014c6451b18968a1dbcf07 mt8183-cadmium-kukui.cci-6.patch
88560c512a328a7d142f62eb6b74a23d01741667bd731fce6b96a968595d641dcfd8aeb3b26c797d333a2eaeec218c033dc710eace4080d8324b99ff55dab47f mt8183-kukui-jacuzzi-fix-anx7625-04.patch
8e2bee598a6f7110d1e198e17ee5b8137f4029abdb651debb8a3e6204bb389485720b532fb07ab6075c432a68ffaacfd17f9c0b6c1bf9265e209dafb8a8d4982 mt8183-cadmium-kukui.cci-7.patch
cd629355bb9b172a7e68d7334dc2a97f040f8d5757c835e064a8706e9cf5a31b91023ca6e0ef23e56a9965e19ceca61332a5fcf2a0b1cce420a90bbbc0425531 mt8183-kukui-jacuzzi-fix-display-resume.patch
f0e78266b8d5db67476ca47fc115830d4296182486d88744d714b05bed35c4976b82a59a7aa4fb36144adb38980b8633e89830411ed073a2461dee63659b8652 mt8183-cadmium-kukui.cci-8.patch
519b6468bca78d0e315c826592ae40dddca9daeba7c2b451a20ca996494cca45721833b9138fefbb543f53e0b9257c78ec4fec54de2a160aa8df730daf3ac996 mt8183-kukui-jacuzzi-fix-display-resume.patch
e9a128a8ddd98c6c8957ba45186afa2ea8ebeac83d4f2db3ff9ee8a5dd8027af90868c334a7b456bfe7dce793517f27ad63efa220bc933e3407f6362da6d7b2a mt8183-kukui-jacuzzi-hack-dpms-resume.patch
8ab89b0845d3aaee9ae5d244e7880601f21b85b159677464960c1e08cf20038db2a8ad1b57c9ed99d817735ad450d0e4d4fe9051cb1808dd08a00e2f68af5028 mt8183-cadmium-kukui.gpu-vsram.patch
863966b986c3680d013ba81e02e2d0a5f092d95ef6d3b60cb6991ca7acc3c4ce5323e528b3190b95e594f72c1b0ae26f7b8db20e118557850161777a90e2b45f mt8183-panel-orientation.patch
5dd10e26aa90b9610a3ac9fa643aed72b727860cfcc949e087bbd1a963256aeb51b8d9785f778c7a766df8d421442c767da9e9b7da0be67a4dc02ff98de7dd8c config-postmarketos-mediatek-mt8183.aarch64
ca1eec5277c3cd8afc2e6079fd4ccfe2f3937cdc8296cafac1d61bb14ca7acdde6e97d561f5a80a919b01fbc06ec991767d3ea1ff4bc34c1d9033993f2689130 mt81xx-fix-low-speed-usb-devices.patch
5db854d3cb1bad58e93eba86014deb1e2cf3b79a1a74561e22832dccf5cd79f6f0c42cc6210926e0dfc4ca9c939b666018cb2ce5612eb49ad84a8b285dc63e07 mt81xx-usb-02.patch
d7ed719bcb8edd394d268a8a9989d8d0c37443ca79f48dc8a1d829cd22925ed1a19f3240089a998d22fa407e92984e66b33facce47463e0475a5d407c747139d config-postmarketos-mediatek-mt8183.aarch64
"

707
device/testing/linux-postmarketos-mediatek-mt8183/config-postmarketos-mediatek-mt8183.aarch64
View file

File diff suppressed because it is too large Load diff

39
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-cadmium-improved-kukui.gpu.patch
View file

@ -1,39 +0,0 @@
this patch is based on:
https://pastebin.com/kwNHAdhu
via: https://oftc.irclog.whitequark.org/panfrost/2022-05-09#30915485
as it is supposed to be an improved version of the older and known to
be broken gpu freq scaling code from cadmium
diff -Nur linux-kukui/arch/arm64/boot/dts/mediatek/mt8183.dtsi linux-kukui-gud/arch/arm64/boot/dts/mediatek/mt8183.dtsi
--- linux-kukui/arch/arm64/boot/dts/mediatek/mt8183.dtsi 2021-07-13 17:16:13.752666183 +0200
+++ linux-kukui-gud/arch/arm64/boot/dts/mediatek/mt8183.dtsi 2021-07-13 17:01:43.516154051 +0200
@@ -1581,7 +1581,15 @@
<GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "job", "mmu", "gpu";
- clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
+ clocks = <&topckgen CLK_TOP_MFGPLL_CK>,
+ <&topckgen CLK_TOP_MUX_MFG>,
+ <&clk26m>,
+ <&mfgcfg CLK_MFG_BG3D>;
+ clock-names =
+ "clk_main_parent",
+ "clk_mux",
+ "clk_sub_parent",
+ "subsys_mfg_cg";
power-domains =
<&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
diff -Nur linux-kukui/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi linux-kukui-gud/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
--- linux-kukui/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi 2021-07-13 17:16:13.756666129 +0200
+++ linux-kukui-gud/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi 2021-07-13 16:53:12.906778709 +0200
@@ -295,6 +295,7 @@
};
&gpu {
+ supply-names = "mali", "sram";
mali-supply = <&mt6358_vgpu_reg>;
sram-supply = <&mt6358_vsram_gpu_reg>;
};

162
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-cadmium-improved-kukui.opp-multi-regulator.patch
View file

@ -1,162 +0,0 @@
this patch is based on:
https://pastebin.com/kwNHAdhu
via: https://oftc.irclog.whitequark.org/panfrost/2022-05-09#30915485
as it is supposed to be an improved version of the older and known to
be broken gpu freq scaling code from cadmium
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index acce9d02dba0..9641769c64d1 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -29,13 +29,34 @@ static int panfrost_devfreq_target(struct device *dev, unsigned long *freq,
u32 flags)
{
struct dev_pm_opp *opp;
+ struct panfrost_device *pfdev = dev_get_drvdata(dev);
+ int ret, err;
+ char needs_reparenting = pfdev->mtk_clk_mux != NULL;
opp = devfreq_recommended_opp(dev, freq, flags);
if (IS_ERR(opp))
return PTR_ERR(opp);
dev_pm_opp_put(opp);
- return dev_pm_opp_set_rate(dev, *freq);
+ if (needs_reparenting) {
+ err = clk_set_parent(pfdev->mtk_clk_mux, pfdev->mtk_clk_sub);
+ if (err) {
+ DRM_DEV_ERROR(dev, "Failed to select sub clock source\n");
+ return err;
+ }
+ }
+
+ ret = dev_pm_opp_set_rate(dev, *freq);
+
+ if (needs_reparenting) {
+ err = clk_set_parent(pfdev->mtk_clk_mux, pfdev->mtk_clk_parent);
+ if (err) {
+ DRM_DEV_ERROR(dev, "Failed to select main clock source\n");
+ return err;
+ }
+ }
+
+ return ret;
}
static void panfrost_devfreq_reset(struct panfrost_devfreq *pfdevfreq)
@@ -91,16 +112,7 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
struct devfreq *devfreq;
struct opp_table *opp_table;
struct thermal_cooling_device *cooling;
- struct panfrost_devfreq *pfdevfreq = &pfdev->pfdevfreq;
-
- if (pfdev->comp->num_supplies > 1) {
- /*
- * GPUs with more than 1 supply require platform-specific handling:
- * continue without devfreq
- */
- DRM_DEV_INFO(dev, "More than 1 supply is not supported yet\n");
- return 0;
- }
+ struct panfrost_devfreq *pfdevfreq = &pfdev->pfdevfreq;
opp_table = dev_pm_opp_set_regulators(dev, pfdev->comp->supply_names,
pfdev->comp->num_supplies);
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c
index a2a09c51eed7..b77d738c7fb8 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.c
+++ b/drivers/gpu/drm/panfrost/panfrost_device.c
@@ -67,6 +67,32 @@ static int panfrost_clk_init(struct panfrost_device *pfdev)
goto disable_clock;
}
+ pfdev->mtk_clk_mux = devm_clk_get_optional(pfdev->dev, "clk_mux");
+ if (pfdev->mtk_clk_mux) {
+ if (IS_ERR(pfdev->mtk_clk_mux)) {
+ dev_err(pfdev->dev, "get clk_mux failed %ld\n",
+ PTR_ERR(pfdev->mtk_clk_mux));
+ err = PTR_ERR(pfdev->mtk_clk_mux);
+ goto disable_clock;
+ }
+
+ pfdev->mtk_clk_parent = devm_clk_get(pfdev->dev, "clk_main_parent");
+ if (IS_ERR(pfdev->mtk_clk_parent)) {
+ dev_err(pfdev->dev, "get clk_main_parent failed %ld\n",
+ PTR_ERR(pfdev->mtk_clk_parent));
+ err = PTR_ERR(pfdev->mtk_clk_parent);
+ goto disable_clock;
+ }
+
+ pfdev->mtk_clk_sub = devm_clk_get(pfdev->dev, "clk_sub_parent");
+ if (IS_ERR(pfdev->mtk_clk_sub)) {
+ dev_err(pfdev->dev, "get clk_sub_parent failed %ld\n",
+ PTR_ERR(pfdev->mtk_clk_sub));
+ err = PTR_ERR(pfdev->mtk_clk_sub);
+ goto disable_clock;
+ }
+ }
+
return 0;
disable_clock:
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h
index 8b2cdb8c701d..410b6099fea9 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.h
+++ b/drivers/gpu/drm/panfrost/panfrost_device.h
@@ -84,6 +84,9 @@ struct panfrost_device {
void __iomem *iomem;
struct clk *clock;
struct clk *bus_clock;
+ struct clk *mtk_clk_mux;
+ struct clk *mtk_clk_parent;
+ struct clk *mtk_clk_sub;
struct regulator_bulk_data *regulators;
struct reset_control *rstc;
/* pm_domains for devices with more than one. */
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index 65df3a106cf5..a3534dd83a00 100644
--- a/drivers/opp/core.c
+++ b/drivers/opp/core.c
@@ -784,18 +784,15 @@ static int _generic_set_opp_regulator(struct opp_table *opp_table,
struct regulator *reg = opp_table->regulators[0];
struct dev_pm_opp *old_opp = opp_table->current_opp;
int ret;
-
- /* This function only supports single regulator per device */
- if (WARN_ON(opp_table->regulator_count > 1)) {
- dev_err(dev, "multiple regulators are not supported\n");
- return -EINVAL;
- }
+ unsigned i;
/* Scaling up? Scale voltage before frequency */
if (!scaling_down) {
- ret = _set_opp_voltage(dev, reg, opp->supplies);
- if (ret)
- goto restore_voltage;
+ for (i = 0; i < opp_table->regulator_count; i++) {
+ ret = _set_opp_voltage(dev, opp_table->regulators[i], &opp->supplies[i]);
+ if (ret)
+ goto restore_voltage;
+ }
}
/* Change frequency */
@@ -805,9 +802,11 @@ static int _generic_set_opp_regulator(struct opp_table *opp_table,
/* Scaling down? Scale voltage after frequency */
if (scaling_down) {
- ret = _set_opp_voltage(dev, reg, opp->supplies);
- if (ret)
- goto restore_freq;
+ for (i = 0; i < opp_table->regulator_count; i++) {
+ ret = _set_opp_voltage(dev, opp_table->regulators[i], &opp->supplies[i]);
+ if (ret)
+ goto restore_freq;
+ }
}
/*
--

457
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-cadmium-kukui.cci-1.patch
View file

@ -1,457 +0,0 @@
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 00704efe6398..f56132b0ae64 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -73,6 +73,8 @@ config DEVFREQ_GOV_PASSIVE
device. This governor does not change the frequency by itself
through sysfs entries. The passive governor recommends that
devfreq device uses the OPP table to get the frequency/voltage.
+ Alternatively the governor can also be chosen to scale based on
+ the online CPUs current frequency.
comment "DEVFREQ Drivers"
diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c
index b094132bd20b..9cc57b083839 100644
--- a/drivers/devfreq/governor_passive.c
+++ b/drivers/devfreq/governor_passive.c
@@ -8,11 +8,103 @@
*/
#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/cpufreq.h>
+#include <linux/cpumask.h>
#include <linux/device.h>
#include <linux/devfreq.h>
+#include <linux/slab.h>
#include "governor.h"
-static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
+struct devfreq_cpu_state {
+ unsigned int curr_freq;
+ unsigned int min_freq;
+ unsigned int max_freq;
+ unsigned int first_cpu;
+ struct device *cpu_dev;
+ struct opp_table *opp_table;
+};
+
+static unsigned long xlate_cpufreq_to_devfreq(struct devfreq_passive_data *data,
+ unsigned int cpu)
+{
+ unsigned int cpu_min_freq, cpu_max_freq, cpu_curr_freq_khz, cpu_percent;
+ unsigned long dev_min_freq, dev_max_freq, dev_max_state;
+
+ struct devfreq_cpu_state *cpu_state = data->cpu_state[cpu];
+ struct devfreq *devfreq = (struct devfreq *)data->this;
+ unsigned long *dev_freq_table = devfreq->profile->freq_table;
+ struct dev_pm_opp *opp = NULL, *p_opp = NULL;
+ unsigned long cpu_curr_freq, freq;
+
+ if (!cpu_state || cpu_state->first_cpu != cpu ||
+ !cpu_state->opp_table || !devfreq->opp_table)
+ return 0;
+
+ cpu_curr_freq = cpu_state->curr_freq * 1000;
+ p_opp = devfreq_recommended_opp(cpu_state->cpu_dev, &cpu_curr_freq, 0);
+ if (IS_ERR(p_opp))
+ return 0;
+
+ opp = dev_pm_opp_xlate_required_opp(cpu_state->opp_table,
+ devfreq->opp_table, p_opp);
+ dev_pm_opp_put(p_opp);
+
+ if (!IS_ERR(opp)) {
+ freq = dev_pm_opp_get_freq(opp);
+ dev_pm_opp_put(opp);
+ goto out;
+ }
+
+ /* Use Interpolation if required opps is not available */
+ cpu_min_freq = cpu_state->min_freq;
+ cpu_max_freq = cpu_state->max_freq;
+ cpu_curr_freq_khz = cpu_state->curr_freq;
+
+ if (dev_freq_table) {
+ /* Get minimum frequency according to sorting order */
+ dev_max_state = dev_freq_table[devfreq->profile->max_state - 1];
+ if (dev_freq_table[0] < dev_max_state) {
+ dev_min_freq = dev_freq_table[0];
+ dev_max_freq = dev_max_state;
+ } else {
+ dev_min_freq = dev_max_state;
+ dev_max_freq = dev_freq_table[0];
+ }
+ } else {
+ dev_min_freq = dev_pm_qos_read_value(devfreq->dev.parent,
+ DEV_PM_QOS_MIN_FREQUENCY);
+ dev_max_freq = dev_pm_qos_read_value(devfreq->dev.parent,
+ DEV_PM_QOS_MAX_FREQUENCY);
+
+ if (dev_max_freq <= dev_min_freq)
+ return 0;
+ }
+ cpu_percent = ((cpu_curr_freq_khz - cpu_min_freq) * 100) / cpu_max_freq - cpu_min_freq;
+ freq = dev_min_freq + mult_frac(dev_max_freq - dev_min_freq, cpu_percent, 100);
+
+out:
+ return freq;
+}
+
+static int get_target_freq_with_cpufreq(struct devfreq *devfreq,
+ unsigned long *freq)
+{
+ struct devfreq_passive_data *p_data =
+ (struct devfreq_passive_data *)devfreq->data;
+ unsigned int cpu;
+ unsigned long target_freq = 0;
+
+ for_each_online_cpu(cpu)
+ target_freq = max(target_freq,
+ xlate_cpufreq_to_devfreq(p_data, cpu));
+
+ *freq = target_freq;
+
+ return 0;
+}
+
+static int get_target_freq_with_devfreq(struct devfreq *devfreq,
unsigned long *freq)
{
struct devfreq_passive_data *p_data
@@ -23,14 +115,6 @@ static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
int i, count;
/*
- * If the devfreq device with passive governor has the specific method
- * to determine the next frequency, should use the get_target_freq()
- * of struct devfreq_passive_data.
- */
- if (p_data->get_target_freq)
- return p_data->get_target_freq(devfreq, freq);
-
- /*
* If the parent and passive devfreq device uses the OPP table,
* get the next frequency by using the OPP table.
*/
@@ -98,6 +182,37 @@ static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
return 0;
}
+static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
+ unsigned long *freq)
+{
+ struct devfreq_passive_data *p_data =
+ (struct devfreq_passive_data *)devfreq->data;
+ int ret;
+
+ /*
+ * If the devfreq device with passive governor has the specific method
+ * to determine the next frequency, should use the get_target_freq()
+ * of struct devfreq_passive_data.
+ */
+ if (p_data->get_target_freq)
+ return p_data->get_target_freq(devfreq, freq);
+
+ switch (p_data->parent_type) {
+ case DEVFREQ_PARENT_DEV:
+ ret = get_target_freq_with_devfreq(devfreq, freq);
+ break;
+ case CPUFREQ_PARENT_DEV:
+ ret = get_target_freq_with_cpufreq(devfreq, freq);
+ break;
+ default:
+ ret = -EINVAL;
+ dev_err(&devfreq->dev, "Invalid parent type\n");
+ break;
+ }
+
+ return ret;
+}
+
static int devfreq_passive_notifier_call(struct notifier_block *nb,
unsigned long event, void *ptr)
{
@@ -130,16 +245,200 @@ static int devfreq_passive_notifier_call(struct notifier_block *nb,
return NOTIFY_DONE;
}
+static int cpufreq_passive_notifier_call(struct notifier_block *nb,
+ unsigned long event, void *ptr)
+{
+ struct devfreq_passive_data *data =
+ container_of(nb, struct devfreq_passive_data, nb);
+ struct devfreq *devfreq = (struct devfreq *)data->this;
+ struct devfreq_cpu_state *cpu_state;
+ struct cpufreq_freqs *cpu_freq = ptr;
+ unsigned int curr_freq;
+ int ret;
+
+ if (event != CPUFREQ_POSTCHANGE || !cpu_freq ||
+ !data->cpu_state[cpu_freq->policy->cpu])
+ return 0;
+
+ cpu_state = data->cpu_state[cpu_freq->policy->cpu];
+ if (cpu_state->curr_freq == cpu_freq->new)
+ return 0;
+
+ /* Backup current freq and pre-update cpu state freq*/
+ curr_freq = cpu_state->curr_freq;
+ cpu_state->curr_freq = cpu_freq->new;
+
+ mutex_lock(&devfreq->lock);
+ ret = update_devfreq(devfreq);
+ mutex_unlock(&devfreq->lock);
+ if (ret) {
+ cpu_state->curr_freq = curr_freq;
+ dev_err(&devfreq->dev, "Couldn't update the frequency.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int cpufreq_passive_register(struct devfreq_passive_data **p_data)
+{
+ struct devfreq_passive_data *data = *p_data;
+ struct devfreq *devfreq = (struct devfreq *)data->this;
+ struct device *dev = devfreq->dev.parent;
+ struct opp_table *opp_table = NULL;
+ struct devfreq_cpu_state *cpu_state;
+ struct cpufreq_policy *policy;
+ struct device *cpu_dev;
+ unsigned int cpu;
+ int ret;
+
+ cpus_read_lock();
+
+ data->nb.notifier_call = cpufreq_passive_notifier_call;
+ ret = cpufreq_register_notifier(&data->nb,
+ CPUFREQ_TRANSITION_NOTIFIER);
+ if (ret) {
+ dev_err(dev, "Couldn't register cpufreq notifier.\n");
+ data->nb.notifier_call = NULL;
+ goto out;
+ }
+
+ /* Populate devfreq_cpu_state */
+ for_each_online_cpu(cpu) {
+ if (data->cpu_state[cpu])
+ continue;
+
+ policy = cpufreq_cpu_get(cpu);
+ if (!policy) {
+ ret = -EINVAL;
+ goto out;
+ } else if (PTR_ERR(policy) == -EPROBE_DEFER) {
+ ret = -EPROBE_DEFER;
+ goto out;
+ } else if (IS_ERR(policy)) {
+ ret = PTR_ERR(policy);
+ dev_err(dev, "Couldn't get the cpufreq_poliy.\n");
+ goto out;
+ }
+
+ cpu_state = kzalloc(sizeof(*cpu_state), GFP_KERNEL);
+ if (!cpu_state) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ cpu_dev = get_cpu_device(cpu);
+ if (!cpu_dev) {
+ dev_err(dev, "Couldn't get cpu device.\n");
+ ret = -ENODEV;
+ goto out;
+ }
+
+ opp_table = dev_pm_opp_get_opp_table(cpu_dev);
+ if (IS_ERR(devfreq->opp_table)) {
+ ret = PTR_ERR(opp_table);
+ goto out;
+ }
+
+ cpu_state->cpu_dev = cpu_dev;
+ cpu_state->opp_table = opp_table;
+ cpu_state->first_cpu = cpumask_first(policy->related_cpus);
+ cpu_state->curr_freq = policy->cur;
+ cpu_state->min_freq = policy->cpuinfo.min_freq;
+ cpu_state->max_freq = policy->cpuinfo.max_freq;
+ data->cpu_state[cpu] = cpu_state;
+
+ cpufreq_cpu_put(policy);
+ }
+
+out:
+ cpus_read_unlock();
+ if (ret)
+ return ret;
+
+ /* Update devfreq */
+ mutex_lock(&devfreq->lock);
+ ret = update_devfreq(devfreq);
+ mutex_unlock(&devfreq->lock);
+ if (ret)
+ dev_err(dev, "Couldn't update the frequency.\n");
+
+ return ret;
+}
+
+static int cpufreq_passive_unregister(struct devfreq_passive_data **p_data)
+{
+ struct devfreq_passive_data *data = *p_data;
+ struct devfreq_cpu_state *cpu_state;
+ int cpu;
+
+ if (data->nb.notifier_call)
+ cpufreq_unregister_notifier(&data->nb,
+ CPUFREQ_TRANSITION_NOTIFIER);
+
+ for_each_possible_cpu(cpu) {
+ cpu_state = data->cpu_state[cpu];
+ if (cpu_state) {
+ if (cpu_state->opp_table)
+ dev_pm_opp_put_opp_table(cpu_state->opp_table);
+ kfree(cpu_state);
+ cpu_state = NULL;
+ }
+ }
+
+ return 0;
+}
+
+int register_parent_dev_notifier(struct devfreq_passive_data **p_data)
+{
+ struct notifier_block *nb = &(*p_data)->nb;
+ int ret = 0;
+
+ switch ((*p_data)->parent_type) {
+ case DEVFREQ_PARENT_DEV:
+ nb->notifier_call = devfreq_passive_notifier_call;
+ ret = devfreq_register_notifier((struct devfreq *)(*p_data)->parent, nb,
+ DEVFREQ_TRANSITION_NOTIFIER);
+ break;
+ case CPUFREQ_PARENT_DEV:
+ ret = cpufreq_passive_register(p_data);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
+int unregister_parent_dev_notifier(struct devfreq_passive_data **p_data)
+{
+ int ret = 0;
+
+ switch ((*p_data)->parent_type) {
+ case DEVFREQ_PARENT_DEV:
+ WARN_ON(devfreq_unregister_notifier((struct devfreq *)(*p_data)->parent,
+ &(*p_data)->nb,
+ DEVFREQ_TRANSITION_NOTIFIER));
+ break;
+ case CPUFREQ_PARENT_DEV:
+ cpufreq_passive_unregister(p_data);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
static int devfreq_passive_event_handler(struct devfreq *devfreq,
unsigned int event, void *data)
{
struct devfreq_passive_data *p_data
= (struct devfreq_passive_data *)devfreq->data;
struct devfreq *parent = (struct devfreq *)p_data->parent;
- struct notifier_block *nb = &p_data->nb;
int ret = 0;
- if (!parent)
+ if (p_data->parent_type == DEVFREQ_PARENT_DEV && !parent)
return -EPROBE_DEFER;
switch (event) {
@@ -147,13 +446,11 @@ static int devfreq_passive_event_handler(struct devfreq *devfreq,
if (!p_data->this)
p_data->this = devfreq;
- nb->notifier_call = devfreq_passive_notifier_call;
- ret = devfreq_register_notifier(parent, nb,
- DEVFREQ_TRANSITION_NOTIFIER);
+ ret = register_parent_dev_notifier(&p_data);
break;
+
case DEVFREQ_GOV_STOP:
- WARN_ON(devfreq_unregister_notifier(parent, nb,
- DEVFREQ_TRANSITION_NOTIFIER));
+ ret = unregister_parent_dev_notifier(&p_data);
break;
default:
break;
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index 26ea0850be9b..e0093b7c805c 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -280,6 +280,25 @@ struct devfreq_simple_ondemand_data {
#if IS_ENABLED(CONFIG_DEVFREQ_GOV_PASSIVE)
/**
+ * struct devfreq_cpu_state - holds the per-cpu state
+ * @freq: the current frequency of the cpu.
+ * @min_freq: the min frequency of the cpu.
+ * @max_freq: the max frequency of the cpu.
+ * @first_cpu: the cpumask of the first cpu of a policy.
+ * @dev: reference to cpu device.
+ * @opp_table: reference to cpu opp table.
+ *
+ * This structure stores the required cpu_state of a cpu.
+ * This is auto-populated by the governor.
+ */
+struct devfreq_cpu_state;
+
+enum devfreq_parent_dev_type {
+ DEVFREQ_PARENT_DEV,
+ CPUFREQ_PARENT_DEV,
+};
+
+/**
* struct devfreq_passive_data - ``void *data`` fed to struct devfreq
* and devfreq_add_device
* @parent: the devfreq instance of parent device.
@@ -290,13 +309,15 @@ struct devfreq_simple_ondemand_data {
* using governors except for passive governor.
* If the devfreq device has the specific method to decide
* the next frequency, should use this callback.
+ * @parent_type: parent type of the device
* @this: the devfreq instance of own device.
* @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER list
+ * @cpu_state: the state min/max/current frequency of all online cpu's
*
* The devfreq_passive_data have to set the devfreq instance of parent
* device with governors except for the passive governor. But, don't need to
- * initialize the 'this' and 'nb' field because the devfreq core will handle
- * them.
+ * initialize the 'this', 'nb' and 'cpu_state' field because the devfreq core
+ * will handle them.
*/
struct devfreq_passive_data {
/* Should set the devfreq instance of parent device */
@@ -305,9 +326,13 @@ struct devfreq_passive_data {
/* Optional callback to decide the next frequency of passvice device */
int (*get_target_freq)(struct devfreq *this, unsigned long *freq);
+ /* Should set the type of parent device */
+ enum devfreq_parent_dev_type parent_type;
+
/* For passive governor's internal use. Don't need to set them */
struct devfreq *this;
struct notifier_block nb;
+ struct devfreq_cpu_state *cpu_state[NR_CPUS];
};
#endif

76
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-cadmium-kukui.cci-2.patch
View file

@ -1,76 +0,0 @@
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index f2e491b25b07..432368707ea6 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -350,6 +350,11 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
ret = PTR_ERR(proc_reg);
goto out_free_resources;
}
+ ret = regulator_enable(proc_reg);
+ if (ret) {
+ pr_warn("enable vproc for cpu%d fail\n", cpu);
+ goto out_free_resources;
+ }
/* Both presence and absence of sram regulator are valid cases. */
sram_reg = regulator_get_exclusive(cpu_dev, "sram");
@@ -368,13 +373,21 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
goto out_free_resources;
}
+ ret = clk_prepare_enable(cpu_clk);
+ if (ret)
+ goto out_free_opp_table;
+
+ ret = clk_prepare_enable(inter_clk);
+ if (ret)
+ goto out_disable_mux_clock;
+
/* Search a safe voltage for intermediate frequency. */
rate = clk_get_rate(inter_clk);
opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
if (IS_ERR(opp)) {
pr_err("failed to get intermediate opp for cpu%d\n", cpu);
ret = PTR_ERR(opp);
- goto out_free_opp_table;
+ goto out_disable_inter_clock;
}
info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
@@ -393,6 +406,12 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
return 0;
+out_disable_inter_clock:
+ clk_disable_unprepare(inter_clk);
+
+out_disable_mux_clock:
+ clk_disable_unprepare(cpu_clk);
+
out_free_opp_table:
dev_pm_opp_of_cpumask_remove_table(&info->cpus);
@@ -411,14 +430,20 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
{
- if (!IS_ERR(info->proc_reg))
+ if (!IS_ERR(info->proc_reg)) {
+ regulator_disable(info->proc_reg);
regulator_put(info->proc_reg);
+ }
if (!IS_ERR(info->sram_reg))
regulator_put(info->sram_reg);
- if (!IS_ERR(info->cpu_clk))
+ if (!IS_ERR(info->cpu_clk)) {
+ clk_disable_unprepare(info->cpu_clk);
clk_put(info->cpu_clk);
- if (!IS_ERR(info->inter_clk))
+ }
+ if (!IS_ERR(info->inter_clk)) {
+ clk_disable_unprepare(info->inter_clk);
clk_put(info->inter_clk);
+ }
dev_pm_opp_of_cpumask_remove_table(&info->cpus);
}

57
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-cadmium-kukui.cci-3.patch
View file

@ -1,57 +0,0 @@
diff --git a/Documentation/devicetree/bindings/devfreq/mt8183-cci.yaml b/Documentation/devicetree/bindings/devfreq/mt8183-cci.yaml
new file mode 100644
index 000000000000..a7341fd94097
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/mt8183-cci.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/devfreq/mt8183-cci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CCI_DEVFREQ driver for MT8183.
+
+maintainers:
+ - Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
+
+description: |
+ This module is used to create CCI DEVFREQ.
+ The performance will depend on both CCI frequency and CPU frequency.
+ For MT8183, CCI co-buck with Little core.
+ Contain CCI opp table for voltage and frequency scaling.
+
+properties:
+ compatible:
+ const: "mediatek,mt8183-cci"
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: "cci"
+
+ operating-points-v2: true
+ opp-table: true
+
+ proc-supply:
+ description:
+ Phandle of the regulator that provides the supply voltage.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - proc-supply
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ cci: cci {
+ compatible = "mediatek,mt8183-cci";
+ clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
+ clock-names = "cci";
+ operating-points-v2 = <&cci_opp>;
+ proc-supply = <&mt6358_vproc12_reg>;
+ };
+

237
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-cadmium-kukui.cci-4.patch
View file

@ -1,237 +0,0 @@
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index f56132b0ae64..2538255ac2c1 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -111,6 +111,16 @@ config ARM_IMX8M_DDRC_DEVFREQ
This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows
adjusting DRAM frequency.
+config ARM_MT8183_CCI_DEVFREQ
+ tristate "MT8183 CCI DEVFREQ Driver"
+ depends on ARM_MEDIATEK_CPUFREQ
+ help
+ This adds a devfreq driver for Cache Coherent Interconnect
+ of Mediatek MT8183, which is shared the same regulator
+ with cpu cluster.
+ It can track buck voltage and update a proper CCI frequency.
+ Use notification to get regulator status.
+
config ARM_TEGRA_DEVFREQ
tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver"
depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index a16333ea7034..991ef7740759 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
+obj-$(CONFIG_ARM_MT8183_CCI_DEVFREQ) += mt8183-cci-devfreq.o
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
diff --git a/drivers/devfreq/mt8183-cci-devfreq.c b/drivers/devfreq/mt8183-cci-devfreq.c
new file mode 100644
index 000000000000..018543db7bae
--- /dev/null
+++ b/drivers/devfreq/mt8183-cci-devfreq.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+
+ * Author: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/devfreq.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/time.h>
+
+#define MAX_VOLT_LIMIT (1150000)
+
+struct cci_devfreq {
+ struct devfreq *devfreq;
+ struct regulator *cpu_reg;
+ struct clk *cci_clk;
+ int old_vproc;
+ unsigned long old_freq;
+};
+
+static int mtk_cci_set_voltage(struct cci_devfreq *cci_df, int vproc)
+{
+ int ret;
+
+ ret = regulator_set_voltage(cci_df->cpu_reg, vproc,
+ MAX_VOLT_LIMIT);
+ if (!ret)
+ cci_df->old_vproc = vproc;
+ return ret;
+}
+
+static int mtk_cci_devfreq_target(struct device *dev, unsigned long *freq,
+ u32 flags)
+{
+ int ret;
+ struct cci_devfreq *cci_df = dev_get_drvdata(dev);
+ struct dev_pm_opp *opp;
+ unsigned long opp_rate, opp_voltage, old_voltage;
+
+ if (!cci_df)
+ return -EINVAL;
+
+ if (cci_df->old_freq == *freq)
+ return 0;
+
+ opp_rate = *freq;
+ opp = devfreq_recommended_opp(dev, &opp_rate, 1);
+ opp_voltage = dev_pm_opp_get_voltage(opp);
+ dev_pm_opp_put(opp);
+
+ old_voltage = cci_df->old_vproc;
+ if (old_voltage == 0)
+ old_voltage = regulator_get_voltage(cci_df->cpu_reg);
+
+ // scale up: set voltage first then freq
+ if (opp_voltage > old_voltage) {
+ ret = mtk_cci_set_voltage(cci_df, opp_voltage);
+ if (ret) {
+ pr_err("cci: failed to scale up voltage\n");
+ return ret;
+ }
+ }
+
+ ret = clk_set_rate(cci_df->cci_clk, *freq);
+ if (ret) {
+ pr_err("%s: failed cci to set rate: %d\n", __func__,
+ ret);
+ mtk_cci_set_voltage(cci_df, old_voltage);
+ return ret;
+ }
+
+ // scale down: set freq first then voltage
+ if (opp_voltage < old_voltage) {
+ ret = mtk_cci_set_voltage(cci_df, opp_voltage);
+ if (ret) {
+ pr_err("cci: failed to scale down voltage\n");
+ clk_set_rate(cci_df->cci_clk, cci_df->old_freq);
+ return ret;
+ }
+ }
+
+ cci_df->old_freq = *freq;
+
+ return 0;
+}
+
+static struct devfreq_dev_profile cci_devfreq_profile = {
+ .target = mtk_cci_devfreq_target,
+};
+
+static int mtk_cci_devfreq_probe(struct platform_device *pdev)
+{
+ struct device *cci_dev = &pdev->dev;
+ struct cci_devfreq *cci_df;
+ struct devfreq_passive_data *passive_data;
+ int ret;
+
+ cci_df = devm_kzalloc(cci_dev, sizeof(*cci_df), GFP_KERNEL);
+ if (!cci_df)
+ return -ENOMEM;
+
+ cci_df->cci_clk = devm_clk_get(cci_dev, "cci_clock");
+ ret = PTR_ERR_OR_ZERO(cci_df->cci_clk);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ dev_err(cci_dev, "failed to get clock for CCI: %d\n",
+ ret);
+ return ret;
+ }
+ cci_df->cpu_reg = devm_regulator_get_optional(cci_dev, "proc");
+ ret = PTR_ERR_OR_ZERO(cci_df->cpu_reg);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ dev_err(cci_dev, "failed to get regulator for CCI: %d\n",
+ ret);
+ return ret;
+ }
+ ret = regulator_enable(cci_df->cpu_reg);
+ if (ret) {
+ dev_err(cci_dev, "enable buck for cci fail\n");
+ return ret;
+ }
+
+ ret = dev_pm_opp_of_add_table(cci_dev);
+ if (ret) {
+ dev_err(cci_dev, "Fail to get OPP table for CCI: %d\n", ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, cci_df);
+
+ passive_data = devm_kzalloc(cci_dev, sizeof(*passive_data), GFP_KERNEL);
+ if (!passive_data) {
+ ret = -ENOMEM;
+ goto err_opp;
+ }
+
+ passive_data->parent_type = CPUFREQ_PARENT_DEV;
+
+ cci_df->devfreq = devm_devfreq_add_device(cci_dev,
+ &cci_devfreq_profile,
+ DEVFREQ_GOV_PASSIVE,
+ passive_data);
+ if (IS_ERR(cci_df->devfreq)) {
+ ret = PTR_ERR(cci_df->devfreq);
+ dev_err(cci_dev, "cannot create cci devfreq device:%d\n", ret);
+ goto err_opp;
+ }
+
+ return 0;
+
+err_opp:
+ dev_pm_opp_of_remove_table(cci_dev);
+ return ret;
+}
+
+static int mtk_cci_devfreq_remove(struct platform_device *pdev)
+{
+ struct device *cci_dev = &pdev->dev;
+ struct cci_devfreq *cci_df;
+ struct notifier_block *opp_nb;
+
+ cci_df = platform_get_drvdata(pdev);
+ opp_nb = &cci_df->opp_nb;
+
+ dev_pm_opp_unregister_notifier(cci_dev, opp_nb);
+ dev_pm_opp_of_remove_table(cci_dev);
+ regulator_disable(cci_df->cpu_reg);
+
+ return 0;
+}
+
+static const __maybe_unused struct of_device_id
+ mediatek_cci_of_match[] = {
+ { .compatible = "mediatek,mt8183-cci" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, mediatek_cci_of_match);
+
+static struct platform_driver cci_devfreq_driver = {
+ .probe = mtk_cci_devfreq_probe,
+ .remove = mtk_cci_devfreq_remove,
+ .driver = {
+ .name = "mediatek-cci-devfreq",
+ .of_match_table = of_match_ptr(mediatek_cci_of_match),
+ },
+};
+
+module_platform_driver(cci_devfreq_driver);
+
+MODULE_DESCRIPTION("Mediatek CCI devfreq driver");
+MODULE_AUTHOR("Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>");
+MODULE_LICENSE("GPL v2");

43
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-cadmium-kukui.cci-5.patch
View file

@ -1,43 +0,0 @@
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 432368707ea6..2a82c36aec21 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -42,6 +42,7 @@ struct mtk_cpu_dvfs_info {
struct list_head list_head;
int intermediate_voltage;
bool need_voltage_tracking;
+ int old_vproc;
};
static LIST_HEAD(dvfs_info_list);
@@ -192,11 +193,16 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
{
+ int ret;
+
if (info->need_voltage_tracking)
- return mtk_cpufreq_voltage_tracking(info, vproc);
+ ret = mtk_cpufreq_voltage_tracking(info, vproc);
else
- return regulator_set_voltage(info->proc_reg, vproc,
- vproc + VOLT_TOL);
+ ret = regulator_set_voltage(info->proc_reg, vproc,
+ MAX_VOLT_LIMIT);
+ if (!ret)
+ info->old_vproc = vproc;
+ return ret;
}
static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
@@ -214,7 +220,9 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
inter_vproc = info->intermediate_voltage;
old_freq_hz = clk_get_rate(cpu_clk);
- old_vproc = regulator_get_voltage(info->proc_reg);
+ old_vproc = info->old_vproc;
+ if (old_vproc == 0)
+ old_vproc = regulator_get_voltage(info->proc_reg);
if (old_vproc < 0) {
pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
return old_vproc;

147
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-cadmium-kukui.cci-6.patch
View file

@ -1,147 +0,0 @@
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 2a82c36aec21..1747b03e3059 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -43,6 +43,10 @@ struct mtk_cpu_dvfs_info {
int intermediate_voltage;
bool need_voltage_tracking;
int old_vproc;
+ struct mutex lock; /* avoid notify and policy race condition */
+ struct notifier_block opp_nb;
+ int opp_cpu;
+ unsigned long opp_freq;
};
static LIST_HEAD(dvfs_info_list);
@@ -239,6 +243,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
vproc = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
+ mutex_lock(&info->lock);
/*
* If the new voltage or the intermediate voltage is higher than the
* current voltage, scale up voltage first.
@@ -250,6 +255,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
pr_err("cpu%d: failed to scale up voltage!\n",
policy->cpu);
mtk_cpufreq_set_voltage(info, old_vproc);
+ mutex_unlock(&info->lock);
return ret;
}
}
@@ -261,6 +267,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
policy->cpu);
mtk_cpufreq_set_voltage(info, old_vproc);
WARN_ON(1);
+ mutex_unlock(&info->lock);
return ret;
}
@@ -271,6 +278,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
policy->cpu);
clk_set_parent(cpu_clk, armpll);
mtk_cpufreq_set_voltage(info, old_vproc);
+ mutex_unlock(&info->lock);
return ret;
}
@@ -281,6 +289,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
policy->cpu);
mtk_cpufreq_set_voltage(info, inter_vproc);
WARN_ON(1);
+ mutex_unlock(&info->lock);
return ret;
}
@@ -296,15 +305,69 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
clk_set_parent(cpu_clk, info->inter_clk);
clk_set_rate(armpll, old_freq_hz);
clk_set_parent(cpu_clk, armpll);
+ mutex_unlock(&info->lock);
return ret;
}
}
+ info->opp_freq = freq_hz;
+ mutex_unlock(&info->lock);
+
return 0;
}
#define DYNAMIC_POWER "dynamic-power-coefficient"
+static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct dev_pm_opp *opp = data;
+ struct dev_pm_opp *new_opp;
+ struct mtk_cpu_dvfs_info *info;
+ unsigned long freq, volt;
+ struct cpufreq_policy *policy;
+ int ret = 0;
+
+ info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
+
+ if (event == OPP_EVENT_ADJUST_VOLTAGE) {
+ freq = dev_pm_opp_get_freq(opp);
+
+ mutex_lock(&info->lock);
+ if (info->opp_freq == freq) {
+ volt = dev_pm_opp_get_voltage(opp);
+ ret = mtk_cpufreq_set_voltage(info, volt);
+ if (ret)
+ dev_err(info->cpu_dev, "failed to scale voltage: %d\n",
+ ret);
+ }
+ mutex_unlock(&info->lock);
+ } else if (event == OPP_EVENT_DISABLE) {
+ freq = dev_pm_opp_get_freq(opp);
+ /* case of current opp item is disabled */
+ if (info->opp_freq == freq) {
+ freq = 1;
+ new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev,
+ &freq);
+ if (!IS_ERR(new_opp)) {
+ dev_pm_opp_put(new_opp);
+ policy = cpufreq_cpu_get(info->opp_cpu);
+ if (policy) {
+ cpufreq_driver_target(policy,
+ freq / 1000,
+ CPUFREQ_RELATION_L);
+ cpufreq_cpu_put(policy);
+ }
+ } else {
+ pr_err("%s: all opp items are disabled\n",
+ __func__);
+ }
+ }
+ }
+
+ return notifier_from_errno(ret);
+}
+
static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
{
struct device *cpu_dev;
@@ -400,11 +463,21 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
+ info->opp_cpu = cpu;
+ info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
+ ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
+ if (ret) {
+ pr_warn("cannot register opp notification\n");
+ goto out_disable_inter_clock;
+ }
+
+ mutex_init(&info->lock);
info->cpu_dev = cpu_dev;
info->proc_reg = proc_reg;
info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg;
info->cpu_clk = cpu_clk;
info->inter_clk = inter_clk;
+ info->opp_freq = clk_get_rate(cpu_clk);
/*
* If SRAM regulator is present, software "voltage tracking" is needed

65
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-cadmium-kukui.cci-7.patch
View file

@ -1,65 +0,0 @@
diff --git a/drivers/devfreq/mt8183-cci-devfreq.c b/drivers/devfreq/mt8183-cci-devfreq.c
index 018543db7bae..6942a48f3f4f 100644
--- a/drivers/devfreq/mt8183-cci-devfreq.c
+++ b/drivers/devfreq/mt8183-cci-devfreq.c
@@ -21,6 +21,7 @@ struct cci_devfreq {
struct clk *cci_clk;
int old_vproc;
unsigned long old_freq;
+ struct notifier_block opp_nb;
};
static int mtk_cci_set_voltage(struct cci_devfreq *cci_df, int vproc)
@@ -89,6 +90,26 @@ static int mtk_cci_devfreq_target(struct device *dev, unsigned long *freq,
return 0;
}
+static int ccidevfreq_opp_notifier(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct dev_pm_opp *opp = data;
+ struct cci_devfreq *cci_df = container_of(nb, struct cci_devfreq,
+ opp_nb);
+ unsigned long freq, volt;
+
+ if (event == OPP_EVENT_ADJUST_VOLTAGE) {
+ freq = dev_pm_opp_get_freq(opp);
+ /* current opp item is changed */
+ if (freq == cci_df->old_freq) {
+ volt = dev_pm_opp_get_voltage(opp);
+ mtk_cci_set_voltage(cci_df, volt);
+ }
+ }
+
+ return 0;
+}
+
static struct devfreq_dev_profile cci_devfreq_profile = {
.target = mtk_cci_devfreq_target,
};
@@ -98,12 +119,15 @@ static int mtk_cci_devfreq_probe(struct platform_device *pdev)
struct device *cci_dev = &pdev->dev;
struct cci_devfreq *cci_df;
struct devfreq_passive_data *passive_data;
+ struct notifier_block *opp_nb;
int ret;
cci_df = devm_kzalloc(cci_dev, sizeof(*cci_df), GFP_KERNEL);
if (!cci_df)
return -ENOMEM;
+ opp_nb = &cci_df->opp_nb;
+
cci_df->cci_clk = devm_clk_get(cci_dev, "cci_clock");
ret = PTR_ERR_OR_ZERO(cci_df->cci_clk);
if (ret) {
@@ -152,6 +176,9 @@ static int mtk_cci_devfreq_probe(struct platform_device *pdev)
goto err_opp;
}
+ opp_nb->notifier_call = ccidevfreq_opp_notifier;
+ dev_pm_opp_register_notifier(cci_dev, opp_nb);
+
return 0;
err_opp:

406
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-cadmium-kukui.cci-8.patch
View file

@ -1,406 +0,0 @@
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index 3249c959f76f..77a591cc09a6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -395,6 +395,42 @@
};
+&cci {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu0 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu1 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu2 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu3 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu4 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu5 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu6 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu7 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
index ff56bcfa3370..b1c3b88c4ac4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
@@ -217,6 +217,10 @@
status = "okay";
};
+&cci {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
&cpu0 {
proc-supply = <&mt6358_vproc12_reg>;
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 80519a145f13..c3dc87b01067 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -41,6 +41,251 @@
rdma1 = &rdma1;
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp0_00 {
+ opp-hz = /bits/ 64 <793000000>;
+ opp-microvolt = <650000>;
+ required-opps = <&opp2_00>;
+ };
+ opp0_01 {
+ opp-hz = /bits/ 64 <910000000>;
+ opp-microvolt = <687500>;
+ required-opps = <&opp2_01>;
+ };
+ opp0_02 {
+ opp-hz = /bits/ 64 <1014000000>;
+ opp-microvolt = <718750>;
+ required-opps = <&opp2_02>;
+ };
+ opp0_03 {
+ opp-hz = /bits/ 64 <1131000000>;
+ opp-microvolt = <756250>;
+ required-opps = <&opp2_03>;
+ };
+ opp0_04 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <800000>;
+ required-opps = <&opp2_04>;
+ };
+ opp0_05 {
+ opp-hz = /bits/ 64 <1326000000>;
+ opp-microvolt = <818750>;
+ required-opps = <&opp2_05>;
+ };
+ opp0_06 {
+ opp-hz = /bits/ 64 <1417000000>;
+ opp-microvolt = <850000>;
+ required-opps = <&opp2_06>;
+ };
+ opp0_07 {
+ opp-hz = /bits/ 64 <1508000000>;
+ opp-microvolt = <868750>;
+ required-opps = <&opp2_07>;
+ };
+ opp0_08 {
+ opp-hz = /bits/ 64 <1586000000>;
+ opp-microvolt = <893750>;
+ required-opps = <&opp2_08>;
+ };
+ opp0_09 {
+ opp-hz = /bits/ 64 <1625000000>;
+ opp-microvolt = <906250>;
+ required-opps = <&opp2_09>;
+ };
+ opp0_10 {
+ opp-hz = /bits/ 64 <1677000000>;
+ opp-microvolt = <931250>;
+ required-opps = <&opp2_10>;
+ };
+ opp0_11 {
+ opp-hz = /bits/ 64 <1716000000>;
+ opp-microvolt = <943750>;
+ required-opps = <&opp2_11>;
+ };
+ opp0_12 {
+ opp-hz = /bits/ 64 <1781000000>;
+ opp-microvolt = <975000>;
+ required-opps = <&opp2_12>;
+ };
+ opp0_13 {
+ opp-hz = /bits/ 64 <1846000000>;
+ opp-microvolt = <1000000>;
+ required-opps = <&opp2_13>;
+ };
+ opp0_14 {
+ opp-hz = /bits/ 64 <1924000000>;
+ opp-microvolt = <1025000>;
+ required-opps = <&opp2_14>;
+ };
+ opp0_15 {
+ opp-hz = /bits/ 64 <1989000000>;
+ opp-microvolt = <1050000>;
+ required-opps = <&opp2_15>;
+ }; };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp1_00 {
+ opp-hz = /bits/ 64 <793000000>;
+ opp-microvolt = <700000>;
+ required-opps = <&opp2_00>;
+ };
+ opp1_01 {
+ opp-hz = /bits/ 64 <910000000>;
+ opp-microvolt = <725000>;
+ required-opps = <&opp2_01>;
+ };
+ opp1_02 {
+ opp-hz = /bits/ 64 <1014000000>;
+ opp-microvolt = <750000>;
+ required-opps = <&opp2_02>;
+ };
+ opp1_03 {
+ opp-hz = /bits/ 64 <1131000000>;
+ opp-microvolt = <775000>;
+ required-opps = <&opp2_03>;
+ };
+ opp1_04 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <800000>;
+ required-opps = <&opp2_04>;
+ };
+ opp1_05 {
+ opp-hz = /bits/ 64 <1326000000>;
+ opp-microvolt = <825000>;
+ required-opps = <&opp2_05>;
+ };
+ opp1_06 {
+ opp-hz = /bits/ 64 <1417000000>;
+ opp-microvolt = <850000>;
+ required-opps = <&opp2_06>;
+ };
+ opp1_07 {
+ opp-hz = /bits/ 64 <1508000000>;
+ opp-microvolt = <875000>;
+ required-opps = <&opp2_07>;
+ };
+ opp1_08 {
+ opp-hz = /bits/ 64 <1586000000>;
+ opp-microvolt = <900000>;
+ required-opps = <&opp2_08>;
+ };
+ opp1_09 {
+ opp-hz = /bits/ 64 <1625000000>;
+ opp-microvolt = <912500>;
+ required-opps = <&opp2_09>;
+ };
+ opp1_10 {
+ opp-hz = /bits/ 64 <1677000000>;
+ opp-microvolt = <931250>;
+ required-opps = <&opp2_10>;
+ };
+ opp1_11 {
+ opp-hz = /bits/ 64 <1716000000>;
+ opp-microvolt = <950000>;
+ required-opps = <&opp2_11>;
+ };
+ opp1_12 {
+ opp-hz = /bits/ 64 <1781000000>;
+ opp-microvolt = <975000>;
+ required-opps = <&opp2_12>;
+ };
+ opp1_13 {
+ opp-hz = /bits/ 64 <1846000000>;
+ opp-microvolt = <1000000>;
+ required-opps = <&opp2_13>;
+ };
+ opp1_14 {
+ opp-hz = /bits/ 64 <1924000000>;
+ opp-microvolt = <1025000>;
+ required-opps = <&opp2_14>;
+ };
+ opp1_15 {
+ opp-hz = /bits/ 64 <1989000000>;
+ opp-microvolt = <1050000>;
+ required-opps = <&opp2_15>;
+ };
+ };
+
+ cci_opp: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp2_00: opp-273000000 {
+ opp-hz = /bits/ 64 <273000000>;
+ opp-microvolt = <650000>;
+ };
+ opp2_01: opp-338000000 {
+ opp-hz = /bits/ 64 <338000000>;
+ opp-microvolt = <687500>;
+ };
+ opp2_02: opp-403000000 {
+ opp-hz = /bits/ 64 <403000000>;
+ opp-microvolt = <718750>;
+ };
+ opp2_03: opp-463000000 {
+ opp-hz = /bits/ 64 <463000000>;
+ opp-microvolt = <756250>;
+ };
+ opp2_04: opp-546000000 {
+ opp-hz = /bits/ 64 <546000000>;
+ opp-microvolt = <800000>;
+ };
+ opp2_05: opp-624000000 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-microvolt = <818750>;
+ };
+ opp2_06: opp-689000000 {
+ opp-hz = /bits/ 64 <689000000>;
+ opp-microvolt = <850000>;
+ };
+ opp2_07: opp-767000000 {
+ opp-hz = /bits/ 64 <767000000>;
+ opp-microvolt = <868750>;
+ };
+ opp2_08: opp-845000000 {
+ opp-hz = /bits/ 64 <845000000>;
+ opp-microvolt = <893750>;
+ };
+ opp2_09: opp-871000000 {
+ opp-hz = /bits/ 64 <871000000>;
+ opp-microvolt = <906250>;
+ };
+ opp2_10: opp-923000000 {
+ opp-hz = /bits/ 64 <923000000>;
+ opp-microvolt = <931250>;
+ };
+ opp2_11: opp-962000000 {
+ opp-hz = /bits/ 64 <962000000>;
+ opp-microvolt = <943750>;
+ };
+ opp2_12: opp-1027000000 {
+ opp-hz = /bits/ 64 <1027000000>;
+ opp-microvolt = <975000>;
+ };
+ opp2_13: opp-1092000000 {
+ opp-hz = /bits/ 64 <1092000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp2_14: opp-1144000000 {
+ opp-hz = /bits/ 64 <1144000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp2_15: opp-1196000000 {
+ opp-hz = /bits/ 64 <1196000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+
+ cci: cci {
+ compatible = "mediatek,mt8183-cci";
+ clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
+ clock-names = "cci_clock";
+ operating-points-v2 = <&cci_opp>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -84,6 +329,10 @@
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -95,6 +344,10 @@
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -106,6 +359,10 @@
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -117,6 +374,10 @@
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -128,6 +389,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -139,6 +404,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -150,6 +419,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -161,6 +434,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};

153
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-cadmium-kukui.enable-ite.patch Normal file
View file

@ -0,0 +1,153 @@
diff -Naur a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi 2022-01-29 22:43:21.564586347 +0000
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi 2022-01-29 22:23:29.179058153 +0000
@@ -1728,6 +1728,17 @@
phy-names = "dphy";
};
+ dpi0: dpi@14015000 {
+ compatible = "mediatek,mt8183-dpi";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DPI_IF>,
+ <&mmsys CLK_MM_DPI_MM>,
+ <&apmixedsys CLK_APMIXED_TVDPLL>;
+ clock-names = "pixel", "engine", "pll";
+ };
+
mutex: mutex@14016000 {
compatible = "mediatek,mt8183-disp-mutex";
reg = <0 0x14016000 0 0x1000>;
diff -Naur a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi 2022-01-29 22:43:21.560586382 +0000
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi 2022-01-29 17:55:54.649273984 +0000
@@ -266,6 +266,18 @@
proc-supply = <&mt6358_vproc11_reg>;
};
+&dpi0 {
+ pinctrl-names = "default", "dpimode";
+ pinctrl-0 = <&dpi_pin_default>;
+ pinctrl-1 = <&dpi_pin_func>;
+ status = "okay";
+ port {
+ dpi_out: endpoint {
+ remote-endpoint = <&it6505_in>;
+ };
+ };
+};
+
&dsi0 {
status = "okay";
#address-cells = <1>;
@@ -325,6 +337,28 @@
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
+
+ it6505dptx: it6505dptx@5c {
+ afe-setting = <1>;
+ compatible = "ite,it6505";
+ status = "okay";
+ interrupt-parent = <&pio>;
+ interrupts = <152 IRQ_TYPE_EDGE_FALLING 152 0>;
+ reg = <0x5c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&it6505_pins>;
+ ovdd-supply = <&mt6358_vsim2_reg>;
+ pwr18-supply = <&it6505_pp18_reg>;
+ reset-gpios = <&pio 179 1>;
+ hpd-gpios = <&pio 9 0>;
+ extcon = <&usbc_extcon>;
+ no-laneswap;
+ port {
+ it6505_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+ };
};
&i2c5 {
@@ -473,6 +507,50 @@
};
};
+ dpi_pin_default: dpi_pin_default {
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO13__FUNC_GPIO13>,
+ <PINMUX_GPIO14__FUNC_GPIO14>,
+ <PINMUX_GPIO15__FUNC_GPIO15>,
+ <PINMUX_GPIO16__FUNC_GPIO16>,
+ <PINMUX_GPIO17__FUNC_GPIO17>,
+ <PINMUX_GPIO18__FUNC_GPIO18>,
+ <PINMUX_GPIO19__FUNC_GPIO19>,
+ <PINMUX_GPIO20__FUNC_GPIO20>,
+ <PINMUX_GPIO21__FUNC_GPIO21>,
+ <PINMUX_GPIO22__FUNC_GPIO22>,
+ <PINMUX_GPIO23__FUNC_GPIO23>,
+ <PINMUX_GPIO24__FUNC_GPIO24>,
+ <PINMUX_GPIO25__FUNC_GPIO25>,
+ <PINMUX_GPIO26__FUNC_GPIO26>,
+ <PINMUX_GPIO27__FUNC_GPIO27>,
+ <PINMUX_GPIO28__FUNC_GPIO28>;
+ drive-strength = <MTK_DRIVE_6mA>;
+ output-low;
+ };
+ };
+ dpi_pin_func: dpi_pin_func {
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO13__FUNC_DBPI_D0>,
+ <PINMUX_GPIO14__FUNC_DBPI_D1>,
+ <PINMUX_GPIO15__FUNC_DBPI_D2>,
+ <PINMUX_GPIO16__FUNC_DBPI_D3>,
+ <PINMUX_GPIO17__FUNC_DBPI_D4>,
+ <PINMUX_GPIO18__FUNC_DBPI_D5>,
+ <PINMUX_GPIO19__FUNC_DBPI_D6>,
+ <PINMUX_GPIO20__FUNC_DBPI_D7>,
+ <PINMUX_GPIO21__FUNC_DBPI_D8>,
+ <PINMUX_GPIO22__FUNC_DBPI_D9>,
+ <PINMUX_GPIO23__FUNC_DBPI_D10>,
+ <PINMUX_GPIO24__FUNC_DBPI_D11>,
+ <PINMUX_GPIO25__FUNC_DBPI_HSYNC>,
+ <PINMUX_GPIO26__FUNC_DBPI_VSYNC>,
+ <PINMUX_GPIO27__FUNC_DBPI_DE>,
+ <PINMUX_GPIO28__FUNC_DBPI_CK>;
+ drive-strength = <MTK_DRIVE_6mA>;
+ };
+ };
+
ec_ap_int_odl: ec_ap_int_odl {
pins1 {
pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
@@ -550,6 +628,29 @@
};
};
+ it6505_pins: it6505_pins {
+ pins_hpd {
+ pinmux = <PINMUX_GPIO9__FUNC_GPIO9>;
+ input-enable;
+ bias-pull-up;
+ };
+ pins_int {
+ pinmux = <PINMUX_GPIO152__FUNC_GPIO152>;
+ input-enable;
+ bias-pull-up;
+ };
+ pins_power_enable {
+ pinmux = <PINMUX_GPIO178__FUNC_GPIO178>;
+ output-low;
+ bias-pull-up;
+ };
+ pins_reset {
+ pinmux = <PINMUX_GPIO179__FUNC_GPIO179>;
+ output-low;
+ bias-pull-up;
+ };
+ };
+
mmc0_pins_default: mmc0-pins-default {
pins_cmd_dat {
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,

10
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-cadmium-kukui.gpu-vsram.patch
View file

@ -1,10 +0,0 @@
--- linux-kukui-new/arch/arm64/boot/dts/mediatek/mt6358.dtsi 2021-06-30 16:08:03.382271887 +0200
+++ linux-kukui/arch/arm64/boot/dts/mediatek/mt6358.dtsi 2021-06-30 16:10:18.072445277 +0200
@@ -209,6 +209,7 @@
mt6358_vsram_gpu_reg: ldo_vsram_gpu {
regulator-name = "vsram_gpu";
+ regulator-always-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <6250>;

11
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-cadmium-kukui.move-gpu-opp-to-3.patch
View file

@ -1,11 +0,0 @@
--- linux-kukui-2/arch/arm64/boot/dts/mediatek/mt8183.dtsi 2021-07-13 17:13:43.706654294 +0200
+++ linux-kukui/arch/arm64/boot/dts/mediatek/mt8183.dtsi 2021-07-13 17:14:03.978385800 +0200
@@ -197,7 +197,7 @@
};
};
- gpu_opp_table: opp_table0 {
+ gpu_opp_table: opp_table3 {
compatible = "operating-points-v2";
opp-shared;

8
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-cadmium-kukui.panel-dts-rotation.patch
View file

@ -1,8 +0,0 @@
--- linux-kukui/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts 2021-06-23 21:48:58.128171064 +0200
+++ linux-kukui-gud/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts 2021-06-23 18:35:25.532087704 +0200
@@ -20,4 +20,5 @@
&panel {
status = "okay";
compatible = "boe,tv101wum-nl6";
+ rotation = <270>;
};

8
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-cadmium-kukui.panel-dts-rotation_sku0.patch
View file

@ -1,8 +0,0 @@
--- linux-kukui/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts 2021-06-23 21:48:58.128171064 +0200
+++ linux-kukui-gud/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts 2021-06-23 18:35:25.532087704 +0200
@@ -20,4 +20,5 @@
&panel {
status = "okay";
compatible = "auo,kd101n80-45na";
+ rotation = <270>;
};

110
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-fix-audio-module-loading.patch Normal file
View file

@ -0,0 +1,110 @@
from: https://patchwork.kernel.org/project/linux-mediatek/cover/20221107160437.740353-1-nfraprado@collabora.com/
diff --git a/sound/soc/mediatek/mt2701/mt2701-cs42448.c b/sound/soc/mediatek/mt2701/mt2701-cs42448.c
index d9fd6eb786aa..08ef109744c7 100644
--- a/sound/soc/mediatek/mt2701/mt2701-cs42448.c
+++ b/sound/soc/mediatek/mt2701/mt2701-cs42448.c
@@ -418,6 +418,7 @@ static const struct of_device_id mt2701_cs42448_machine_dt_match[] = {
{.compatible = "mediatek,mt2701-cs42448-machine",},
{}
};
+MODULE_DEVICE_TABLE(of, mt2701_cs42448_machine_dt_match);
#endif
static struct platform_driver mt2701_cs42448_machine = {
diff --git a/sound/soc/mediatek/mt2701/mt2701-wm8960.c b/sound/soc/mediatek/mt2701/mt2701-wm8960.c
index 0cdf2ae36243..a184032c15b6 100644
--- a/sound/soc/mediatek/mt2701/mt2701-wm8960.c
+++ b/sound/soc/mediatek/mt2701/mt2701-wm8960.c
@@ -161,6 +161,7 @@ static const struct of_device_id mt2701_wm8960_machine_dt_match[] = {
{.compatible = "mediatek,mt2701-wm8960-machine",},
{}
};
+MODULE_DEVICE_TABLE(of, mt2701_wm8960_machine_dt_match);
#endif
static struct platform_driver mt2701_wm8960_machine = {
diff --git a/sound/soc/mediatek/mt6797/mt6797-mt6351.c b/sound/soc/mediatek/mt6797/mt6797-mt6351.c
index d2f6213a6bfc..784c201b8fd4 100644
--- a/sound/soc/mediatek/mt6797/mt6797-mt6351.c
+++ b/sound/soc/mediatek/mt6797/mt6797-mt6351.c
@@ -242,6 +242,7 @@ static const struct of_device_id mt6797_mt6351_dt_match[] = {
{.compatible = "mediatek,mt6797-mt6351-sound",},
{}
};
+MODULE_DEVICE_TABLE(of, mt6797_mt6351_dt_match);
#endif
static struct platform_driver mt6797_mt6351_driver = {
diff --git a/sound/soc/mediatek/mt8183/mt8183-da7219-max98357.c b/sound/soc/mediatek/mt8183/mt8183-da7219-max98357.c
index 9f22d3939818..0e572fe28c58 100644
--- a/sound/soc/mediatek/mt8183/mt8183-da7219-max98357.c
+++ b/sound/soc/mediatek/mt8183/mt8183-da7219-max98357.c
@@ -842,6 +842,7 @@ static const struct of_device_id mt8183_da7219_max98357_dt_match[] = {
},
{}
};
+MODULE_DEVICE_TABLE(of, mt8183_da7219_max98357_dt_match);
#endif
static struct platform_driver mt8183_da7219_max98357_driver = {
diff --git a/sound/soc/mediatek/mt8183/mt8183-mt6358-ts3a227-max98357.c b/sound/soc/mediatek/mt8183/mt8183-mt6358-ts3a227-max98357.c
index a86085223677..8fb473543cf9 100644
--- a/sound/soc/mediatek/mt8183/mt8183-mt6358-ts3a227-max98357.c
+++ b/sound/soc/mediatek/mt8183/mt8183-mt6358-ts3a227-max98357.c
@@ -835,6 +835,7 @@ static const struct of_device_id mt8183_mt6358_ts3a227_max98357_dt_match[] = {
},
{}
};
+MODULE_DEVICE_TABLE(of, mt8183_mt6358_ts3a227_max98357_dt_match);
#endif
static struct platform_driver mt8183_mt6358_ts3a227_max98357_driver = {
diff --git a/sound/soc/mediatek/mt8186/mt8186-mt6366-da7219-max98357.c b/sound/soc/mediatek/mt8186/mt8186-mt6366-da7219-max98357.c
index cfca6bdee834..08ff57f7189c 100644
--- a/sound/soc/mediatek/mt8186/mt8186-mt6366-da7219-max98357.c
+++ b/sound/soc/mediatek/mt8186/mt8186-mt6366-da7219-max98357.c
@@ -1161,6 +1161,7 @@ static const struct of_device_id mt8186_mt6366_da7219_max98357_dt_match[] = {
},
{}
};
+MODULE_DEVICE_TABLE(of, mt8186_mt6366_da7219_max98357_dt_match);
#endif
static struct platform_driver mt8186_mt6366_da7219_max98357_driver = {
diff --git a/sound/soc/mediatek/mt8186/mt8186-mt6366-rt1019-rt5682s.c b/sound/soc/mediatek/mt8186/mt8186-mt6366-rt1019-rt5682s.c
index 16d834f3153d..e59d92e2afa3 100644
--- a/sound/soc/mediatek/mt8186/mt8186-mt6366-rt1019-rt5682s.c
+++ b/sound/soc/mediatek/mt8186/mt8186-mt6366-rt1019-rt5682s.c
@@ -1237,6 +1237,7 @@ static const struct of_device_id mt8186_mt6366_rt1019_rt5682s_dt_match[] = {
},
{}
};
+MODULE_DEVICE_TABLE(of, mt8186_mt6366_rt1019_rt5682s_dt_match);
#endif
static struct platform_driver mt8186_mt6366_rt1019_rt5682s_driver = {
diff --git a/sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c b/sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c
index b93c3237ef2d..16660eda577e 100644
--- a/sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c
+++ b/sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c
@@ -1261,6 +1261,7 @@ static const struct of_device_id mt8192_mt6359_dt_match[] = {
},
{}
};
+MODULE_DEVICE_TABLE(of, mt8192_mt6359_dt_match);
#endif
static const struct dev_pm_ops mt8192_mt6359_pm_ops = {
diff --git a/sound/soc/mediatek/mt8195/mt8195-mt6359.c b/sound/soc/mediatek/mt8195/mt8195-mt6359.c
index 480ed3e08d5b..61be66f47723 100644
--- a/sound/soc/mediatek/mt8195/mt8195-mt6359.c
+++ b/sound/soc/mediatek/mt8195/mt8195-mt6359.c
@@ -1544,6 +1544,7 @@ static const struct of_device_id mt8195_mt6359_dt_match[] = {
},
{},
};
+MODULE_DEVICE_TABLE(of, mt8195_mt6359_dt_match);
static struct platform_driver mt8195_mt6359_driver = {
.driver = {

72
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-kukui-jacuzzi-fix-anx7625-01.patch
View file

@ -1,72 +0,0 @@
from: https://lore.kernel.org/all/20220422084720.959271-1-xji@analogixsemi.com/
"[PATCH v2 1/4] media/v4l2-core: Add enum V4L2_FWNODE_BUS_TYPE_DPI"
thanks to wens from the #linux-mediatek irc for pointing me to this patch
As V4L2_FWNODE_BUS_TYPE_PARALLEL is not used for DPI interface, this
patch add V4L2_FWNODE_BUS_TYPE_DPI for video DPI interface.
Signed-off-by: Xin Ji <xji@analogixsemi.com>
---
drivers/media/v4l2-core/v4l2-fwnode.c | 4 ++++
include/media/v4l2-fwnode.h | 2 ++
include/media/v4l2-mediabus.h | 2 ++
3 files changed, 8 insertions(+)
diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c
index afceb35e500c..3d85a8600f57 100644
--- a/drivers/media/v4l2-core/v4l2-fwnode.c
+++ b/drivers/media/v4l2-core/v4l2-fwnode.c
@@ -61,6 +61,10 @@ static const struct v4l2_fwnode_bus_conv {
V4L2_FWNODE_BUS_TYPE_BT656,
V4L2_MBUS_BT656,
"Bt.656",
+ }, {
+ V4L2_FWNODE_BUS_TYPE_DPI,
+ V4L2_MBUS_DPI,
+ "DPI",
}
};
diff --git a/include/media/v4l2-fwnode.h b/include/media/v4l2-fwnode.h
index feb132df45a3..15e4ab672223 100644
--- a/include/media/v4l2-fwnode.h
+++ b/include/media/v4l2-fwnode.h
@@ -173,6 +173,7 @@ struct v4l2_fwnode_connector {
* @V4L2_FWNODE_BUS_TYPE_CSI2_DPHY: MIPI CSI-2 bus, D-PHY physical layer
* @V4L2_FWNODE_BUS_TYPE_PARALLEL: Camera Parallel Interface bus
* @V4L2_FWNODE_BUS_TYPE_BT656: BT.656 video format bus-type
+ * @V4L2_FWNODE_BUS_TYPE_DPI: Video Parallel Interface bus
* @NR_OF_V4L2_FWNODE_BUS_TYPE: Number of bus-types
*/
enum v4l2_fwnode_bus_type {
@@ -183,6 +184,7 @@ enum v4l2_fwnode_bus_type {
V4L2_FWNODE_BUS_TYPE_CSI2_DPHY,
V4L2_FWNODE_BUS_TYPE_PARALLEL,
V4L2_FWNODE_BUS_TYPE_BT656,
+ V4L2_FWNODE_BUS_TYPE_DPI,
NR_OF_V4L2_FWNODE_BUS_TYPE
};
diff --git a/include/media/v4l2-mediabus.h b/include/media/v4l2-mediabus.h
index e0db3bcff9ed..f67a74daf799 100644
--- a/include/media/v4l2-mediabus.h
+++ b/include/media/v4l2-mediabus.h
@@ -129,6 +129,7 @@ struct v4l2_mbus_config_mipi_csi1 {
* @V4L2_MBUS_CCP2: CCP2 (Compact Camera Port 2)
* @V4L2_MBUS_CSI2_DPHY: MIPI CSI-2 serial interface, with D-PHY
* @V4L2_MBUS_CSI2_CPHY: MIPI CSI-2 serial interface, with C-PHY
+ * @V4L2_MBUS_DPI: MIPI VIDEO DPI interface
* @V4L2_MBUS_INVALID: invalid bus type (keep as last)
*/
enum v4l2_mbus_type {
@@ -139,6 +140,7 @@ enum v4l2_mbus_type {
V4L2_MBUS_CCP2,
V4L2_MBUS_CSI2_DPHY,
V4L2_MBUS_CSI2_CPHY,
+ V4L2_MBUS_DPI,
V4L2_MBUS_INVALID,
};
--
2.25.1

48
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-kukui-jacuzzi-fix-anx7625-04.patch
View file

@ -1,48 +0,0 @@
from: https://lore.kernel.org/all/20220422084720.959271-4-xji@analogixsemi.com/
"[PATCH v2 4/4] drm/bridge: anx7625: Use DPI bus type"
thanks to wens from the #linux-mediatek irc for pointing me to this patch
As V4L2_FWNODE_BUS_TYPE_PARALLEL not properly descript for DPI
interface, this patch use new defined V4L2_FWNODE_BUS_TYPE_DPI for it.
Fixes: fd0310b6fe7d ("drm/bridge: anx7625: add MIPI DPI input feature")
Signed-off-by: Xin Ji <xji@analogixsemi.com>
---
drivers/gpu/drm/bridge/analogix/anx7625.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
index 376da01243a3..71df977e8f53 100644
--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
@@ -1623,14 +1623,14 @@ static int anx7625_parse_dt(struct device *dev,
anx7625_get_swing_setting(dev, pdata);
- pdata->is_dpi = 1; /* default dpi mode */
+ pdata->is_dpi = 0; /* default dsi mode */
pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0);
if (!pdata->mipi_host_node) {
DRM_DEV_ERROR(dev, "fail to get internal panel.\n");
return -ENODEV;
}
- bus_type = V4L2_FWNODE_BUS_TYPE_PARALLEL;
+ bus_type = 0;
mipi_lanes = MAX_LANES_SUPPORT;
ep0 = of_graph_get_endpoint_by_regs(np, 0, 0);
if (ep0) {
@@ -1640,8 +1640,8 @@ static int anx7625_parse_dt(struct device *dev,
mipi_lanes = of_property_count_u32_elems(ep0, "data-lanes");
}
- if (bus_type == V4L2_FWNODE_BUS_TYPE_PARALLEL) /* bus type is Parallel(DSI) */
- pdata->is_dpi = 0;
+ if (bus_type == V4L2_FWNODE_BUS_TYPE_DPI) /* bus type is DPI */
+ pdata->is_dpi = 1;
pdata->mipi_lanes = mipi_lanes;
if (pdata->mipi_lanes > MAX_LANES_SUPPORT || pdata->mipi_lanes <= 0)
--
2.25.1

41
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-kukui-jacuzzi-fix-display-resume.patch
View file

@ -49,47 +49,6 @@ index 14d73fb1dd15..8325e8d0ee19 100644
}
static enum drm_mode_status
@@ -1720,38 +1738,9 @@ static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev)
return 0;
}
-static int __maybe_unused anx7625_resume(struct device *dev)
-{
- struct anx7625_data *ctx = dev_get_drvdata(dev);
-
- if (!ctx->pdata.intp_irq)
- return 0;
-
- if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
- enable_irq(ctx->pdata.intp_irq);
- anx7625_runtime_pm_resume(dev);
- }
-
- return 0;
-}
-
-static int __maybe_unused anx7625_suspend(struct device *dev)
-{
- struct anx7625_data *ctx = dev_get_drvdata(dev);
-
- if (!ctx->pdata.intp_irq)
- return 0;
-
- if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
- anx7625_runtime_pm_suspend(dev);
- disable_irq(ctx->pdata.intp_irq);
- }
-
- return 0;
-}
-
static const struct dev_pm_ops anx7625_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume)
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend,
anx7625_runtime_pm_resume, NULL)
};
diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.h b/drivers/gpu/drm/bridge/analogix/anx7625.h
index edbbfe410a56..299e62df6238 100644
--- a/drivers/gpu/drm/bridge/analogix/anx7625.h

312
device/testing/linux-postmarketos-mediatek-mt8183/mt8183-panel-orientation.patch
View file

@ -1,312 +0,0 @@
From: Hsin-Yi Wang <hsinyi@chromium.org>
Subject: [PATCH v6 1/3] gpu: drm: separate panel orientation property creating and value setting
Date: Thu, 29 Apr 2021 12:28:32 +0800
drm_dev_register() sets connector->registration_state to
DRM_CONNECTOR_REGISTERED and dev->registered to true. If
drm_connector_set_panel_orientation() is first called after
drm_dev_register(), it will fail several checks and results in following
warning.
Add a function to create panel orientation property and set default value
to UNKNOWN, so drivers can call this function to init the property earlier
, and let the panel set the real value later.
[ 4.480976] ------------[ cut here ]------------
[ 4.485603] WARNING: CPU: 5 PID: 369 at drivers/gpu/drm/drm_mode_object.c:45 __drm_mode_object_add+0xb4/0xbc
<snip>
[ 4.609772] Call trace:
[ 4.612208] __drm_mode_object_add+0xb4/0xbc
[ 4.616466] drm_mode_object_add+0x20/0x2c
[ 4.620552] drm_property_create+0xdc/0x174
[ 4.624723] drm_property_create_enum+0x34/0x98
[ 4.629241] drm_connector_set_panel_orientation+0x64/0xa0
[ 4.634716] boe_panel_get_modes+0x88/0xd8
[ 4.638802] drm_panel_get_modes+0x2c/0x48
[ 4.642887] panel_bridge_get_modes+0x1c/0x28
[ 4.647233] drm_bridge_connector_get_modes+0xa0/0xd4
[ 4.652273] drm_helper_probe_single_connector_modes+0x218/0x700
[ 4.658266] drm_mode_getconnector+0x1b4/0x45c
[ 4.662699] drm_ioctl_kernel+0xac/0x128
[ 4.666611] drm_ioctl+0x268/0x410
[ 4.670002] drm_compat_ioctl+0xdc/0xf0
[ 4.673829] __arm64_compat_sys_ioctl+0xc8/0x100
[ 4.678436] el0_svc_common+0xf4/0x1c0
[ 4.682174] do_el0_svc_compat+0x28/0x3c
[ 4.686088] el0_svc_compat+0x10/0x1c
[ 4.689738] el0_sync_compat_handler+0xa8/0xcc
[ 4.694171] el0_sync_compat+0x178/0x180
[ 4.698082] ---[ end trace b4f2db9d9c88610b ]---
[ 4.702721] ------------[ cut here ]------------
[ 4.707329] WARNING: CPU: 5 PID: 369 at drivers/gpu/drm/drm_mode_object.c:243 drm_object_attach_property+0x48/0xb8
<snip>
[ 4.833830] Call trace:
[ 4.836266] drm_object_attach_property+0x48/0xb8
[ 4.840958] drm_connector_set_panel_orientation+0x84/0xa0
[ 4.846432] boe_panel_get_modes+0x88/0xd8
[ 4.850516] drm_panel_get_modes+0x2c/0x48
[ 4.854600] panel_bridge_get_modes+0x1c/0x28
[ 4.858946] drm_bridge_connector_get_modes+0xa0/0xd4
[ 4.863984] drm_helper_probe_single_connector_modes+0x218/0x700
[ 4.869978] drm_mode_getconnector+0x1b4/0x45c
[ 4.874410] drm_ioctl_kernel+0xac/0x128
[ 4.878320] drm_ioctl+0x268/0x410
[ 4.881711] drm_compat_ioctl+0xdc/0xf0
[ 4.885536] __arm64_compat_sys_ioctl+0xc8/0x100
[ 4.890142] el0_svc_common+0xf4/0x1c0
[ 4.893879] do_el0_svc_compat+0x28/0x3c
[ 4.897791] el0_svc_compat+0x10/0x1c
[ 4.901441] el0_sync_compat_handler+0xa8/0xcc
[ 4.905873] el0_sync_compat+0x178/0x180
[ 4.909783] ---[ end trace b4f2db9d9c88610c ]---
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
v6, v5:
don't create property in set_panel_orientation.
v4, v3:
create property in dsi driver and set value in panel.
v2:
create property in connector init
https://patchwork.kernel.org/project/linux-mediatek/patch/20210426051848.2600890-1-hsinyi@chromium.org/
v1:
set panel orientation in dsi driver
https://patchwork.kernel.org/project/linux-mediatek/patch/20210409045314.3420733-1-hsinyi@chromium.org/
---
drivers/gpu/drm/drm_connector.c | 58 ++++++++++++++++++-------
drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 1 +
drivers/gpu/drm/i915/display/vlv_dsi.c | 1 +
include/drm/drm_connector.h | 2 +
5 files changed, 47 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 7631f76e7f34..7189baaabf41 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1210,7 +1210,7 @@ static const struct drm_prop_enum_list dp_colorspaces[] = {
* INPUT_PROP_DIRECT) will still map 1:1 to the actual LCD panel
* coordinates, so if userspace rotates the picture to adjust for
* the orientation it must also apply the same transformation to the
- * touchscreen input coordinates. This property is initialized by calling
+ * touchscreen input coordinates. This property value is set by calling
* drm_connector_set_panel_orientation() or
* drm_connector_set_panel_orientation_with_quirk()
*
@@ -2173,8 +2173,8 @@ EXPORT_SYMBOL(drm_connector_set_vrr_capable_property);
* @connector: connector for which to set the panel-orientation property.
* @panel_orientation: drm_panel_orientation value to set
*
- * This function sets the connector's panel_orientation and attaches
- * a "panel orientation" property to the connector.
+ * This function sets the connector's panel_orientation value. If the property
+ * doesn't exist, it will return an error.
*
* Calling this function on a connector where the panel_orientation has
* already been set is a no-op (e.g. the orientation has been overridden with
@@ -2205,19 +2205,11 @@ int drm_connector_set_panel_orientation(
info->panel_orientation = panel_orientation;
prop = dev->mode_config.panel_orientation_property;
- if (!prop) {
- prop = drm_property_create_enum(dev, DRM_MODE_PROP_IMMUTABLE,
- "panel orientation",
- drm_panel_orientation_enum_list,
- ARRAY_SIZE(drm_panel_orientation_enum_list));
- if (!prop)
- return -ENOMEM;
-
- dev->mode_config.panel_orientation_property = prop;
- }
+ if (WARN_ON(!prop))
+ return -EINVAL;
- drm_object_attach_property(&connector->base, prop,
- info->panel_orientation);
+ drm_object_property_set_value(&connector->base, prop,
+ info->panel_orientation);
return 0;
}
EXPORT_SYMBOL(drm_connector_set_panel_orientation);
@@ -2225,7 +2217,7 @@ EXPORT_SYMBOL(drm_connector_set_panel_orientation);
/**
* drm_connector_set_panel_orientation_with_quirk - set the
* connector's panel_orientation after checking for quirks
- * @connector: connector for which to init the panel-orientation property.
+ * @connector: connector for which to set the panel-orientation property.
* @panel_orientation: drm_panel_orientation value to set
* @width: width in pixels of the panel, used for panel quirk detection
* @height: height in pixels of the panel, used for panel quirk detection
@@ -2252,6 +2244,40 @@ int drm_connector_set_panel_orientation_with_quirk(
}
EXPORT_SYMBOL(drm_connector_set_panel_orientation_with_quirk);
+/**
+ * drm_connector_init_panel_orientation_property -
+ * create the connector's panel orientation property
+ *
+ * This function attaches a "panel orientation" property to the connector
+ * and initializes its value to DRM_MODE_PANEL_ORIENTATION_UNKNOWN.
+ *
+ * The value of the property can be set by drm_connector_set_panel_orientation()
+ * or drm_connector_set_panel_orientation_with_quirk() later.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_connector_init_panel_orientation_property(
+ struct drm_connector *connector)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_property *prop;
+
+ prop = drm_property_create_enum(dev, DRM_MODE_PROP_IMMUTABLE,
+ "panel orientation",
+ drm_panel_orientation_enum_list,
+ ARRAY_SIZE(drm_panel_orientation_enum_list));
+ if (!prop)
+ return -ENOMEM;
+
+ dev->mode_config.panel_orientation_property = prop;
+ drm_object_attach_property(&connector->base, prop,
+ DRM_MODE_PANEL_ORIENTATION_UNKNOWN);
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_connector_init_panel_orientation_property);
+
int drm_connector_set_obj_prop(struct drm_mode_object *obj,
struct drm_property *property,
uint64_t value)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 9282978060b0..5ac4538e4283 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1903,6 +1903,7 @@ static void icl_dsi_add_properties(struct intel_connector *connector)
connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
+ drm_connector_init_panel_orientation_property(&connector->base);
drm_connector_set_panel_orientation_with_quirk(&connector->base,
intel_dsi_get_panel_orientation(connector),
connector->panel.fixed_mode->hdisplay,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a5231ac3443a..f1d664e5abb2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5263,6 +5263,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
intel_panel_setup_backlight(connector, pipe);
if (fixed_mode) {
+ drm_connector_init_panel_orientation_property(connector);
drm_connector_set_panel_orientation_with_quirk(connector,
dev_priv->vbt.orientation,
fixed_mode->hdisplay, fixed_mode->vdisplay);
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 9bee99fe5495..853855482af1 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1632,6 +1632,7 @@ static void vlv_dsi_add_properties(struct intel_connector *connector)
connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
+ drm_connector_init_panel_orientation_property(&connector->base);
drm_connector_set_panel_orientation_with_quirk(&connector->base,
intel_dsi_get_panel_orientation(connector),
connector->panel.fixed_mode->hdisplay,
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 1922b278ffad..4396c1c4a5db 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -1696,6 +1696,8 @@ int drm_connector_set_panel_orientation_with_quirk(
struct drm_connector *connector,
enum drm_panel_orientation panel_orientation,
int width, int height);
+int drm_connector_init_panel_orientation_property(
+ struct drm_connector *connector);
int drm_connector_attach_max_bpc_property(struct drm_connector *connector,
int min, int max);
--
2.31.1.498.g6c1eba8ee3d-goog
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
From: Hsin-Yi Wang <hsinyi@chromium.org>
Subject: [PATCH v6 2/3] drm/mediatek: init panel orientation property
Date: Thu, 29 Apr 2021 12:28:33 +0800
Init panel orientation property after connector is initialized. Let the
panel driver decides the orientation value later.
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index ae403c67cbd9..9da1fd649131 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -964,6 +964,13 @@ static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi)
ret = PTR_ERR(dsi->connector);
goto err_cleanup_encoder;
}
+
+ ret = drm_connector_init_panel_orientation_property(dsi->connector);
+ if (ret) {
+ DRM_ERROR("Unable to init panel orientation\n");
+ goto err_cleanup_encoder;
+ }
+
drm_connector_attach_encoder(dsi->connector, &dsi->encoder);
return 0;
--
2.31.1.498.g6c1eba8ee3d-goog
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http://lists.infradead.org/mailman/listinfo/linux-mediatek
From: Hsin-Yi Wang <hsinyi@chromium.org>
Subject: [PATCH v6 3/3] arm64: dts: mt8183: Add panel rotation
Date: Thu, 29 Apr 2021 12:28:34 +0800
krane, kakadu, and kodama boards have a default panel rotation.
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
index ff56bcfa3370..793cc9501337 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
@@ -263,6 +263,7 @@ panel: panel@0 {
avee-supply = <&ppvarp_lcd>;
pp1800-supply = <&pp1800_lcd>;
backlight = <&backlight_lcd0>;
+ rotation = <270>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi_out>;
--
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43
device/testing/linux-postmarketos-mediatek-mt8183/mt81xx-fix-low-speed-usb-devices.patch Normal file
View file

@ -0,0 +1,43 @@
this one reverts commit 8b13ea05117ffad4727b0971ed09122d5c91c4dc from mainline
from author: Chunfeng Yun <chunfeng.yun@mediatek.com>
from date: Fri Aug 19 16:05:55 2022 +0800
subject: usb: xhci-mtk: relax TT periodic bandwidth allocation
link: https://lore.kernel.org/r/20220819080556.32215-1-chunfeng.yun@mediatek.com
if this commit is in it results in low speed usb devices (keybard, mice etc.)
connected to a usb hub longer working properly and kernel messages like:
"kernel: usb 1-2.1.2: reset low-speed USB device number 6 using xhci-mtk"
diff --git a/drivers/usb/host/xhci-mtk-sch.c b/drivers/usb/host/xhci-mtk-sch.c
index 579899eb24c1..d86f1c84ad8f 100644
--- a/drivers/usb/host/xhci-mtk-sch.c
+++ b/drivers/usb/host/xhci-mtk-sch.c
@@ -425,6 +425,7 @@ static int check_fs_bus_bw(struct mu3h_sch_ep_info *sch_ep, int offset)
static int check_sch_tt(struct mu3h_sch_ep_info *sch_ep, u32 offset)
{
+ u32 extra_cs_count;
u32 start_ss, last_ss;
u32 start_cs, last_cs;
@@ -460,12 +461,18 @@ static int check_sch_tt(struct mu3h_sch_ep_info *sch_ep, u32 offset)
if (last_cs > 7)
return -ESCH_CS_OVERFLOW;
+ if (sch_ep->ep_type == ISOC_IN_EP)
+ extra_cs_count = (last_cs == 7) ? 1 : 2;
+ else /* ep_type : INTR IN / INTR OUT */
+ extra_cs_count = 1;
+
+ cs_count += extra_cs_count;
if (cs_count > 7)
cs_count = 7; /* HW limit */
sch_ep->cs_count = cs_count;
- /* ss, idle are ignored */
- sch_ep->num_budget_microframes = cs_count;
+ /* one for ss, the other for idle */
+ sch_ep->num_budget_microframes = cs_count + 2;
/*
* if interval=1, maxp >752, num_budge_micoframe is larger

155
device/testing/linux-postmarketos-mediatek-mt8183/mt81xx-usb-02.patch Normal file
View file

@ -0,0 +1,155 @@
from: https://patchwork.kernel.org/project/linux-mediatek/patch/20221118110116.20165-1-chunfeng.yun@mediatek.com/
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index 01705e559c42..cff3c4aea036 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c
@@ -485,6 +485,7 @@ static int xhci_mtk_probe(struct platform_device *pdev)
const struct hc_driver *driver;
struct xhci_hcd *xhci;
struct resource *res;
+ struct usb_hcd *usb3_hcd;
struct usb_hcd *hcd;
int ret = -ENODEV;
int wakeup_irq;
@@ -593,6 +594,7 @@ static int xhci_mtk_probe(struct platform_device *pdev)
xhci = hcd_to_xhci(hcd);
xhci->main_hcd = hcd;
+ xhci->allow_single_roothub = 1;
/*
* imod_interval is the interrupt moderation value in nanoseconds.
@@ -602,24 +604,29 @@ static int xhci_mtk_probe(struct platform_device *pdev)
xhci->imod_interval = 5000;
device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval);
- xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
- dev_name(dev), hcd);
- if (!xhci->shared_hcd) {
- ret = -ENOMEM;
- goto disable_device_wakeup;
- }
-
ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
if (ret)
- goto put_usb3_hcd;
+ goto disable_device_wakeup;
- if (HCC_MAX_PSA(xhci->hcc_params) >= 4 &&
+ if (!xhci_has_one_roothub(xhci)) {
+ xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
+ dev_name(dev), hcd);
+ if (!xhci->shared_hcd) {
+ ret = -ENOMEM;
+ goto dealloc_usb2_hcd;
+ }
+ }
+
+ usb3_hcd = xhci_get_usb3_hcd(xhci);
+ if (usb3_hcd && HCC_MAX_PSA(xhci->hcc_params) >= 4 &&
!(xhci->quirks & XHCI_BROKEN_STREAMS))
- xhci->shared_hcd->can_do_streams = 1;
+ usb3_hcd->can_do_streams = 1;
- ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
- if (ret)
- goto dealloc_usb2_hcd;
+ if (xhci->shared_hcd) {
+ ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
+ if (ret)
+ goto put_usb3_hcd;
+ }
if (wakeup_irq > 0) {
ret = dev_pm_set_dedicated_wake_irq_reverse(dev, wakeup_irq);
@@ -641,13 +648,13 @@ static int xhci_mtk_probe(struct platform_device *pdev)
usb_remove_hcd(xhci->shared_hcd);
xhci->shared_hcd = NULL;
-dealloc_usb2_hcd:
- usb_remove_hcd(hcd);
-
put_usb3_hcd:
- xhci_mtk_sch_exit(mtk);
usb_put_hcd(xhci->shared_hcd);
+dealloc_usb2_hcd:
+ xhci_mtk_sch_exit(mtk);
+ usb_remove_hcd(hcd);
+
disable_device_wakeup:
device_init_wakeup(dev, false);
@@ -679,10 +686,15 @@ static int xhci_mtk_remove(struct platform_device *pdev)
dev_pm_clear_wake_irq(dev);
device_init_wakeup(dev, false);
- usb_remove_hcd(shared_hcd);
- xhci->shared_hcd = NULL;
+ if (shared_hcd) {
+ usb_remove_hcd(shared_hcd);
+ xhci->shared_hcd = NULL;
+ }
usb_remove_hcd(hcd);
- usb_put_hcd(shared_hcd);
+
+ if (shared_hcd)
+ usb_put_hcd(shared_hcd);
+
usb_put_hcd(hcd);
xhci_mtk_sch_exit(mtk);
clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
@@ -700,13 +712,16 @@ static int __maybe_unused xhci_mtk_suspend(struct device *dev)
struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
struct usb_hcd *hcd = mtk->hcd;
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+ struct usb_hcd *shared_hcd = xhci->shared_hcd;
int ret;
xhci_dbg(xhci, "%s: stop port polling\n", __func__);
clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
del_timer_sync(&hcd->rh_timer);
- clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
- del_timer_sync(&xhci->shared_hcd->rh_timer);
+ if (shared_hcd) {
+ clear_bit(HCD_FLAG_POLL_RH, &shared_hcd->flags);
+ del_timer_sync(&shared_hcd->rh_timer);
+ }
ret = xhci_mtk_host_disable(mtk);
if (ret)
@@ -718,8 +733,10 @@ static int __maybe_unused xhci_mtk_suspend(struct device *dev)
restart_poll_rh:
xhci_dbg(xhci, "%s: restart port polling\n", __func__);
- set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
- usb_hcd_poll_rh_status(xhci->shared_hcd);
+ if (shared_hcd) {
+ set_bit(HCD_FLAG_POLL_RH, &shared_hcd->flags);
+ usb_hcd_poll_rh_status(shared_hcd);
+ }
set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
usb_hcd_poll_rh_status(hcd);
return ret;
@@ -730,6 +747,7 @@ static int __maybe_unused xhci_mtk_resume(struct device *dev)
struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
struct usb_hcd *hcd = mtk->hcd;
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+ struct usb_hcd *shared_hcd = xhci->shared_hcd;
int ret;
usb_wakeup_set(mtk, false);
@@ -742,8 +760,10 @@ static int __maybe_unused xhci_mtk_resume(struct device *dev)
goto disable_clks;
xhci_dbg(xhci, "%s: restart port polling\n", __func__);
- set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
- usb_hcd_poll_rh_status(xhci->shared_hcd);
+ if (shared_hcd) {
+ set_bit(HCD_FLAG_POLL_RH, &shared_hcd->flags);
+ usb_hcd_poll_rh_status(shared_hcd);
+ }
set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
usb_hcd_poll_rh_status(hcd);
return 0;