temp/u-boot-pinephone: apply patch for 3GB RAM support (MR 1420)
This commit is contained in:
Luca Weiss
Bart Ribbers
parent
957dc9356a
commit
9a878ee7ee
2 changed files with 215 additions and 5 deletions
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@ -0,0 +1,208 @@
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From 26251b8792608080e2e8a551291e8a362cc31769 Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Fri, 19 Jun 2020 20:16:57 +0800
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Subject: [PATCH] sunxi: support asymmetric dual rank DRAM on A64/R40
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Previously we have known that R40 has a configuration register for its
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rank 1, which allows different configuration than rank 0. Reverse
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engineering of newest libdram of A64 from Allwinner shows that A64 has
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this register too. It's bit 0 (which enables dual rank in rank 0
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configuration register) means a dedicated rank size setup is used for
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rank 1.
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Now, Pine64 scheduled to use a 3GiB LPDDR3 DRAM chip (which has 2GiB
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rank 0 and 1GiB rank 1) on PinePhone, that makes asymmetric dual rank
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DRAM support necessary.
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Add this support. As we have gained knowledge of asymmetric dual rank,
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we can now allow R40 dual rank memory setup to work too.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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.../include/asm/arch-sunxi/dram_sunxi_dw.h | 11 +-
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arch/arm/mach-sunxi/dram_sunxi_dw.c | 100 +++++++++++++-----
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2 files changed, 84 insertions(+), 27 deletions(-)
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diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
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index a5a7ebde44..e843c14202 100644
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--- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
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+++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
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@@ -215,12 +215,17 @@ struct sunxi_mctl_ctl_reg {
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#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
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/* The eight data lines (DQn) plus DM, DQS and DQSN */
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#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3)
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-struct dram_para {
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+
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+struct rank_para {
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u16 page_size;
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- u8 bus_full_width;
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- u8 dual_rank;
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u8 row_bits;
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u8 bank_bits;
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+};
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+
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+struct dram_para {
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+ u8 dual_rank;
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+ u8 bus_full_width;
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+ struct rank_para ranks[2];
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const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
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const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
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const u8 ac_delays[31];
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diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
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index 85e7a1874e..b679f92e70 100644
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--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
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+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
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@@ -346,18 +346,24 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para)
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#else
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#error Unsupported DRAM type!
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#endif
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- (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) |
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+ (para->ranks[0].bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) |
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MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
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(para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
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- MCTL_CR_PAGE_SIZE(para->page_size) |
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- MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
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+ MCTL_CR_PAGE_SIZE(para->ranks[0].page_size) |
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+ MCTL_CR_ROW_BITS(para->ranks[0].row_bits), &mctl_com->cr);
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- if (socid == SOCID_R40) {
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- if (para->dual_rank)
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- panic("Dual rank memory not supported\n");
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+ if (socid == SOCID_A64 || socid == SOCID_R40) {
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+ writel((para->ranks[1].bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) |
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+ MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
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+ (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
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+ MCTL_CR_PAGE_SIZE(para->ranks[1].page_size) |
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+ MCTL_CR_ROW_BITS(para->ranks[1].row_bits), &mctl_com->cr_r1);
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+ }
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+ if (socid == SOCID_R40) {
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/* Mux pin to A15 address line for single rank memory. */
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- setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15);
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+ if (!para->dual_rank)
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+ setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15);
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}
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}
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@@ -581,35 +587,63 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
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return 0;
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}
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-static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
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+/*
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+ * Test if memory at offset offset matches memory at a certain base
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+ */
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+static bool mctl_mem_matches_base(u32 offset, ulong base)
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+{
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+ /* Try to write different values to RAM at two addresses */
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+ writel(0, base);
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+ writel(0xaa55aa55, base + offset);
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+ dsb();
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+ /* Check if the same value is actually observed when reading back */
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+ return readl(base) ==
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+ readl(base + offset);
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+}
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+
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+static void mctl_auto_detect_dram_size_rank(uint16_t socid, struct dram_para *para, ulong base, struct rank_para *rank)
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{
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/* detect row address bits */
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- para->page_size = 512;
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- para->row_bits = 16;
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- para->bank_bits = 2;
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+ rank->page_size = 512;
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+ rank->row_bits = 16;
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+ rank->bank_bits = 2;
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mctl_set_cr(socid, para);
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- for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
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- if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits)) * para->page_size))
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+ for (rank->row_bits = 11; rank->row_bits < 16; rank->row_bits++)
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+ if (mctl_mem_matches_base((1 << (rank->row_bits + rank->bank_bits)) * rank->page_size, base))
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break;
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/* detect bank address bits */
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- para->bank_bits = 3;
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+ rank->bank_bits = 3;
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mctl_set_cr(socid, para);
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- for (para->bank_bits = 2; para->bank_bits < 3; para->bank_bits++)
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- if (mctl_mem_matches((1 << para->bank_bits) * para->page_size))
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+ for (rank->bank_bits = 2; rank->bank_bits < 3; rank->bank_bits++)
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+ if (mctl_mem_matches_base((1 << rank->bank_bits) * rank->page_size, base))
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break;
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/* detect page size */
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- para->page_size = 8192;
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+ rank->page_size = 8192;
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mctl_set_cr(socid, para);
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- for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)
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- if (mctl_mem_matches(para->page_size))
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+ for (rank->page_size = 512; rank->page_size < 8192; rank->page_size *= 2)
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+ if (mctl_mem_matches_base(rank->page_size, base))
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break;
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}
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+static unsigned long mctl_calc_rank_size(struct rank_para *rank)
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+{
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+ return (1UL << (rank->row_bits + rank->bank_bits)) * rank->page_size;
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+}
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+
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+static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
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+{
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+ mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE, ¶->ranks[0]);
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+
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+ if ((socid == SOCID_A64 || socid == SOCID_R40) && para->dual_rank) {
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+ mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]);
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+ }
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+}
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+
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/*
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* The actual values used here are taken from Allwinner provided boot0
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* binaries, though they are probably board specific, so would likely benefit
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@@ -688,12 +722,23 @@ unsigned long sunxi_dram_init(void)
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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+ unsigned long size;
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+
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struct dram_para para = {
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.dual_rank = 1,
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.bus_full_width = 1,
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- .row_bits = 15,
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- .bank_bits = 3,
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- .page_size = 4096,
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+ .ranks = {
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+ {
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+ .row_bits = 15,
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+ .bank_bits = 3,
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+ .page_size = 4096,
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+ },
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+ {
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+ .row_bits = 15,
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+ .bank_bits = 3,
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+ .page_size = 4096,
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+ }
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+ },
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#if defined(CONFIG_MACH_SUN8I_H3)
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.dx_read_delays = SUN8I_H3_DX_READ_DELAYS,
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@@ -762,6 +807,13 @@ unsigned long sunxi_dram_init(void)
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mctl_auto_detect_dram_size(socid, ¶);
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mctl_set_cr(socid, ¶);
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- return (1UL << (para.row_bits + para.bank_bits)) * para.page_size *
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- (para.dual_rank ? 2 : 1);
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+ size = mctl_calc_rank_size(¶.ranks[0]);
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+ if (socid == SOCID_A64 || socid == SOCID_R40) {
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+ if (para.dual_rank)
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+ size += mctl_calc_rank_size(¶.ranks[1]);
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+ } else if (para.dual_rank) {
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+ size *= 2;
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+ }
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+
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+ return size;
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}
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--
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2.27.0
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@ -1,7 +1,7 @@
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# U-boot with patches to make the PinePhone boot faster and have control over the ddr clock speed
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pkgname=u-boot-pinephone
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pkgver=2020.07_git20200612
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pkgrel=0
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pkgrel=1
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_commit="78c99d82596fef01444c076f4c975b60e084a09b"
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pkgdesc="u-boot bootloader for the PINE64 PinePhone"
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url="https://gitlab.com/pine64-org/u-boot"
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@ -10,10 +10,10 @@ license="GPL-2.0-or-later OFL-1.1 BSD-2-Clause BSD-3-Clause eCos-2.0 IBM-pibs
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ISC LGPL-2.0-only LGPL-2.1-only X11"
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makedepends="$depends_dev bc dtc python3-dev swig bison flex openssl-dev arm-trusted-firmware-sun50i crust"
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options="!check"
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source="
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https://github.com/crust-firmware/u-boot/archive/$_commit/u-boot-$_commit.tar.gz
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source="https://github.com/crust-firmware/u-boot/archive/$_commit/u-boot-$_commit.tar.gz
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update-u-boot
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"
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0001-sunxi-support-asymmetric-dual-rank-DRAM-on-A64-R40.patch
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"
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builddir="$srcdir/u-boot-$_commit"
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build() {
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@ -35,5 +35,7 @@ package() {
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"$pkgdir"/usr/share/u-boot/pine64-pinephone/u-boot-sunxi-with-spl.bin
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install -D -m 755 "$srcdir"/update-u-boot "$pkgdir"/usr/sbin/update-u-boot
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}
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sha512sums="3fe43a9d3364a68ba88f5c895da5fbc2e309461d64be0fb0493840ef70fe07e89c71ce13f5ae97b61526ba223ea1a5efa505f97f40bc9c74fe336019973e27bc u-boot-78c99d82596fef01444c076f4c975b60e084a09b.tar.gz
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4a3a1772a7309d44e7977dee4aca499d5c79675d99cda1395d8765abb415b8456260c7a989650f0bd2dfda0377af2346917fbcbf3e356a36265ed07e161ddc3b update-u-boot"
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4a3a1772a7309d44e7977dee4aca499d5c79675d99cda1395d8765abb415b8456260c7a989650f0bd2dfda0377af2346917fbcbf3e356a36265ed07e161ddc3b update-u-boot
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7369f4d1f28d1ec2adf9640636940b3672eb5d4573160f2906451778369b67a02d4a684fb81246b3e2b9983acf0c9632b1c880f7d77c850a00a41080fca65481 0001-sunxi-support-asymmetric-dual-rank-DRAM-on-A64-R40.patch"
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