cross/gcc-riscv64: upgrade to 13.1.1_git20230722-r3 (MR 4476)
This reverts commit 72e55aae91, which was
itself a revert of this change 🥳
[ci:skip-build]: Already built successfully in CI
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Clayton Craft
Stefan Hansson
parent
ca6ff9cd98
commit
9400f43579
2 changed files with 189 additions and 1 deletions
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@ -0,0 +1,186 @@
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https://gcc.gnu.org/PR110792
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https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
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https://github.com/randombit/botan/issues/3637
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From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
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From: Roger Sayle <roger@nextmovesoftware.com>
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Date: Thu, 3 Aug 2023 07:12:04 +0100
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Subject: [PATCH] PR target/110792: Early clobber issues with
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rot32di2_doubleword on i386.
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This patch is a conservative fix for PR target/110792, a wrong-code
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regression affecting doubleword rotations by BITS_PER_WORD, which
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effectively swaps the highpart and lowpart words, when the source to be
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rotated resides in memory. The issue is that if the register used to
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hold the lowpart of the destination is mentioned in the address of
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the memory operand, the current define_insn_and_split unintentionally
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clobbers it before reading the highpart.
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Hence, for the testcase, the incorrectly generated code looks like:
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salq $4, %rdi // calculate address
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movq WHIRL_S+8(%rdi), %rdi // accidentally clobber addr
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movq WHIRL_S(%rdi), %rbp // load (wrong) lowpart
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Traditionally, the textbook way to fix this would be to add an
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explicit early clobber to the instruction's constraints.
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(define_insn_and_split "<insn>32di2_doubleword"
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- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
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+ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
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(any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
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(const_int 32)))]
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but unfortunately this currently generates significantly worse code,
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due to a strange choice of reloads (effectively memcpy), which ends up
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looking like:
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salq $4, %rdi // calculate address
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movdqa WHIRL_S(%rdi), %xmm0 // load the double word in SSE reg.
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movaps %xmm0, -16(%rsp) // store the SSE reg back to the stack
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movq -8(%rsp), %rdi // load highpart
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movq -16(%rsp), %rbp // load lowpart
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Note that reload's "&" doesn't distinguish between the memory being
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early clobbered, vs the registers used in an addressing mode being
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early clobbered.
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The fix proposed in this patch is to remove the third alternative, that
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allowed offsetable memory as an operand, forcing reload to place the
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operand into a register before the rotation. This results in:
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salq $4, %rdi
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movq WHIRL_S(%rdi), %rax
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movq WHIRL_S+8(%rdi), %rdi
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movq %rax, %rbp
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I believe there's a more advanced solution, by swapping the order of
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the loads (if first destination register is mentioned in the address),
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or inserting a lea insn (if both destination registers are mentioned
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in the address), but this fix is a minimal "safe" solution, that
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should hopefully be suitable for backporting.
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2023-08-03 Roger Sayle <roger@nextmovesoftware.com>
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gcc/ChangeLog
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PR target/110792
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* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
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place operand in a register before gen_<insn>64ti2_doubleword.
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(<any_rotate>di3): Likewise, for rotations by 32 bits, place
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operand in a register before gen_<insn>32di2_doubleword.
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(<any_rotate>32di2_doubleword): Constrain operand to be in register.
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(<any_rotate>64ti2_doubleword): Likewise.
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gcc/testsuite/ChangeLog
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PR target/110792
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* g++.target/i386/pr110792.C: New 32-bit C++ test case.
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* gcc.target/i386/pr110792.c: New 64-bit C test case.
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(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
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---
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gcc/config/i386/i386.md | 18 ++++++++++++------
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gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
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gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
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3 files changed, 46 insertions(+), 6 deletions(-)
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create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
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create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
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diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
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index f3a3305..a71e837 100644
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--- a/gcc/config/i386/i386.md
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+++ b/gcc/config/i386/i386.md
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@@ -14359,7 +14359,10 @@
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emit_insn (gen_ix86_<insn>ti3_doubleword
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(operands[0], operands[1], operands[2]));
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else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
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- emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
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+ {
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+ operands[1] = force_reg (TImode, operands[1]);
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+ emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
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+ }
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else
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{
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rtx amount = force_reg (QImode, operands[2]);
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@@ -14394,7 +14397,10 @@
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emit_insn (gen_ix86_<insn>di3_doubleword
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(operands[0], operands[1], operands[2]));
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else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
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- emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
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+ {
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+ operands[1] = force_reg (DImode, operands[1]);
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+ emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
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+ }
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else
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FAIL;
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@@ -14562,8 +14568,8 @@
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})
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(define_insn_and_split "<insn>32di2_doubleword"
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- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
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- (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
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+ [(set (match_operand:DI 0 "register_operand" "=r,r")
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+ (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
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(const_int 32)))]
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"!TARGET_64BIT"
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"#"
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@@ -14580,8 +14586,8 @@
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})
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(define_insn_and_split "<insn>64ti2_doubleword"
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- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
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- (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
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+ [(set (match_operand:TI 0 "register_operand" "=r,r")
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+ (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
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(const_int 64)))]
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"TARGET_64BIT"
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"#"
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diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
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new file mode 100644
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index 0000000..ce21a7a
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--- /dev/null
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+++ b/gcc/testsuite/g++.target/i386/pr110792.C
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@@ -0,0 +1,16 @@
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+/* { dg-do compile { target ia32 } } */
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+/* { dg-options "-O2" } */
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+
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+template <int ROT, typename T>
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+inline T rotr(T input)
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+{
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+ return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
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+}
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+
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+unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
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+unsigned long long whirl(unsigned char x0)
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+{
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+ const unsigned long long s4 = WHIRL_S[x0&0xFF];
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+ return rotr<32>(s4);
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+}
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+/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
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diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
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new file mode 100644
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index 0000000..b65125c
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/i386/pr110792.c
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@@ -0,0 +1,18 @@
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+/* { dg-do compile { target int128 } } */
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+/* { dg-options "-O2" } */
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+
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+static inline unsigned __int128 rotr(unsigned __int128 input)
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+{
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+ return ((input >> 64) | (input << (64)));
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+}
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+
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+unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
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+unsigned __int128 whirl(unsigned char x0)
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+{
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+ register int t __asm("rdi") = x0&0xFF;
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+ const unsigned __int128 s4 = WHIRL_S[t];
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+ register unsigned __int128 tt __asm("rdi") = rotr(s4);
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+ asm("":::"memory");
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+ return tt;
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+}
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+/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
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--
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2.41.0
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@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
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[ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
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pkgname=gcc-riscv64
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pkgrel=2
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pkgrel=3
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pkgdesc="Stage2 cross-compiler for riscv64"
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url="https://gcc.gnu.org"
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arch="x86_64"
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@ -269,6 +269,7 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
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0033-libphobos-do-not-use-LFS64-symbols.patch
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0034-libgo-fix-lfs64-use.patch
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0035-Fix-ICE-observed-in-PR110280.patch
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0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
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"
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# we build out-of-tree
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@ -819,4 +820,5 @@ b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95
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c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75 0033-libphobos-do-not-use-LFS64-symbols.patch
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c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c 0034-libgo-fix-lfs64-use.patch
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048d767f4477c92ee6835850d13063ede21c0be751d0945c94445d04054e134cdc617eeb0b1ac8c892a604d8644580fcfebeccaf537d6b7380558ac6378e445a 0035-Fix-ICE-observed-in-PR110280.patch
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cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8 0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
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"
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