samsung-coreprimevelte: add mainline kernel (MR 4267)
[ci:skip-build]: already built successfully in CI
This commit is contained in:
Duje Mihanović
Oliver Smith
parent
4ebd1d1a17
commit
4f842cfd9a
15 changed files with 6396 additions and 5 deletions
|
|
@ -2,14 +2,18 @@
|
||||||
pkgname=device-samsung-coreprimevelte
|
pkgname=device-samsung-coreprimevelte
|
||||||
pkgdesc="Samsung Galaxy Core Prime LTE"
|
pkgdesc="Samsung Galaxy Core Prime LTE"
|
||||||
pkgver=0.1
|
pkgver=0.1
|
||||||
pkgrel=8
|
pkgrel=9
|
||||||
url="https://postmarketos.org"
|
url="https://postmarketos.org"
|
||||||
license="MIT"
|
license="MIT"
|
||||||
arch="aarch64"
|
arch="aarch64"
|
||||||
options="!check !archcheck"
|
options="!check !archcheck"
|
||||||
depends="postmarketos-base linux-samsung-coreprimevelte mkbootimg u-boot-tools pxa-mkbootimg"
|
depends="postmarketos-base mkbootimg u-boot-tools pxa-mkbootimg"
|
||||||
makedepends="devicepkg-dev"
|
makedepends="devicepkg-dev"
|
||||||
subpackages="$pkgname-nonfree-firmware:nonfree_firmware"
|
subpackages="
|
||||||
|
$pkgname-kernel-downstream:kernel_downstream
|
||||||
|
$pkgname-kernel-mainline:kernel_mainline
|
||||||
|
$pkgname-nonfree-firmware:nonfree_firmware
|
||||||
|
"
|
||||||
source="deviceinfo 90-coreprimevelte.conf"
|
source="deviceinfo 90-coreprimevelte.conf"
|
||||||
|
|
||||||
build() {
|
build() {
|
||||||
|
|
@ -18,9 +22,21 @@ build() {
|
||||||
|
|
||||||
package() {
|
package() {
|
||||||
devicepkg_package $startdir $pkgname
|
devicepkg_package $startdir $pkgname
|
||||||
|
}
|
||||||
|
|
||||||
|
kernel_downstream() {
|
||||||
|
pkgdesc="Downstream kernel"
|
||||||
|
depends="linux-samsung-coreprimevelte"
|
||||||
|
devicepkg_subpackage_kernel $startdir $pkgname $subpkgname
|
||||||
install -Dm444 $startdir/90-coreprimevelte.conf $pkgdir/etc/sysctl.d/90-coreprimevelte.conf
|
install -Dm444 $startdir/90-coreprimevelte.conf $pkgdir/etc/sysctl.d/90-coreprimevelte.conf
|
||||||
}
|
}
|
||||||
|
|
||||||
|
kernel_mainline() {
|
||||||
|
pkgdesc="Mainline kernel (for development only)"
|
||||||
|
depends="linux-samsung-coreprimevelte-mainline"
|
||||||
|
devicepkg_subpackage_kernel $startdir $pkgname $subpkgname
|
||||||
|
}
|
||||||
|
|
||||||
nonfree_firmware() {
|
nonfree_firmware() {
|
||||||
pkgdesc="Wi-Fi firmware"
|
pkgdesc="Wi-Fi firmware"
|
||||||
depends="firmware-samsung-pxa1908"
|
depends="firmware-samsung-pxa1908"
|
||||||
|
|
@ -28,6 +44,6 @@ nonfree_firmware() {
|
||||||
}
|
}
|
||||||
|
|
||||||
sha512sums="
|
sha512sums="
|
||||||
39a9f0afb2d709983634e14ce7a05fcc4cd631f2e5b31aa971aaba452e11c37d2aba91ae971e33ebaffbd6432da6e3a2c4bbcdbf8708830fb34907e1af4be732 deviceinfo
|
9d8f140567e3345cd4608bbcf97392eef3da63119ee37a5c8d171aaae5a47f11ec8b36d7926e745936108d42f0ed287845606298ae8898ef87c29d496a7dcadf deviceinfo
|
||||||
4854cc57b86e1199dbc165110514e672dabf45044fe9f7ebbde5b2b24768fb5497273b5f38612cf2dfeffc9bf0648c725114b4fa01165bf7fb02f7d741ee5806 90-coreprimevelte.conf
|
4854cc57b86e1199dbc165110514e672dabf45044fe9f7ebbde5b2b24768fb5497273b5f38612cf2dfeffc9bf0648c725114b4fa01165bf7fb02f7d741ee5806 90-coreprimevelte.conf
|
||||||
"
|
"
|
||||||
|
|
|
||||||
|
|
@ -11,11 +11,12 @@ deviceinfo_arch="aarch64"
|
||||||
# Device related
|
# Device related
|
||||||
deviceinfo_chassis="handset"
|
deviceinfo_chassis="handset"
|
||||||
deviceinfo_keyboard="false"
|
deviceinfo_keyboard="false"
|
||||||
deviceinfo_external_storage="false"
|
deviceinfo_external_storage="true"
|
||||||
deviceinfo_screen_width="480"
|
deviceinfo_screen_width="480"
|
||||||
deviceinfo_screen_height="800"
|
deviceinfo_screen_height="800"
|
||||||
|
|
||||||
# Bootloader related
|
# Bootloader related
|
||||||
|
deviceinfo_dtb_mainline="marvell/pxa1908-samsung-coreprimevelte"
|
||||||
deviceinfo_flash_method="heimdall-bootimg"
|
deviceinfo_flash_method="heimdall-bootimg"
|
||||||
deviceinfo_generate_bootimg="true"
|
deviceinfo_generate_bootimg="true"
|
||||||
deviceinfo_bootimg_qcdt="true"
|
deviceinfo_bootimg_qcdt="true"
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,32 @@
|
||||||
|
From 210337a85f95f0c7f3411bd0028c325818a23839 Mon Sep 17 00:00:00 2001
|
||||||
|
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
|
||||||
|
Date: Fri, 21 Jul 2023 22:37:43 +0200
|
||||||
|
Subject: [PATCH] tty: serial: 8250: Define earlycon for mrvl,mmp-uart
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
mrvl,pxa-uart already supports earlycon and both compatible strings use
|
||||||
|
the same driver, so there's no reason for mmp-uart to not have earlycon
|
||||||
|
as well.
|
||||||
|
|
||||||
|
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
|
||||||
|
---
|
||||||
|
drivers/tty/serial/8250/8250_pxa.c | 1 +
|
||||||
|
1 file changed, 1 insertion(+)
|
||||||
|
|
||||||
|
diff --git a/drivers/tty/serial/8250/8250_pxa.c b/drivers/tty/serial/8250/8250_pxa.c
|
||||||
|
index 28b341f602c6..a5b3ea27fc90 100644
|
||||||
|
--- a/drivers/tty/serial/8250/8250_pxa.c
|
||||||
|
+++ b/drivers/tty/serial/8250/8250_pxa.c
|
||||||
|
@@ -183,6 +183,7 @@ static int __init early_serial_pxa_setup(struct earlycon_device *device,
|
||||||
|
return early_serial8250_setup(device, NULL);
|
||||||
|
}
|
||||||
|
OF_EARLYCON_DECLARE(early_pxa, "mrvl,pxa-uart", early_serial_pxa_setup);
|
||||||
|
+OF_EARLYCON_DECLARE(mmp, "mrvl,mmp-uart", early_serial_pxa_setup);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
MODULE_AUTHOR("Sergei Ianovich");
|
||||||
|
--
|
||||||
|
2.41.0
|
||||||
|
|
||||||
|
|
@ -0,0 +1,33 @@
|
||||||
|
From d53f28d1c946a99a5968f429219530655e95ff88 Mon Sep 17 00:00:00 2001
|
||||||
|
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
|
||||||
|
Date: Fri, 21 Jul 2023 22:37:45 +0200
|
||||||
|
Subject: [PATCH] gpio: pxa: disable pinctrl calls for MMP_GPIO
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
Similarly to PXA3xx and MMP2, pinctrl-single isn't capable of setting
|
||||||
|
pin direction on MMP either.
|
||||||
|
|
||||||
|
Fixes: a770d946371e ("gpio: pxa: add pin control gpio direction and request")
|
||||||
|
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
|
||||||
|
Reviewed-by: Andy Shevchenko <andy@kernel.org>
|
||||||
|
---
|
||||||
|
drivers/gpio/gpio-pxa.c | 1 +
|
||||||
|
1 file changed, 1 insertion(+)
|
||||||
|
|
||||||
|
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
|
||||||
|
index a1630ed4b741..d92650aecb06 100644
|
||||||
|
--- a/drivers/gpio/gpio-pxa.c
|
||||||
|
+++ b/drivers/gpio/gpio-pxa.c
|
||||||
|
@@ -238,6 +238,7 @@ static bool pxa_gpio_has_pinctrl(void)
|
||||||
|
switch (gpio_type) {
|
||||||
|
case PXA3XX_GPIO:
|
||||||
|
case MMP2_GPIO:
|
||||||
|
+ case MMP_GPIO:
|
||||||
|
return false;
|
||||||
|
|
||||||
|
default:
|
||||||
|
--
|
||||||
|
2.41.0
|
||||||
|
|
||||||
|
|
@ -0,0 +1,349 @@
|
||||||
|
From ef90e6f6bdd88eb6700a1605b5ebd4a8aaeb98c2 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||||
|
Date: Mon, 24 Jul 2023 12:48:38 +0300
|
||||||
|
Subject: [PATCH] clk: mmp: Switch to use struct u32_fract instead of custom
|
||||||
|
one
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
The struct mmp_clk_factor_tbl repeats the generic struct u32_fract.
|
||||||
|
Kill the custom one and use the generic one instead.
|
||||||
|
|
||||||
|
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||||
|
Tested-by: Duje Mihanović <duje.mihanovic@skole.hr>
|
||||||
|
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
|
||||||
|
---
|
||||||
|
drivers/clk/mmp/clk-frac.c | 57 ++++++++++++++++----------------
|
||||||
|
drivers/clk/mmp/clk-mmp2.c | 6 ++--
|
||||||
|
drivers/clk/mmp/clk-of-mmp2.c | 26 +++++++--------
|
||||||
|
drivers/clk/mmp/clk-of-pxa168.c | 4 +--
|
||||||
|
drivers/clk/mmp/clk-of-pxa1928.c | 6 ++--
|
||||||
|
drivers/clk/mmp/clk-of-pxa910.c | 4 +--
|
||||||
|
drivers/clk/mmp/clk-pxa168.c | 4 +--
|
||||||
|
drivers/clk/mmp/clk-pxa910.c | 4 +--
|
||||||
|
drivers/clk/mmp/clk.h | 10 ++----
|
||||||
|
9 files changed, 58 insertions(+), 63 deletions(-)
|
||||||
|
|
||||||
|
diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c
|
||||||
|
index 1b90867b60c4..6556f6ada2e8 100644
|
||||||
|
--- a/drivers/clk/mmp/clk-frac.c
|
||||||
|
+++ b/drivers/clk/mmp/clk-frac.c
|
||||||
|
@@ -26,14 +26,15 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
|
||||||
|
{
|
||||||
|
struct mmp_clk_factor *factor = to_clk_factor(hw);
|
||||||
|
u64 rate = 0, prev_rate;
|
||||||
|
+ struct u32_fract *d;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < factor->ftbl_cnt; i++) {
|
||||||
|
- prev_rate = rate;
|
||||||
|
- rate = *prate;
|
||||||
|
- rate *= factor->ftbl[i].den;
|
||||||
|
- do_div(rate, factor->ftbl[i].num * factor->masks->factor);
|
||||||
|
+ d = &factor->ftbl[i];
|
||||||
|
|
||||||
|
+ prev_rate = rate;
|
||||||
|
+ rate = (u64)(*prate) * d->denominator;
|
||||||
|
+ do_div(rate, d->numerator * factor->masks->factor);
|
||||||
|
if (rate > drate)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
@@ -52,23 +53,22 @@ static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
|
||||||
|
{
|
||||||
|
struct mmp_clk_factor *factor = to_clk_factor(hw);
|
||||||
|
struct mmp_clk_factor_masks *masks = factor->masks;
|
||||||
|
- unsigned int val, num, den;
|
||||||
|
+ struct u32_fract d;
|
||||||
|
+ unsigned int val;
|
||||||
|
u64 rate;
|
||||||
|
|
||||||
|
val = readl_relaxed(factor->base);
|
||||||
|
|
||||||
|
/* calculate numerator */
|
||||||
|
- num = (val >> masks->num_shift) & masks->num_mask;
|
||||||
|
+ d.numerator = (val >> masks->num_shift) & masks->num_mask;
|
||||||
|
|
||||||
|
/* calculate denominator */
|
||||||
|
- den = (val >> masks->den_shift) & masks->den_mask;
|
||||||
|
-
|
||||||
|
- if (!den)
|
||||||
|
+ d.denominator = (val >> masks->den_shift) & masks->den_mask;
|
||||||
|
+ if (!d.denominator)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
- rate = parent_rate;
|
||||||
|
- rate *= den;
|
||||||
|
- do_div(rate, num * factor->masks->factor);
|
||||||
|
+ rate = (u64)parent_rate * d.denominator;
|
||||||
|
+ do_div(rate, d.numerator * factor->masks->factor);
|
||||||
|
|
||||||
|
return rate;
|
||||||
|
}
|
||||||
|
@@ -82,18 +82,18 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||||
|
int i;
|
||||||
|
unsigned long val;
|
||||||
|
unsigned long flags = 0;
|
||||||
|
+ struct u32_fract *d;
|
||||||
|
u64 rate = 0;
|
||||||
|
|
||||||
|
for (i = 0; i < factor->ftbl_cnt; i++) {
|
||||||
|
- rate = prate;
|
||||||
|
- rate *= factor->ftbl[i].den;
|
||||||
|
- do_div(rate, factor->ftbl[i].num * factor->masks->factor);
|
||||||
|
+ d = &factor->ftbl[i];
|
||||||
|
|
||||||
|
+ rate = (u64)prate * d->denominator;
|
||||||
|
+ do_div(rate, d->numerator * factor->masks->factor);
|
||||||
|
if (rate > drate)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
- if (i > 0)
|
||||||
|
- i--;
|
||||||
|
+ d = i ? &factor->ftbl[i - 1] : &factor->ftbl[0];
|
||||||
|
|
||||||
|
if (factor->lock)
|
||||||
|
spin_lock_irqsave(factor->lock, flags);
|
||||||
|
@@ -101,10 +101,10 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||||
|
val = readl_relaxed(factor->base);
|
||||||
|
|
||||||
|
val &= ~(masks->num_mask << masks->num_shift);
|
||||||
|
- val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift;
|
||||||
|
+ val |= (d->numerator & masks->num_mask) << masks->num_shift;
|
||||||
|
|
||||||
|
val &= ~(masks->den_mask << masks->den_shift);
|
||||||
|
- val |= (factor->ftbl[i].den & masks->den_mask) << masks->den_shift;
|
||||||
|
+ val |= (d->denominator & masks->den_mask) << masks->den_shift;
|
||||||
|
|
||||||
|
writel_relaxed(val, factor->base);
|
||||||
|
|
||||||
|
@@ -118,7 +118,8 @@ static int clk_factor_init(struct clk_hw *hw)
|
||||||
|
{
|
||||||
|
struct mmp_clk_factor *factor = to_clk_factor(hw);
|
||||||
|
struct mmp_clk_factor_masks *masks = factor->masks;
|
||||||
|
- u32 val, num, den;
|
||||||
|
+ struct u32_fract d;
|
||||||
|
+ u32 val;
|
||||||
|
int i;
|
||||||
|
unsigned long flags = 0;
|
||||||
|
|
||||||
|
@@ -128,23 +129,22 @@ static int clk_factor_init(struct clk_hw *hw)
|
||||||
|
val = readl(factor->base);
|
||||||
|
|
||||||
|
/* calculate numerator */
|
||||||
|
- num = (val >> masks->num_shift) & masks->num_mask;
|
||||||
|
+ d.numerator = (val >> masks->num_shift) & masks->num_mask;
|
||||||
|
|
||||||
|
/* calculate denominator */
|
||||||
|
- den = (val >> masks->den_shift) & masks->den_mask;
|
||||||
|
+ d.denominator = (val >> masks->den_shift) & masks->den_mask;
|
||||||
|
|
||||||
|
for (i = 0; i < factor->ftbl_cnt; i++)
|
||||||
|
- if (den == factor->ftbl[i].den && num == factor->ftbl[i].num)
|
||||||
|
+ if (d.denominator == factor->ftbl[i].denominator &&
|
||||||
|
+ d.numerator == factor->ftbl[i].numerator)
|
||||||
|
break;
|
||||||
|
|
||||||
|
if (i >= factor->ftbl_cnt) {
|
||||||
|
val &= ~(masks->num_mask << masks->num_shift);
|
||||||
|
- val |= (factor->ftbl[0].num & masks->num_mask) <<
|
||||||
|
- masks->num_shift;
|
||||||
|
+ val |= (factor->ftbl[0].numerator & masks->num_mask) << masks->num_shift;
|
||||||
|
|
||||||
|
val &= ~(masks->den_mask << masks->den_shift);
|
||||||
|
- val |= (factor->ftbl[0].den & masks->den_mask) <<
|
||||||
|
- masks->den_shift;
|
||||||
|
+ val |= (factor->ftbl[0].denominator & masks->den_mask) << masks->den_shift;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!(val & masks->enable_mask) || i >= factor->ftbl_cnt) {
|
||||||
|
@@ -168,8 +168,7 @@ static const struct clk_ops clk_factor_ops = {
|
||||||
|
struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
|
||||||
|
unsigned long flags, void __iomem *base,
|
||||||
|
struct mmp_clk_factor_masks *masks,
|
||||||
|
- struct mmp_clk_factor_tbl *ftbl,
|
||||||
|
- unsigned int ftbl_cnt, spinlock_t *lock)
|
||||||
|
+ struct u32_fract *ftbl, unsigned int ftbl_cnt, spinlock_t *lock)
|
||||||
|
{
|
||||||
|
struct mmp_clk_factor *factor;
|
||||||
|
struct clk_init_data init;
|
||||||
|
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
|
||||||
|
index aabacfa10158..ab7dde7e7a44 100644
|
||||||
|
--- a/drivers/clk/mmp/clk-mmp2.c
|
||||||
|
+++ b/drivers/clk/mmp/clk-mmp2.c
|
||||||
|
@@ -59,9 +59,9 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
|
||||||
|
.den_shift = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
|
||||||
|
- {.num = 8125, .den = 1536}, /*14.745MHZ */
|
||||||
|
- {.num = 3521, .den = 689}, /*19.23MHZ */
|
||||||
|
+static struct u32_fract uart_factor_tbl[] = {
|
||||||
|
+ { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */
|
||||||
|
+ { .numerator = 3521, .denominator = 689 }, /* 19.23MHZ */
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char *uart_parent[] = {"uart_pll", "vctcxo"};
|
||||||
|
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
|
||||||
|
index bcf60f43aa13..d771b3e5fb2d 100644
|
||||||
|
--- a/drivers/clk/mmp/clk-of-mmp2.c
|
||||||
|
+++ b/drivers/clk/mmp/clk-of-mmp2.c
|
||||||
|
@@ -141,9 +141,9 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
|
||||||
|
.den_shift = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
|
||||||
|
- {.num = 8125, .den = 1536}, /*14.745MHZ */
|
||||||
|
- {.num = 3521, .den = 689}, /*19.23MHZ */
|
||||||
|
+static struct u32_fract uart_factor_tbl[] = {
|
||||||
|
+ { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */
|
||||||
|
+ { .numerator = 3521, .denominator = 689 }, /* 19.23MHZ */
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct mmp_clk_factor_masks i2s_factor_masks = {
|
||||||
|
@@ -155,16 +155,16 @@ static struct mmp_clk_factor_masks i2s_factor_masks = {
|
||||||
|
.enable_mask = 0xd0000000,
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct mmp_clk_factor_tbl i2s_factor_tbl[] = {
|
||||||
|
- {.num = 24868, .den = 511}, /* 2.0480 MHz */
|
||||||
|
- {.num = 28003, .den = 793}, /* 2.8224 MHz */
|
||||||
|
- {.num = 24941, .den = 1025}, /* 4.0960 MHz */
|
||||||
|
- {.num = 28003, .den = 1586}, /* 5.6448 MHz */
|
||||||
|
- {.num = 31158, .den = 2561}, /* 8.1920 MHz */
|
||||||
|
- {.num = 16288, .den = 1845}, /* 11.2896 MHz */
|
||||||
|
- {.num = 20772, .den = 2561}, /* 12.2880 MHz */
|
||||||
|
- {.num = 8144, .den = 1845}, /* 22.5792 MHz */
|
||||||
|
- {.num = 10386, .den = 2561}, /* 24.5760 MHz */
|
||||||
|
+static struct u32_fract i2s_factor_tbl[] = {
|
||||||
|
+ { .numerator = 24868, .denominator = 511 }, /* 2.0480 MHz */
|
||||||
|
+ { .numerator = 28003, .denominator = 793 }, /* 2.8224 MHz */
|
||||||
|
+ { .numerator = 24941, .denominator = 1025 }, /* 4.0960 MHz */
|
||||||
|
+ { .numerator = 28003, .denominator = 1586 }, /* 5.6448 MHz */
|
||||||
|
+ { .numerator = 31158, .denominator = 2561 }, /* 8.1920 MHz */
|
||||||
|
+ { .numerator = 16288, .denominator = 1845 }, /* 11.2896 MHz */
|
||||||
|
+ { .numerator = 20772, .denominator = 2561 }, /* 12.2880 MHz */
|
||||||
|
+ { .numerator = 8144, .denominator = 1845 }, /* 22.5792 MHz */
|
||||||
|
+ { .numerator = 10386, .denominator = 2561 }, /* 24.5760 MHz */
|
||||||
|
};
|
||||||
|
|
||||||
|
static DEFINE_SPINLOCK(acgr_lock);
|
||||||
|
diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c
|
||||||
|
index 130d1a723879..17cb5c622c31 100644
|
||||||
|
--- a/drivers/clk/mmp/clk-of-pxa168.c
|
||||||
|
+++ b/drivers/clk/mmp/clk-of-pxa168.c
|
||||||
|
@@ -104,8 +104,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
|
||||||
|
.den_shift = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
|
||||||
|
- {.num = 8125, .den = 1536}, /*14.745MHZ */
|
||||||
|
+static struct u32_fract uart_factor_tbl[] = {
|
||||||
|
+ { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */
|
||||||
|
};
|
||||||
|
|
||||||
|
static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit)
|
||||||
|
diff --git a/drivers/clk/mmp/clk-of-pxa1928.c b/drivers/clk/mmp/clk-of-pxa1928.c
|
||||||
|
index 2508a0d795f8..675d695c5f7d 100644
|
||||||
|
--- a/drivers/clk/mmp/clk-of-pxa1928.c
|
||||||
|
+++ b/drivers/clk/mmp/clk-of-pxa1928.c
|
||||||
|
@@ -58,9 +58,9 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
|
||||||
|
.den_shift = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
|
||||||
|
- {.num = 832, .den = 234}, /*58.5MHZ */
|
||||||
|
- {.num = 1, .den = 1}, /*26MHZ */
|
||||||
|
+static struct u32_fract uart_factor_tbl[] = {
|
||||||
|
+ { .numerator = 832, .denominator = 234 }, /* 58.5MHZ */
|
||||||
|
+ { .numerator = 1, .denominator = 1 }, /* 26MHZ */
|
||||||
|
};
|
||||||
|
|
||||||
|
static void pxa1928_pll_init(struct pxa1928_clk_unit *pxa_unit)
|
||||||
|
diff --git a/drivers/clk/mmp/clk-of-pxa910.c b/drivers/clk/mmp/clk-of-pxa910.c
|
||||||
|
index 4d15bac987eb..f5b0b7b278c0 100644
|
||||||
|
--- a/drivers/clk/mmp/clk-of-pxa910.c
|
||||||
|
+++ b/drivers/clk/mmp/clk-of-pxa910.c
|
||||||
|
@@ -84,8 +84,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
|
||||||
|
.den_shift = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
|
||||||
|
- {.num = 8125, .den = 1536}, /*14.745MHZ */
|
||||||
|
+static struct u32_fract uart_factor_tbl[] = {
|
||||||
|
+ { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */
|
||||||
|
};
|
||||||
|
|
||||||
|
static void pxa910_pll_init(struct pxa910_clk_unit *pxa_unit)
|
||||||
|
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
|
||||||
|
index 8a9b8fb3a465..2ea88945bffd 100644
|
||||||
|
--- a/drivers/clk/mmp/clk-pxa168.c
|
||||||
|
+++ b/drivers/clk/mmp/clk-pxa168.c
|
||||||
|
@@ -52,8 +52,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
|
||||||
|
.den_shift = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
|
||||||
|
- {.num = 8125, .den = 1536}, /*14.745MHZ */
|
||||||
|
+static struct u32_fract uart_factor_tbl[] = {
|
||||||
|
+ { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
|
||||||
|
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
|
||||||
|
index 9fcd76316d7e..e29b0fd6f423 100644
|
||||||
|
--- a/drivers/clk/mmp/clk-pxa910.c
|
||||||
|
+++ b/drivers/clk/mmp/clk-pxa910.c
|
||||||
|
@@ -50,8 +50,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
|
||||||
|
.den_shift = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
|
||||||
|
- {.num = 8125, .den = 1536}, /*14.745MHZ */
|
||||||
|
+static struct u32_fract uart_factor_tbl[] = {
|
||||||
|
+ { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
|
||||||
|
diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
|
||||||
|
index 55ac05379781..c83cec169ddc 100644
|
||||||
|
--- a/drivers/clk/mmp/clk.h
|
||||||
|
+++ b/drivers/clk/mmp/clk.h
|
||||||
|
@@ -3,6 +3,7 @@
|
||||||
|
#define __MACH_MMP_CLK_H
|
||||||
|
|
||||||
|
#include <linux/clk-provider.h>
|
||||||
|
+#include <linux/math.h>
|
||||||
|
#include <linux/pm_domain.h>
|
||||||
|
#include <linux/clkdev.h>
|
||||||
|
|
||||||
|
@@ -20,16 +21,11 @@ struct mmp_clk_factor_masks {
|
||||||
|
unsigned int enable_mask;
|
||||||
|
};
|
||||||
|
|
||||||
|
-struct mmp_clk_factor_tbl {
|
||||||
|
- unsigned int num;
|
||||||
|
- unsigned int den;
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
struct mmp_clk_factor {
|
||||||
|
struct clk_hw hw;
|
||||||
|
void __iomem *base;
|
||||||
|
struct mmp_clk_factor_masks *masks;
|
||||||
|
- struct mmp_clk_factor_tbl *ftbl;
|
||||||
|
+ struct u32_fract *ftbl;
|
||||||
|
unsigned int ftbl_cnt;
|
||||||
|
spinlock_t *lock;
|
||||||
|
};
|
||||||
|
@@ -37,7 +33,7 @@ struct mmp_clk_factor {
|
||||||
|
extern struct clk *mmp_clk_register_factor(const char *name,
|
||||||
|
const char *parent_name, unsigned long flags,
|
||||||
|
void __iomem *base, struct mmp_clk_factor_masks *masks,
|
||||||
|
- struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
|
||||||
|
+ struct u32_fract *ftbl, unsigned int ftbl_cnt,
|
||||||
|
spinlock_t *lock);
|
||||||
|
|
||||||
|
/* Clock type "mix" */
|
||||||
|
--
|
||||||
|
2.41.0
|
||||||
|
|
||||||
|
|
@ -0,0 +1,173 @@
|
||||||
|
From 303c2b86cd5ebd0764e3768335883f0cd2e9fe04 Mon Sep 17 00:00:00 2001
|
||||||
|
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
|
||||||
|
Date: Fri, 21 Jul 2023 22:37:47 +0200
|
||||||
|
Subject: [PATCH] dt-bindings: clock: Add Marvell PXA1908 clock bindings
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
Add dt bindings and documentation for the Marvell PXA1908 clock
|
||||||
|
controller.
|
||||||
|
|
||||||
|
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
|
||||||
|
---
|
||||||
|
.../bindings/clock/marvell,pxa1908.yaml | 47 ++++++++++
|
||||||
|
include/dt-bindings/clock/marvell,pxa1908.h | 92 +++++++++++++++++++
|
||||||
|
2 files changed, 139 insertions(+)
|
||||||
|
create mode 100644 Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
|
||||||
|
create mode 100644 include/dt-bindings/clock/marvell,pxa1908.h
|
||||||
|
|
||||||
|
diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
|
||||||
|
new file mode 100644
|
||||||
|
index 000000000000..a5af7992b1b6
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
|
||||||
|
@@ -0,0 +1,47 @@
|
||||||
|
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||||
|
+%YAML 1.2
|
||||||
|
+---
|
||||||
|
+$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml#
|
||||||
|
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
+
|
||||||
|
+title: Marvell PXA1908 Clock Controllers
|
||||||
|
+
|
||||||
|
+maintainers:
|
||||||
|
+ - Duje Mihanović <duje.mihanovic@skole.hr>
|
||||||
|
+
|
||||||
|
+description: |
|
||||||
|
+ The PXA1908 clock subsystem generates and supplies clock to various
|
||||||
|
+ controllers within the PXA1908 SoC. The PXA1908 contains numerous clock
|
||||||
|
+ controller blocks, with the ones currently supported being APBC, APBCP, MPMU
|
||||||
|
+ and APMU roughly corresponding to internal buses.
|
||||||
|
+
|
||||||
|
+ All these clock identifiers could be found in <include/dt-bindings/marvell,pxa1908.h>.
|
||||||
|
+
|
||||||
|
+properties:
|
||||||
|
+ compatible:
|
||||||
|
+ enum:
|
||||||
|
+ - marvell,pxa1908-apbc
|
||||||
|
+ - marvell,pxa1908-apbcp
|
||||||
|
+ - marvell,pxa1908-mpmu
|
||||||
|
+ - marvell,pxa1908-apmu
|
||||||
|
+ reg:
|
||||||
|
+ maxItems: 1
|
||||||
|
+
|
||||||
|
+ '#clock-cells':
|
||||||
|
+ const: 1
|
||||||
|
+
|
||||||
|
+required:
|
||||||
|
+ - compatible
|
||||||
|
+ - reg
|
||||||
|
+ - '#clock-cells'
|
||||||
|
+
|
||||||
|
+additionalProperties: false
|
||||||
|
+
|
||||||
|
+examples:
|
||||||
|
+ # APMU block:
|
||||||
|
+ - |
|
||||||
|
+ clock-controller@d4282800 {
|
||||||
|
+ compatible = "marvell,pxa1908-apmu";
|
||||||
|
+ reg = <0xd4282800 0x400>;
|
||||||
|
+ #clock-cells = <1>;
|
||||||
|
+ };
|
||||||
|
diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindings/clock/marvell,pxa1908.h
|
||||||
|
new file mode 100644
|
||||||
|
index 000000000000..a4b035928137
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/include/dt-bindings/clock/marvell,pxa1908.h
|
||||||
|
@@ -0,0 +1,92 @@
|
||||||
|
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
|
||||||
|
+#ifndef __DTS_MARVELL_PXA1908_CLOCK_H
|
||||||
|
+#define __DTS_MARVELL_PXA1908_CLOCK_H
|
||||||
|
+
|
||||||
|
+/* plls */
|
||||||
|
+#define PXA1908_CLK_CLK32 1
|
||||||
|
+#define PXA1908_CLK_VCTCXO 2
|
||||||
|
+#define PXA1908_CLK_PLL1_624 3
|
||||||
|
+#define PXA1908_CLK_PLL1_416 4
|
||||||
|
+#define PXA1908_CLK_PLL1_499 5
|
||||||
|
+#define PXA1908_CLK_PLL1_832 6
|
||||||
|
+#define PXA1908_CLK_PLL1_1248 7
|
||||||
|
+#define PXA1908_CLK_PLL1_D2 8
|
||||||
|
+#define PXA1908_CLK_PLL1_D4 9
|
||||||
|
+#define PXA1908_CLK_PLL1_D8 10
|
||||||
|
+#define PXA1908_CLK_PLL1_D16 11
|
||||||
|
+#define PXA1908_CLK_PLL1_D6 12
|
||||||
|
+#define PXA1908_CLK_PLL1_D12 13
|
||||||
|
+#define PXA1908_CLK_PLL1_D24 14
|
||||||
|
+#define PXA1908_CLK_PLL1_D48 15
|
||||||
|
+#define PXA1908_CLK_PLL1_D96 16
|
||||||
|
+#define PXA1908_CLK_PLL1_D13 17
|
||||||
|
+#define PXA1908_CLK_PLL1_32 18
|
||||||
|
+#define PXA1908_CLK_PLL1_208 19
|
||||||
|
+#define PXA1908_CLK_PLL1_117 20
|
||||||
|
+#define PXA1908_CLK_PLL1_416_GATE 21
|
||||||
|
+#define PXA1908_CLK_PLL1_624_GATE 22
|
||||||
|
+#define PXA1908_CLK_PLL1_832_GATE 23
|
||||||
|
+#define PXA1908_CLK_PLL1_1248_GATE 24
|
||||||
|
+#define PXA1908_CLK_PLL1_D2_GATE 25
|
||||||
|
+#define PXA1908_CLK_PLL1_499_EN 26
|
||||||
|
+#define PXA1908_CLK_PLL2VCO 27
|
||||||
|
+#define PXA1908_CLK_PLL2 28
|
||||||
|
+#define PXA1908_CLK_PLL2P 29
|
||||||
|
+#define PXA1908_CLK_PLL2VCODIV3 30
|
||||||
|
+#define PXA1908_CLK_PLL3VCO 31
|
||||||
|
+#define PXA1908_CLK_PLL3 32
|
||||||
|
+#define PXA1908_CLK_PLL3P 33
|
||||||
|
+#define PXA1908_CLK_PLL3VCODIV3 34
|
||||||
|
+#define PXA1908_CLK_PLL4VCO 35
|
||||||
|
+#define PXA1908_CLK_PLL4 36
|
||||||
|
+#define PXA1908_CLK_PLL4P 37
|
||||||
|
+#define PXA1908_CLK_PLL4VCODIV3 38
|
||||||
|
+#define PXA1908_MPMU_NR_CLKS 38
|
||||||
|
+
|
||||||
|
+/* apb (apbc) peripherals */
|
||||||
|
+#define PXA1908_CLK_UART0 1
|
||||||
|
+#define PXA1908_CLK_UART1 2
|
||||||
|
+#define PXA1908_CLK_GPIO 3
|
||||||
|
+#define PXA1908_CLK_PWM0 4
|
||||||
|
+#define PXA1908_CLK_PWM1 5
|
||||||
|
+#define PXA1908_CLK_PWM2 6
|
||||||
|
+#define PXA1908_CLK_PWM3 7
|
||||||
|
+#define PXA1908_CLK_SSP0 8
|
||||||
|
+#define PXA1908_CLK_SSP1 9
|
||||||
|
+#define PXA1908_CLK_IPC_RST 10
|
||||||
|
+#define PXA1908_CLK_RTC 11
|
||||||
|
+#define PXA1908_CLK_TWSI0 12
|
||||||
|
+#define PXA1908_CLK_KPC 13
|
||||||
|
+#define PXA1908_CLK_SWJTAG 14
|
||||||
|
+#define PXA1908_CLK_SSP2 15
|
||||||
|
+#define PXA1908_CLK_TWSI1 16
|
||||||
|
+#define PXA1908_CLK_THERMAL 17
|
||||||
|
+#define PXA1908_CLK_TWSI3 18
|
||||||
|
+#define PXA1908_APBC_NR_CLKS 50
|
||||||
|
+
|
||||||
|
+/* apb (apbcp) peripherals */
|
||||||
|
+#define PXA1908_CLK_UART2 1
|
||||||
|
+#define PXA1908_CLK_TWSI2 2
|
||||||
|
+#define PXA1908_CLK_AICER 3
|
||||||
|
+#define PXA1908_APBCP_NR_CLKS 50
|
||||||
|
+
|
||||||
|
+/* axi (apmu) peripherals */
|
||||||
|
+#define PXA1908_CLK_CCIC1 1
|
||||||
|
+#define PXA1908_CLK_ISP 2
|
||||||
|
+#define PXA1908_CLK_DSI1 3
|
||||||
|
+#define PXA1908_CLK_DISP1 4
|
||||||
|
+#define PXA1908_CLK_CCIC0 5
|
||||||
|
+#define PXA1908_CLK_SDH0 6
|
||||||
|
+#define PXA1908_CLK_SDH1 7
|
||||||
|
+#define PXA1908_CLK_USB 8
|
||||||
|
+#define PXA1908_CLK_NF 9
|
||||||
|
+#define PXA1908_CLK_CORE_DEBUG 10
|
||||||
|
+#define PXA1908_CLK_VPU 11
|
||||||
|
+#define PXA1908_CLK_GC 12
|
||||||
|
+#define PXA1908_CLK_SDH2 13
|
||||||
|
+#define PXA1908_CLK_GC2D 14
|
||||||
|
+#define PXA1908_CLK_TRACE 15
|
||||||
|
+#define PXA1908_CLK_DVC_DFC_DEBUG 16
|
||||||
|
+#define PXA1908_APMU_NR_CLKS 50
|
||||||
|
+
|
||||||
|
+#endif
|
||||||
|
--
|
||||||
|
2.41.0
|
||||||
|
|
||||||
|
|
@ -0,0 +1,361 @@
|
||||||
|
From 3db77bd6640b6b160e90b9228af922a5f647f069 Mon Sep 17 00:00:00 2001
|
||||||
|
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
|
||||||
|
Date: Fri, 21 Jul 2023 22:37:46 +0200
|
||||||
|
Subject: [PATCH] clk: mmp: Add Marvell PXA1908 clock driver
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
Add driver for Marvell PXA1908 clock controller blocks. The SoC has
|
||||||
|
numerous clock controller blocks, currently supporting APBC, APBCP, MPMU
|
||||||
|
and APMU.
|
||||||
|
|
||||||
|
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
|
||||||
|
---
|
||||||
|
drivers/clk/mmp/Makefile | 2 +-
|
||||||
|
drivers/clk/mmp/clk-of-pxa1908.c | 323 +++++++++++++++++++++++++++++++
|
||||||
|
2 files changed, 324 insertions(+), 1 deletion(-)
|
||||||
|
create mode 100644 drivers/clk/mmp/clk-of-pxa1908.c
|
||||||
|
|
||||||
|
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
|
||||||
|
index cbcc2f8430a2..feacddb28fc4 100644
|
||||||
|
--- a/drivers/clk/mmp/Makefile
|
||||||
|
+++ b/drivers/clk/mmp/Makefile
|
||||||
|
@@ -15,4 +15,4 @@ obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
|
||||||
|
obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
|
||||||
|
obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o
|
||||||
|
|
||||||
|
-obj-y += clk-of-pxa1928.o
|
||||||
|
+obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o clk-of-pxa1908.o
|
||||||
|
diff --git a/drivers/clk/mmp/clk-of-pxa1908.c b/drivers/clk/mmp/clk-of-pxa1908.c
|
||||||
|
new file mode 100644
|
||||||
|
index 000000000000..520440cb082c
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/drivers/clk/mmp/clk-of-pxa1908.c
|
||||||
|
@@ -0,0 +1,323 @@
|
||||||
|
+// SPDX-License-Identifier: GPL-2.0-only
|
||||||
|
+#include <linux/bits.h>
|
||||||
|
+#include <linux/clk-provider.h>
|
||||||
|
+#include <linux/of_address.h>
|
||||||
|
+#include <linux/slab.h>
|
||||||
|
+#include <linux/spinlock.h>
|
||||||
|
+#include <linux/units.h>
|
||||||
|
+
|
||||||
|
+#include <dt-bindings/clock/marvell,pxa1908.h>
|
||||||
|
+
|
||||||
|
+#include "clk.h"
|
||||||
|
+
|
||||||
|
+#define APMU_CLK_GATE_CTRL 0x40
|
||||||
|
+#define MPMU_UART_PLL 0x14
|
||||||
|
+
|
||||||
|
+#define APBC_UART0 0x0
|
||||||
|
+#define APBC_UART1 0x4
|
||||||
|
+#define APBC_GPIO 0x8
|
||||||
|
+#define APBC_PWM0 0xc
|
||||||
|
+#define APBC_PWM1 0x10
|
||||||
|
+#define APBC_PWM2 0x14
|
||||||
|
+#define APBC_PWM3 0x18
|
||||||
|
+#define APBC_SSP0 0x1c
|
||||||
|
+#define APBC_SSP1 0x20
|
||||||
|
+#define APBC_IPC_RST 0x24
|
||||||
|
+#define APBC_RTC 0x28
|
||||||
|
+#define APBC_TWSI0 0x2c
|
||||||
|
+#define APBC_KPC 0x30
|
||||||
|
+#define APBC_SWJTAG 0x40
|
||||||
|
+#define APBC_SSP2 0x4c
|
||||||
|
+#define APBC_TWSI1 0x60
|
||||||
|
+#define APBC_THERMAL 0x6c
|
||||||
|
+#define APBC_TWSI3 0x70
|
||||||
|
+
|
||||||
|
+#define APBCP_UART2 0x1c
|
||||||
|
+#define APBCP_TWSI2 0x28
|
||||||
|
+#define APBCP_AICER 0x38
|
||||||
|
+
|
||||||
|
+#define APMU_CCIC1 0x24
|
||||||
|
+#define APMU_ISP 0x38
|
||||||
|
+#define APMU_DSI1 0x44
|
||||||
|
+#define APMU_DISP1 0x4c
|
||||||
|
+#define APMU_CCIC0 0x50
|
||||||
|
+#define APMU_SDH0 0x54
|
||||||
|
+#define APMU_SDH1 0x58
|
||||||
|
+#define APMU_USB 0x5c
|
||||||
|
+#define APMU_NF 0x60
|
||||||
|
+#define APMU_VPU 0xa4
|
||||||
|
+#define APMU_GC 0xcc
|
||||||
|
+#define APMU_SDH2 0xe0
|
||||||
|
+#define APMU_GC2D 0xf4
|
||||||
|
+#define APMU_TRACE 0x108
|
||||||
|
+#define APMU_DVC_DFC_DEBUG 0x140
|
||||||
|
+
|
||||||
|
+struct pxa1908_clk_unit {
|
||||||
|
+ struct mmp_clk_unit unit;
|
||||||
|
+ void __iomem *mpmu_base;
|
||||||
|
+ void __iomem *apmu_base;
|
||||||
|
+ void __iomem *apbc_base;
|
||||||
|
+ void __iomem *apbcp_base;
|
||||||
|
+ void __iomem *apbs_base;
|
||||||
|
+ void __iomem *ciu_base;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
|
||||||
|
+ {PXA1908_CLK_CLK32, "clk32", NULL, 0, 32768},
|
||||||
|
+ {PXA1908_CLK_VCTCXO, "vctcxo", NULL, 0, 26 * HZ_PER_MHZ},
|
||||||
|
+ {PXA1908_CLK_PLL1_624, "pll1_624", NULL, 0, 624 * HZ_PER_MHZ},
|
||||||
|
+ {PXA1908_CLK_PLL1_416, "pll1_416", NULL, 0, 416 * HZ_PER_MHZ},
|
||||||
|
+ {PXA1908_CLK_PLL1_499, "pll1_499", NULL, 0, 499 * HZ_PER_MHZ},
|
||||||
|
+ {PXA1908_CLK_PLL1_832, "pll1_832", NULL, 0, 832 * HZ_PER_MHZ},
|
||||||
|
+ {PXA1908_CLK_PLL1_1248, "pll1_1248", NULL, 0, 1248 * HZ_PER_MHZ},
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
|
||||||
|
+ {PXA1908_CLK_PLL1_D2, "pll1_d2", "pll1_624", 1, 2, 0},
|
||||||
|
+ {PXA1908_CLK_PLL1_D4, "pll1_d4", "pll1_d2", 1, 2, 0},
|
||||||
|
+ {PXA1908_CLK_PLL1_D6, "pll1_d6", "pll1_d2", 1, 3, 0},
|
||||||
|
+ {PXA1908_CLK_PLL1_D8, "pll1_d8", "pll1_d4", 1, 2, 0},
|
||||||
|
+ {PXA1908_CLK_PLL1_D12, "pll1_d12", "pll1_d6", 1, 2, 0},
|
||||||
|
+ {PXA1908_CLK_PLL1_D13, "pll1_d13", "pll1_624", 1, 13, 0},
|
||||||
|
+ {PXA1908_CLK_PLL1_D16, "pll1_d16", "pll1_d8", 1, 2, 0},
|
||||||
|
+ {PXA1908_CLK_PLL1_D24, "pll1_d24", "pll1_d12", 1, 2, 0},
|
||||||
|
+ {PXA1908_CLK_PLL1_D48, "pll1_d48", "pll1_d24", 1, 2, 0},
|
||||||
|
+ {PXA1908_CLK_PLL1_D96, "pll1_d96", "pll1_d48", 1, 2, 0},
|
||||||
|
+ {PXA1908_CLK_PLL1_32, "pll1_32", "pll1_d13", 2, 3, 0},
|
||||||
|
+ {PXA1908_CLK_PLL1_208, "pll1_208", "pll1_d2", 2, 3, 0},
|
||||||
|
+ {PXA1908_CLK_PLL1_117, "pll1_117", "pll1_624", 3, 16, 0},
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct mmp_clk_factor_masks uart_factor_masks = {
|
||||||
|
+ .factor = 2,
|
||||||
|
+ .num_mask = GENMASK(12, 0),
|
||||||
|
+ .den_mask = GENMASK(12, 0),
|
||||||
|
+ .num_shift = 16,
|
||||||
|
+ .den_shift = 0,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct u32_fract uart_factor_tbl[] = {
|
||||||
|
+ {.numerator = 8125, .denominator = 1536}, /* 14.745MHz */
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static DEFINE_SPINLOCK(pll1_lock);
|
||||||
|
+static struct mmp_param_general_gate_clk pll1_gate_clks[] = {
|
||||||
|
+ {PXA1908_CLK_PLL1_D2_GATE, "pll1_d2_gate", "pll1_d2", 0, APMU_CLK_GATE_CTRL, 29, 0, &pll1_lock},
|
||||||
|
+ {PXA1908_CLK_PLL1_416_GATE, "pll1_416_gate", "pll1_416", 0, APMU_CLK_GATE_CTRL, 27, 0, &pll1_lock},
|
||||||
|
+ {PXA1908_CLK_PLL1_624_GATE, "pll1_624_gate", "pll1_624", 0, APMU_CLK_GATE_CTRL, 26, 0, &pll1_lock},
|
||||||
|
+ {PXA1908_CLK_PLL1_832_GATE, "pll1_832_gate", "pll1_832", 0, APMU_CLK_GATE_CTRL, 30, 0, &pll1_lock},
|
||||||
|
+ {PXA1908_CLK_PLL1_1248_GATE, "pll1_1248_gate", "pll1_1248", 0, APMU_CLK_GATE_CTRL, 28, 0, &pll1_lock},
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static void pxa1908_pll_init(struct pxa1908_clk_unit *pxa_unit)
|
||||||
|
+{
|
||||||
|
+ struct mmp_clk_unit *unit = &pxa_unit->unit;
|
||||||
|
+
|
||||||
|
+ mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
|
||||||
|
+ ARRAY_SIZE(fixed_rate_clks));
|
||||||
|
+
|
||||||
|
+ mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
|
||||||
|
+ ARRAY_SIZE(fixed_factor_clks));
|
||||||
|
+
|
||||||
|
+ mmp_clk_register_factor("uart_pll", "pll1_d4",
|
||||||
|
+ CLK_SET_RATE_PARENT,
|
||||||
|
+ pxa_unit->mpmu_base + MPMU_UART_PLL,
|
||||||
|
+ &uart_factor_masks, uart_factor_tbl,
|
||||||
|
+ ARRAY_SIZE(uart_factor_tbl), NULL);
|
||||||
|
+
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static DEFINE_SPINLOCK(pwm0_lock);
|
||||||
|
+static DEFINE_SPINLOCK(pwm2_lock);
|
||||||
|
+
|
||||||
|
+static DEFINE_SPINLOCK(uart0_lock);
|
||||||
|
+static DEFINE_SPINLOCK(uart1_lock);
|
||||||
|
+static DEFINE_SPINLOCK(uart2_lock);
|
||||||
|
+
|
||||||
|
+static const char * const uart_parent_names[] = {"pll1_117", "uart_pll"};
|
||||||
|
+static const char * const ssp_parent_names[] = {"pll1_d16", "pll1_d48", "pll1_d24", "pll1_d12"};
|
||||||
|
+
|
||||||
|
+static struct mmp_param_gate_clk apbc_gate_clks[] = {
|
||||||
|
+ {PXA1908_CLK_TWSI0, "twsi0_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 3, 0, 0, NULL},
|
||||||
|
+ {PXA1908_CLK_TWSI1, "twsi1_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 3, 0, 0, NULL},
|
||||||
|
+ {PXA1908_CLK_TWSI3, "twsi3_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 3, 0, 0, NULL},
|
||||||
|
+ {PXA1908_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 3, 0, 0, NULL},
|
||||||
|
+ {PXA1908_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 3, 0, MMP_CLK_GATE_NEED_DELAY, NULL},
|
||||||
|
+ {PXA1908_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0, MMP_CLK_GATE_NEED_DELAY, NULL},
|
||||||
|
+ {PXA1908_CLK_PWM0, "pwm0_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_PWM0, 0x2, 2, 0, 0, &pwm0_lock},
|
||||||
|
+ {PXA1908_CLK_PWM1, "pwm1_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_PWM1, 0x6, 2, 0, 0, NULL},
|
||||||
|
+ {PXA1908_CLK_PWM2, "pwm2_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_PWM2, 0x2, 2, 0, 0, NULL},
|
||||||
|
+ {PXA1908_CLK_PWM3, "pwm3_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_PWM3, 0x6, 2, 0, 0, NULL},
|
||||||
|
+ {PXA1908_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 3, 0, 0, &uart0_lock},
|
||||||
|
+ {PXA1908_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 3, 0, 0, &uart1_lock},
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct mmp_param_mux_clk apbc_mux_clks[] = {
|
||||||
|
+ {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
|
||||||
|
+ {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
|
||||||
|
+ {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), 0, APBC_SSP0, 4, 3, 0, NULL},
|
||||||
|
+ {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), 0, APBC_SSP2, 4, 3, 0, NULL},
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static void pxa1908_apb_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
|
||||||
|
+{
|
||||||
|
+ struct mmp_clk_unit *unit = &pxa_unit->unit;
|
||||||
|
+
|
||||||
|
+ mmp_clk_register_gate(NULL, "pwm01_apb_share", "pll1_d48",
|
||||||
|
+ CLK_SET_RATE_PARENT,
|
||||||
|
+ pxa_unit->apbc_base + APBC_PWM0,
|
||||||
|
+ 0x5, 1, 0, 0, &pwm0_lock);
|
||||||
|
+ mmp_clk_register_gate(NULL, "pwm23_apb_share", "pll1_d48",
|
||||||
|
+ CLK_SET_RATE_PARENT,
|
||||||
|
+ pxa_unit->apbc_base + APBC_PWM2,
|
||||||
|
+ 0x5, 1, 0, 0, &pwm2_lock);
|
||||||
|
+ mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
|
||||||
|
+ ARRAY_SIZE(apbc_mux_clks));
|
||||||
|
+ mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
|
||||||
|
+ ARRAY_SIZE(apbc_gate_clks));
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static struct mmp_param_gate_clk apbcp_gate_clks[] = {
|
||||||
|
+ {PXA1908_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock},
|
||||||
|
+ {PXA1908_CLK_TWSI2, "twsi2_clk", "pll1_32", CLK_SET_RATE_PARENT, APBCP_TWSI2, 0x7, 0x3, 0x0, 0, NULL},
|
||||||
|
+ {PXA1908_CLK_AICER, "ripc_clk", NULL, 0, APBCP_AICER, 0x7, 0x2, 0x0, 0, NULL},
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct mmp_param_mux_clk apbcp_mux_clks[] = {
|
||||||
|
+ {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock},
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static void pxa1908_apb_p_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
|
||||||
|
+{
|
||||||
|
+ struct mmp_clk_unit *unit = &pxa_unit->unit;
|
||||||
|
+
|
||||||
|
+ mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->apbcp_base,
|
||||||
|
+ ARRAY_SIZE(apbcp_mux_clks));
|
||||||
|
+ mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->apbcp_base,
|
||||||
|
+ ARRAY_SIZE(apbcp_gate_clks));
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static DEFINE_SPINLOCK(sdh0_lock);
|
||||||
|
+static DEFINE_SPINLOCK(sdh1_lock);
|
||||||
|
+static DEFINE_SPINLOCK(sdh2_lock);
|
||||||
|
+
|
||||||
|
+static const char * const sdh_parent_names[] = {"pll1_416", "pll1_624"};
|
||||||
|
+
|
||||||
|
+static struct mmp_clk_mix_config sdh_mix_config = {
|
||||||
|
+ .reg_info = DEFINE_MIX_REG_INFO(3, 8, 2, 6, 11),
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct mmp_param_gate_clk apmu_gate_clks[] = {
|
||||||
|
+ {PXA1908_CLK_USB, "usb_clk", NULL, 0, APMU_USB, 0x9, 0x9, 0x1, 0, NULL},
|
||||||
|
+ {PXA1908_CLK_SDH0, "sdh0_clk", "sdh0_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH0, 0x12, 0x12, 0x0, 0, &sdh0_lock},
|
||||||
|
+ {PXA1908_CLK_SDH1, "sdh1_clk", "sdh1_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH1, 0x12, 0x12, 0x0, 0, &sdh1_lock},
|
||||||
|
+ {PXA1908_CLK_SDH2, "sdh2_clk", "sdh2_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH2, 0x12, 0x12, 0x0, 0, &sdh2_lock}
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static void pxa1908_axi_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
|
||||||
|
+{
|
||||||
|
+ struct mmp_clk_unit *unit = &pxa_unit->unit;
|
||||||
|
+
|
||||||
|
+ mmp_register_general_gate_clks(unit, pll1_gate_clks,
|
||||||
|
+ pxa_unit->apmu_base, ARRAY_SIZE(pll1_gate_clks));
|
||||||
|
+
|
||||||
|
+ sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0;
|
||||||
|
+ mmp_clk_register_mix(NULL, "sdh0_mix_clk", sdh_parent_names,
|
||||||
|
+ ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
|
||||||
|
+ &sdh_mix_config, &sdh0_lock);
|
||||||
|
+ sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH1;
|
||||||
|
+ mmp_clk_register_mix(NULL, "sdh1_mix_clk", sdh_parent_names,
|
||||||
|
+ ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
|
||||||
|
+ &sdh_mix_config, &sdh1_lock);
|
||||||
|
+ sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH2;
|
||||||
|
+ mmp_clk_register_mix(NULL, "sdh2_mix_clk", sdh_parent_names,
|
||||||
|
+ ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
|
||||||
|
+ &sdh_mix_config, &sdh2_lock);
|
||||||
|
+
|
||||||
|
+ mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
|
||||||
|
+ ARRAY_SIZE(apmu_gate_clks));
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void __init pxa1908_apbc_clk_init(struct device_node *np)
|
||||||
|
+{
|
||||||
|
+ struct pxa1908_clk_unit *pxa_unit;
|
||||||
|
+
|
||||||
|
+ pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
|
||||||
|
+ if (!pxa_unit)
|
||||||
|
+ return;
|
||||||
|
+
|
||||||
|
+ pxa_unit->apbc_base = of_iomap(np, 0);
|
||||||
|
+ if (!pxa_unit->apbc_base) {
|
||||||
|
+ pr_err("failed to map apbc registers\n");
|
||||||
|
+ kfree(pxa_unit);
|
||||||
|
+ return;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ mmp_clk_init(np, &pxa_unit->unit, PXA1908_APBC_NR_CLKS);
|
||||||
|
+
|
||||||
|
+ pxa1908_apb_periph_clk_init(pxa_unit);
|
||||||
|
+}
|
||||||
|
+CLK_OF_DECLARE(pxa1908_apbc, "marvell,pxa1908-apbc", pxa1908_apbc_clk_init);
|
||||||
|
+
|
||||||
|
+static void __init pxa1908_apbcp_clk_init(struct device_node *np)
|
||||||
|
+{
|
||||||
|
+ struct pxa1908_clk_unit *pxa_unit;
|
||||||
|
+
|
||||||
|
+ pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
|
||||||
|
+ if (!pxa_unit)
|
||||||
|
+ return;
|
||||||
|
+
|
||||||
|
+ pxa_unit->apbcp_base = of_iomap(np, 0);
|
||||||
|
+ if (!pxa_unit->apbcp_base) {
|
||||||
|
+ pr_err("failed to map apbcp registers\n");
|
||||||
|
+ kfree(pxa_unit);
|
||||||
|
+ return;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ mmp_clk_init(np, &pxa_unit->unit, PXA1908_APBCP_NR_CLKS);
|
||||||
|
+
|
||||||
|
+ pxa1908_apb_p_periph_clk_init(pxa_unit);
|
||||||
|
+}
|
||||||
|
+CLK_OF_DECLARE(pxa1908_apbcp, "marvell,pxa1908-apbcp", pxa1908_apbcp_clk_init);
|
||||||
|
+
|
||||||
|
+static void __init pxa1908_mpmu_clk_init(struct device_node *np)
|
||||||
|
+{
|
||||||
|
+ struct pxa1908_clk_unit *pxa_unit;
|
||||||
|
+
|
||||||
|
+ pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
|
||||||
|
+ if (!pxa_unit)
|
||||||
|
+ return;
|
||||||
|
+
|
||||||
|
+ pxa_unit->mpmu_base = of_iomap(np, 0);
|
||||||
|
+ if (!pxa_unit->mpmu_base) {
|
||||||
|
+ pr_err("failed to map mpmu registers\n");
|
||||||
|
+ kfree(pxa_unit);
|
||||||
|
+ return;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ mmp_clk_init(np, &pxa_unit->unit, PXA1908_MPMU_NR_CLKS);
|
||||||
|
+
|
||||||
|
+ pxa1908_pll_init(pxa_unit);
|
||||||
|
+}
|
||||||
|
+CLK_OF_DECLARE(pxa1908_mpmu, "marvell,pxa1908-mpmu", pxa1908_mpmu_clk_init);
|
||||||
|
+
|
||||||
|
+static void __init pxa1908_apmu_clk_init(struct device_node *np)
|
||||||
|
+{
|
||||||
|
+ struct pxa1908_clk_unit *pxa_unit;
|
||||||
|
+
|
||||||
|
+ pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
|
||||||
|
+ if (!pxa_unit)
|
||||||
|
+ return;
|
||||||
|
+
|
||||||
|
+ pxa_unit->apmu_base = of_iomap(np, 0);
|
||||||
|
+ if (!pxa_unit->apmu_base) {
|
||||||
|
+ pr_err("failed to map apmu registers\n");
|
||||||
|
+ kfree(pxa_unit);
|
||||||
|
+ return;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ mmp_clk_init(np, &pxa_unit->unit, PXA1908_APMU_NR_CLKS);
|
||||||
|
+
|
||||||
|
+ pxa1908_axi_periph_clk_init(pxa_unit);
|
||||||
|
+}
|
||||||
|
+CLK_OF_DECLARE(pxa1908_apmu, "marvell,pxa1908-apmu", pxa1908_apmu_clk_init);
|
||||||
|
--
|
||||||
|
2.41.0
|
||||||
|
|
||||||
|
|
@ -0,0 +1,34 @@
|
||||||
|
From 4a92c2d243b9516d119fb631666ec44d212e4405 Mon Sep 17 00:00:00 2001
|
||||||
|
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
|
||||||
|
Date: Fri, 21 Jul 2023 22:37:51 +0200
|
||||||
|
Subject: [PATCH] dt-bindings: marvell: Document PXA1908 SoC
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
Add dt binding for the Marvell PXA1908 SoC.
|
||||||
|
|
||||||
|
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
|
||||||
|
---
|
||||||
|
Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml | 5 +++++
|
||||||
|
1 file changed, 5 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
|
||||||
|
index 4c43eaf3632e..f73bb8ec3a1a 100644
|
||||||
|
--- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
|
||||||
|
+++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
|
||||||
|
@@ -35,6 +35,11 @@ properties:
|
||||||
|
- enum:
|
||||||
|
- dell,wyse-ariel
|
||||||
|
- const: marvell,mmp3
|
||||||
|
+ - description: PXA1908 based boards
|
||||||
|
+ items:
|
||||||
|
+ - enum:
|
||||||
|
+ - samsung,coreprimevelte
|
||||||
|
+ - const: marvell,pxa1908
|
||||||
|
|
||||||
|
additionalProperties: true
|
||||||
|
|
||||||
|
--
|
||||||
|
2.41.0
|
||||||
|
|
||||||
|
|
@ -0,0 +1,41 @@
|
||||||
|
From 2752ad57729b4b4f769c6014b81fdc3f6c416ba6 Mon Sep 17 00:00:00 2001
|
||||||
|
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
|
||||||
|
Date: Fri, 21 Jul 2023 22:37:49 +0200
|
||||||
|
Subject: [PATCH] arm64: Kconfig.platforms: Add config for Marvell PXA1908
|
||||||
|
platform
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
Add ARCH_MMP configuration option for Marvell PXA1908 SoC.
|
||||||
|
|
||||||
|
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
|
||||||
|
---
|
||||||
|
arch/arm64/Kconfig.platforms | 11 +++++++++++
|
||||||
|
1 file changed, 11 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
|
||||||
|
index 6069120199bb..b417cae42c84 100644
|
||||||
|
--- a/arch/arm64/Kconfig.platforms
|
||||||
|
+++ b/arch/arm64/Kconfig.platforms
|
||||||
|
@@ -89,6 +89,17 @@ config ARCH_BERLIN
|
||||||
|
help
|
||||||
|
This enables support for Marvell Berlin SoC Family
|
||||||
|
|
||||||
|
+config ARCH_MMP
|
||||||
|
+ bool "Marvell MMP SoC Family"
|
||||||
|
+ select ARM_GIC
|
||||||
|
+ select ARM_ARCH_TIMER
|
||||||
|
+ select ARM_SMMU
|
||||||
|
+ select MMP_PDMA
|
||||||
|
+ select PINCTRL_SINGLE
|
||||||
|
+ help
|
||||||
|
+ This enables support for Marvell MMP SoC family, currently
|
||||||
|
+ supporting PXA1908 aka IAP140.
|
||||||
|
+
|
||||||
|
config ARCH_BITMAIN
|
||||||
|
bool "Bitmain SoC Platforms"
|
||||||
|
help
|
||||||
|
--
|
||||||
|
2.41.0
|
||||||
|
|
||||||
|
|
@ -0,0 +1,671 @@
|
||||||
|
From bcd581ae175ab72d3ffa81386e11837923fb4328 Mon Sep 17 00:00:00 2001
|
||||||
|
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
|
||||||
|
Date: Fri, 21 Jul 2023 22:37:50 +0200
|
||||||
|
Subject: [PATCH] arm64: dts: Add DTS for Marvell PXA1908 and
|
||||||
|
samsung,coreprimevelte
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
Add DTS for Marvell PXA1908 SoC and Samsung Galaxy Core Prime Value
|
||||||
|
Edition LTE, a smartphone based on said SoC.
|
||||||
|
|
||||||
|
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
|
||||||
|
---
|
||||||
|
arch/arm64/boot/dts/marvell/Makefile | 3 +
|
||||||
|
.../pxa1908-samsung-coreprimevelte.dts | 332 ++++++++++++++++++
|
||||||
|
arch/arm64/boot/dts/marvell/pxa1908.dtsi | 292 +++++++++++++++
|
||||||
|
3 files changed, 627 insertions(+)
|
||||||
|
create mode 100644 arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
|
||||||
|
create mode 100644 arch/arm64/boot/dts/marvell/pxa1908.dtsi
|
||||||
|
|
||||||
|
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
|
||||||
|
index 79ac09b58a89..263be6ec7567 100644
|
||||||
|
--- a/arch/arm64/boot/dts/marvell/Makefile
|
||||||
|
+++ b/arch/arm64/boot/dts/marvell/Makefile
|
||||||
|
@@ -27,3 +27,6 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb
|
||||||
|
+
|
||||||
|
+# MMP SoC Family
|
||||||
|
+dtb-$(CONFIG_ARCH_MMP) += pxa1908-samsung-coreprimevelte.dtb
|
||||||
|
diff --git a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
|
||||||
|
new file mode 100644
|
||||||
|
index 000000000000..59e5d6f15dd2
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
|
||||||
|
@@ -0,0 +1,332 @@
|
||||||
|
+// SPDX-License-Identifier: GPL-2.0-only
|
||||||
|
+#include "pxa1908.dtsi"
|
||||||
|
+#include <dt-bindings/gpio/gpio.h>
|
||||||
|
+#include <dt-bindings/input/linux-event-codes.h>
|
||||||
|
+
|
||||||
|
+/ {
|
||||||
|
+ model = "Samsung Galaxy Core Prime VE LTE";
|
||||||
|
+ compatible = "samsung,coreprimevelte", "marvell,pxa1908";
|
||||||
|
+
|
||||||
|
+ aliases {
|
||||||
|
+ mmc0 = &sdh2; /* eMMC */
|
||||||
|
+ mmc1 = &sdh0; /* SD card */
|
||||||
|
+ serial0 = &uart0;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ chosen {
|
||||||
|
+ #address-cells = <2>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+ ranges;
|
||||||
|
+
|
||||||
|
+ stdout-path = "serial0:115200n8";
|
||||||
|
+
|
||||||
|
+ fb0: framebuffer@17177000 {
|
||||||
|
+ compatible = "simple-framebuffer";
|
||||||
|
+ reg = <0 0x17177000 0 (480 * 800 * 4)>;
|
||||||
|
+ width = <480>;
|
||||||
|
+ height = <800>;
|
||||||
|
+ stride = <(480 * 4)>;
|
||||||
|
+ format = "a8r8g8b8";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ /* Bootloader fills this in */
|
||||||
|
+ memory {
|
||||||
|
+ device_type = "memory";
|
||||||
|
+ reg = <0 0 0 0>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ reserved-memory {
|
||||||
|
+ #address-cells = <2>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+ ranges;
|
||||||
|
+
|
||||||
|
+ framebuffer@17000000 {
|
||||||
|
+ reg = <0 0x17000000 0 0x1800000>;
|
||||||
|
+ no-map;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ gpu@9000000 {
|
||||||
|
+ reg = <0 0x9000000 0 0x1000000>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ /* Communications processor, aka modem */
|
||||||
|
+ cp@3000000 {
|
||||||
|
+ reg = <0 0x3000000 0 0x5000000>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ cm3@a000000 {
|
||||||
|
+ reg = <0 0xa000000 0 0x80000>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ seclog@8000000 {
|
||||||
|
+ reg = <0 0x8000000 0 0x100000>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ ramoops@8100000 {
|
||||||
|
+ compatible = "ramoops";
|
||||||
|
+ reg = <0 0x8100000 0 0x40000>;
|
||||||
|
+ record-size = <0x8000>;
|
||||||
|
+ console-size = <0x20000>;
|
||||||
|
+ max-reason = <5>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+ i2c-muic {
|
||||||
|
+ compatible = "i2c-gpio";
|
||||||
|
+ sda-gpios = <&gpio 30 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
|
||||||
|
+ scl-gpios = <&gpio 29 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
|
||||||
|
+ i2c-gpio,delay-us = <3>;
|
||||||
|
+ i2c-gpio,timeout-ms = <100>;
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <0>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ pinctrl-0 = <&i2c_muic_pins>;
|
||||||
|
+
|
||||||
|
+ muic: extcon@14 {
|
||||||
|
+ compatible = "siliconmitus,sm5504-muic";
|
||||||
|
+ reg = <0x14>;
|
||||||
|
+ interrupt-parent = <&gpio>;
|
||||||
|
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ gpio-keys {
|
||||||
|
+ compatible = "gpio-keys";
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ pinctrl-0 = <&gpio_keys_pins>;
|
||||||
|
+ autorepeat;
|
||||||
|
+
|
||||||
|
+ key-home {
|
||||||
|
+ label = "Home";
|
||||||
|
+ linux,code = <KEY_HOME>;
|
||||||
|
+ gpios = <&gpio 50 GPIO_ACTIVE_LOW>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ key-volup {
|
||||||
|
+ label = "Volume Up";
|
||||||
|
+ linux,code = <KEY_VOLUMEUP>;
|
||||||
|
+ gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ key-voldown {
|
||||||
|
+ label = "Volume Down";
|
||||||
|
+ linux,code = <KEY_VOLUMEDOWN>;
|
||||||
|
+ gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&smmu {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&pmx {
|
||||||
|
+ pinctrl-single,gpio-range = <&range 55 55 0>,
|
||||||
|
+ <&range 110 32 0>,
|
||||||
|
+ <&range 52 1 0>;
|
||||||
|
+
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ pinctrl-0 = <&board_pins_1 &board_pins_2 &board_pins_3>;
|
||||||
|
+
|
||||||
|
+ board_pins_1: pinmux-board-1 {
|
||||||
|
+ pinctrl-single,pins = <
|
||||||
|
+ 0x160 0
|
||||||
|
+ 0x164 0
|
||||||
|
+ 0x168 0
|
||||||
|
+ 0x16c 0
|
||||||
|
+ >;
|
||||||
|
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
|
||||||
|
+ pinctrl-single,bias-pullup = <0x8000 0x8000 0 0xc000>;
|
||||||
|
+ pinctrl-single,bias-pulldown = <0x8000 0x8000 0 0xa000>;
|
||||||
|
+ pinctrl-single,input-schmitt = <0 0x30>;
|
||||||
|
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
|
||||||
|
+ pinctrl-single,low-power-mode = <0x288 0x388>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ board_pins_2: pinmux-board-2 {
|
||||||
|
+ pinctrl-single,pins = <
|
||||||
|
+ 0x44 1
|
||||||
|
+ 0x48 1
|
||||||
|
+ 0x20 1
|
||||||
|
+ 0x18 1
|
||||||
|
+ 0x14 1
|
||||||
|
+ 0x10 1
|
||||||
|
+ 0xc 1
|
||||||
|
+ 0x8 1
|
||||||
|
+ 0x68 1
|
||||||
|
+ 0x58 0
|
||||||
|
+ 0x54 0
|
||||||
|
+ 0x7c 0
|
||||||
|
+ 0x6c 0
|
||||||
|
+ 0x70 0
|
||||||
|
+ 0x4c 1
|
||||||
|
+ 0x50 1
|
||||||
|
+ 0xac 0
|
||||||
|
+ 0x90 0
|
||||||
|
+ 0x8c 0
|
||||||
|
+ 0x88 0
|
||||||
|
+ 0x84 0
|
||||||
|
+ 0xc8 0
|
||||||
|
+ 0x128 0
|
||||||
|
+ 0x190 0
|
||||||
|
+ 0x194 0
|
||||||
|
+ 0x1a0 0
|
||||||
|
+ 0x114 0
|
||||||
|
+ 0x118 0
|
||||||
|
+ 0x1d8 0
|
||||||
|
+ 0x1e4 0
|
||||||
|
+ 0xe8 0
|
||||||
|
+ 0x100 0
|
||||||
|
+ 0x204 0
|
||||||
|
+ 0x210 0
|
||||||
|
+ 0x218 0
|
||||||
|
+ >;
|
||||||
|
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
|
||||||
|
+ pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xc000>;
|
||||||
|
+ pinctrl-single,low-power-mode = <0x288 0x388>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ board_pins_3: pinmux-board-3 {
|
||||||
|
+ pinctrl-single,pins = <
|
||||||
|
+ 0x260 0
|
||||||
|
+ 0x264 0
|
||||||
|
+ 0x268 0
|
||||||
|
+ 0x26c 0
|
||||||
|
+ 0x270 0
|
||||||
|
+ 0x274 0
|
||||||
|
+ 0x78 0
|
||||||
|
+ 0x74 0
|
||||||
|
+ 0xb0 1
|
||||||
|
+ >;
|
||||||
|
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
|
||||||
|
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
|
||||||
|
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
|
||||||
|
+ pinctrl-single,input-schmitt = <0 0x30>;
|
||||||
|
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
|
||||||
|
+ pinctrl-single,low-power-mode = <0 0x388>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ uart0_pins: pinmux-uart0 {
|
||||||
|
+ pinctrl-single,pins = <
|
||||||
|
+ 0x198 6
|
||||||
|
+ 0x19c 6
|
||||||
|
+ >;
|
||||||
|
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
|
||||||
|
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
|
||||||
|
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
|
||||||
|
+ pinctrl-single,input-schmitt = <0 0x30>;
|
||||||
|
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
|
||||||
|
+ pinctrl-single,low-power-mode = <0 0x388>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ gpio_keys_pins: pinmux-gpio-keys {
|
||||||
|
+ pinctrl-single,pins = <
|
||||||
|
+ 0x11c 0
|
||||||
|
+ 0x120 0
|
||||||
|
+ 0x1a4 0
|
||||||
|
+ >;
|
||||||
|
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
|
||||||
|
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
|
||||||
|
+ pinctrl-single,bias-pulldown = <0x8000 0xa0000 0x8000 0xa000>;
|
||||||
|
+ pinctrl-single,input-schmitt = <0 0x30>;
|
||||||
|
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
|
||||||
|
+ pinctrl-single,low-power-mode = <0 0x388>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ i2c_muic_pins: pinmux-i2c-muic {
|
||||||
|
+ pinctrl-single,pins = <
|
||||||
|
+ 0x154 0
|
||||||
|
+ 0x150 0
|
||||||
|
+ >;
|
||||||
|
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
|
||||||
|
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
|
||||||
|
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
|
||||||
|
+ pinctrl-single,input-schmitt = <0 0x30>;
|
||||||
|
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
|
||||||
|
+ pinctrl-single,low-power-mode = <0x288 0x388>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ sdh0_pins_1: pinmux-sdh0-1 {
|
||||||
|
+ pinctrl-single,pins = <
|
||||||
|
+ 0x108 0
|
||||||
|
+ >;
|
||||||
|
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
|
||||||
|
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
|
||||||
|
+ pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>;
|
||||||
|
+ pinctrl-single,input-schmitt = <0 0x30>;
|
||||||
|
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
|
||||||
|
+ pinctrl-single,low-power-mode = <0 0x388>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ sdh0_pins_2: pinmux-sdh0-2 {
|
||||||
|
+ pinctrl-single,pins = <
|
||||||
|
+ 0x94 0
|
||||||
|
+ 0x98 0
|
||||||
|
+ 0x9c 0
|
||||||
|
+ 0xa0 0
|
||||||
|
+ 0xa4 0
|
||||||
|
+ >;
|
||||||
|
+ pinctrl-single,drive-strength = <0x800 0x1800>;
|
||||||
|
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
|
||||||
|
+ pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>;
|
||||||
|
+ pinctrl-single,input-schmitt = <0 0x30>;
|
||||||
|
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
|
||||||
|
+ pinctrl-single,low-power-mode = <0 0x388>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ sdh0_pins_3: pinmux-sdh0-3 {
|
||||||
|
+ pinctrl-single,pins = <
|
||||||
|
+ 0xa8 0
|
||||||
|
+ >;
|
||||||
|
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
|
||||||
|
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
|
||||||
|
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
|
||||||
|
+ pinctrl-single,input-schmitt = <0 0x30>;
|
||||||
|
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
|
||||||
|
+ pinctrl-single,low-power-mode = <0x208 0x388>;
|
||||||
|
+ };
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&uart0 {
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ pinctrl-0 = <&uart0_pins>;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&twsi0 {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&twsi1 {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&twsi2 {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&twsi3 {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&usb {
|
||||||
|
+ extcon = <&muic>, <&muic>;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&sdh2 {
|
||||||
|
+ /* Disabled for now because initialization fails with -ETIMEDOUT. */
|
||||||
|
+ status = "disabled";
|
||||||
|
+ bus-width = <8>;
|
||||||
|
+ non-removable;
|
||||||
|
+ broken-cd;
|
||||||
|
+ mmc-ddr-1_8v;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&sdh0 {
|
||||||
|
+ pinctrl-0 = <&sdh0_pins_1 &sdh0_pins_2 &sdh0_pins_3>;
|
||||||
|
+ cd-gpios = <&gpio 11 0>;
|
||||||
|
+ cd-inverted;
|
||||||
|
+ bus-width = <4>;
|
||||||
|
+ wp-inverted;
|
||||||
|
+};
|
||||||
|
diff --git a/arch/arm64/boot/dts/marvell/pxa1908.dtsi b/arch/arm64/boot/dts/marvell/pxa1908.dtsi
|
||||||
|
new file mode 100644
|
||||||
|
index 000000000000..59b3e609bb24
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/arch/arm64/boot/dts/marvell/pxa1908.dtsi
|
||||||
|
@@ -0,0 +1,292 @@
|
||||||
|
+// SPDX-License-Identifier: GPL-2.0-only
|
||||||
|
+/dts-v1/;
|
||||||
|
+
|
||||||
|
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
+#include <dt-bindings/clock/marvell,pxa1908.h>
|
||||||
|
+
|
||||||
|
+/ {
|
||||||
|
+ model = "Marvell Armada PXA1908";
|
||||||
|
+ compatible = "marvell,pxa1908";
|
||||||
|
+ #address-cells = <2>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+ interrupt-parent = <&gic>;
|
||||||
|
+
|
||||||
|
+ cpus {
|
||||||
|
+ #address-cells = <2>;
|
||||||
|
+ #size-cells = <0>;
|
||||||
|
+
|
||||||
|
+ cpu@0 {
|
||||||
|
+ device_type = "cpu";
|
||||||
|
+ compatible = "arm,cortex-a53";
|
||||||
|
+ reg = <0 0>;
|
||||||
|
+ enable-method = "psci";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ cpu@1 {
|
||||||
|
+ device_type = "cpu";
|
||||||
|
+ compatible = "arm,cortex-a53";
|
||||||
|
+ reg = <0 1>;
|
||||||
|
+ enable-method = "psci";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ cpu@2 {
|
||||||
|
+ device_type = "cpu";
|
||||||
|
+ compatible = "arm,cortex-a53";
|
||||||
|
+ reg = <0 2>;
|
||||||
|
+ enable-method = "psci";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ cpu@3 {
|
||||||
|
+ device_type = "cpu";
|
||||||
|
+ compatible = "arm,cortex-a53";
|
||||||
|
+ reg = <0 3>;
|
||||||
|
+ enable-method = "psci";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ psci {
|
||||||
|
+ compatible = "arm,psci-0.2";
|
||||||
|
+ method = "smc";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ timer {
|
||||||
|
+ compatible = "arm,armv8-timer";
|
||||||
|
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||||
|
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||||
|
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||||
|
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ soc {
|
||||||
|
+ compatible = "simple-bus";
|
||||||
|
+ #address-cells = <2>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+ ranges;
|
||||||
|
+
|
||||||
|
+ smmu: iommu@c0010000 {
|
||||||
|
+ compatible = "arm,mmu-400";
|
||||||
|
+ reg = <0 0xc0010000 0 0x10000>;
|
||||||
|
+ #global-interrupts = <1>;
|
||||||
|
+ #iommu-cells = <1>;
|
||||||
|
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ gic: interrupt-controller@d1df9000 {
|
||||||
|
+ compatible = "arm,gic-400";
|
||||||
|
+ reg = <0 0xd1df9000 0 0x1000>,
|
||||||
|
+ <0 0xd1dfa000 0 0x2000>;
|
||||||
|
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||||
|
+ interrupt-controller;
|
||||||
|
+ #interrupt-cells = <3>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ apb@d4000000 {
|
||||||
|
+ compatible = "simple-bus";
|
||||||
|
+ reg = <0 0xd4000000 0 0x200000>;
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <1>;
|
||||||
|
+ ranges = <0 0 0xd4000000 0x200000>;
|
||||||
|
+
|
||||||
|
+ pdma: dma-controller@0 {
|
||||||
|
+ compatible = "marvell,pdma-1.0";
|
||||||
|
+ reg = <0 0x10000>;
|
||||||
|
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ dma-channels = <30>;
|
||||||
|
+ #dma-cells = <2>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ twsi1: i2c@10800 {
|
||||||
|
+ compatible = "mrvl,mmp-twsi";
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <0>;
|
||||||
|
+ reg = <0x10800 0x64>;
|
||||||
|
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&apbc PXA1908_CLK_TWSI1>;
|
||||||
|
+ mrvl,i2c-fast-mode;
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ twsi0: i2c@11000 {
|
||||||
|
+ compatible = "mrvl,mmp-twsi";
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <0>;
|
||||||
|
+ reg = <0x11000 0x64>;
|
||||||
|
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&apbc PXA1908_CLK_TWSI0>;
|
||||||
|
+ mrvl,i2c-fast-mode;
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ twsi3: i2c@13800 {
|
||||||
|
+ compatible = "mrvl,mmp-twsi";
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <0>;
|
||||||
|
+ reg = <0x13800 0x64>;
|
||||||
|
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&apbc PXA1908_CLK_TWSI3>;
|
||||||
|
+ mrvl,i2c-fast-mode;
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ apbc: clock-controller@15000 {
|
||||||
|
+ compatible = "marvell,pxa1908-apbc";
|
||||||
|
+ reg = <0x15000 0x1000>;
|
||||||
|
+ #clock-cells = <1>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ uart0: serial@17000 {
|
||||||
|
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
|
||||||
|
+ reg = <0x17000 0x1000>;
|
||||||
|
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&apbc PXA1908_CLK_UART0>;
|
||||||
|
+ reg-shift = <2>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ uart1: serial@18000 {
|
||||||
|
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
|
||||||
|
+ reg = <0x18000 0x1000>;
|
||||||
|
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&apbc PXA1908_CLK_UART1>;
|
||||||
|
+ reg-shift = <2>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ gpio: gpio@19000 {
|
||||||
|
+ compatible = "marvell,mmp-gpio";
|
||||||
|
+ reg = <0x19000 0x800>;
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <1>;
|
||||||
|
+ gpio-controller;
|
||||||
|
+ #gpio-cells = <2>;
|
||||||
|
+ clocks = <&apbc PXA1908_CLK_GPIO>;
|
||||||
|
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ interrupt-names = "gpio_mux";
|
||||||
|
+ interrupt-controller;
|
||||||
|
+ #interrupt-cells = <2>;
|
||||||
|
+ ranges = <0 0x19000 0x800>;
|
||||||
|
+
|
||||||
|
+ gpio@0 {
|
||||||
|
+ reg = <0x0 0x4>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ gpio@4 {
|
||||||
|
+ reg = <0x4 0x4>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ gpio@8 {
|
||||||
|
+ reg = <0x8 0x4>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ gpio@100 {
|
||||||
|
+ reg = <0x100 0x4>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ pmx: pinmux@1e000 {
|
||||||
|
+ compatible = "pinconf-single";
|
||||||
|
+ reg = <0x1e000 0x330>;
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <1>;
|
||||||
|
+ #gpio-range-cells = <3>;
|
||||||
|
+ ranges;
|
||||||
|
+
|
||||||
|
+ #pinctrl-cells = <1>;
|
||||||
|
+ pinctrl-single,register-width = <32>;
|
||||||
|
+ pinctrl-single,function-mask = <7>;
|
||||||
|
+
|
||||||
|
+ range: gpio-range {
|
||||||
|
+ #pinctrl-single,gpio-range-cells = <3>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ uart2: serial@36000 {
|
||||||
|
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
|
||||||
|
+ reg = <0x36000 0x1000>;
|
||||||
|
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&apbcp PXA1908_CLK_UART2>;
|
||||||
|
+ reg-shift = <2>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ twsi2: i2c@37000 {
|
||||||
|
+ compatible = "mrvl,mmp-twsi";
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <0>;
|
||||||
|
+ reg = <0x37000 0x64>;
|
||||||
|
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&apbcp PXA1908_CLK_TWSI2>;
|
||||||
|
+ mrvl,i2c-fast-mode;
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ apbcp: clock-controller@3b000 {
|
||||||
|
+ compatible = "marvell,pxa1908-apbcp";
|
||||||
|
+ reg = <0x3b000 0x1000>;
|
||||||
|
+ #clock-cells = <1>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ mpmu: clock-controller@50000 {
|
||||||
|
+ compatible = "marvell,pxa1908-mpmu";
|
||||||
|
+ reg = <0x50000 0x1000>;
|
||||||
|
+ #clock-cells = <1>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ axi@d4200000 {
|
||||||
|
+ compatible = "simple-bus";
|
||||||
|
+ reg = <0 0xd4200000 0 0x200000>;
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <1>;
|
||||||
|
+ ranges = <0 0 0xd4200000 0x200000>;
|
||||||
|
+
|
||||||
|
+ usbphy: phy@7000 {
|
||||||
|
+ compatible = "marvell,pxa1928-usb-phy";
|
||||||
|
+ reg = <0x7000 0x200>;
|
||||||
|
+ clocks = <&apmu PXA1908_CLK_USB>;
|
||||||
|
+ #phy-cells = <0>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ usb: usb@8000 {
|
||||||
|
+ compatible = "chipidea,usb2";
|
||||||
|
+ reg = <0x8000 0x200>;
|
||||||
|
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&apmu PXA1908_CLK_USB>;
|
||||||
|
+ phys = <&usbphy>;
|
||||||
|
+ phy-names = "usb-phy";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ sdh0: mmc@80000 {
|
||||||
|
+ compatible = "mrvl,pxav3-mmc";
|
||||||
|
+ reg = <0x80000 0x120>;
|
||||||
|
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&apmu PXA1908_CLK_SDH0>;
|
||||||
|
+ clock-names = "io";
|
||||||
|
+ mrvl,clk-delay-cycles = <31>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ sdh1: mmc@80800 {
|
||||||
|
+ compatible = "mrvl,pxav3-mmc";
|
||||||
|
+ reg = <0x80800 0x120>;
|
||||||
|
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&apmu PXA1908_CLK_SDH1>;
|
||||||
|
+ clock-names = "io";
|
||||||
|
+ mrvl,clk-delay-cycles = <31>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ sdh2: mmc@81000 {
|
||||||
|
+ compatible = "mrvl,pxav3-mmc";
|
||||||
|
+ reg = <0x81000 0x120>;
|
||||||
|
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&apmu PXA1908_CLK_SDH2>;
|
||||||
|
+ clock-names = "io";
|
||||||
|
+ mrvl,clk-delay-cycles = <31>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ apmu: clock-controller@82800 {
|
||||||
|
+ compatible = "marvell,pxa1908-apmu";
|
||||||
|
+ reg = <0x82800 0x400>;
|
||||||
|
+ #clock-cells = <1>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+};
|
||||||
|
--
|
||||||
|
2.41.0
|
||||||
|
|
||||||
|
|
@ -0,0 +1,38 @@
|
||||||
|
From a9420a20d18c43f90c256e0b95c7c72ee2b4248d Mon Sep 17 00:00:00 2001
|
||||||
|
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
|
||||||
|
Date: Fri, 21 Jul 2023 22:37:52 +0200
|
||||||
|
Subject: [PATCH] MAINTAINERS: add myself as Marvell PXA1908 maintainer
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
Add myself as the maintainer for Marvell PXA1908 SoC support.
|
||||||
|
|
||||||
|
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
|
||||||
|
---
|
||||||
|
MAINTAINERS | 9 +++++++++
|
||||||
|
1 file changed, 9 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/MAINTAINERS b/MAINTAINERS
|
||||||
|
index 53b7ca804465..79173056e5cc 100644
|
||||||
|
--- a/MAINTAINERS
|
||||||
|
+++ b/MAINTAINERS
|
||||||
|
@@ -2299,6 +2299,15 @@ F: drivers/irqchip/irq-mvebu-*
|
||||||
|
F: drivers/pinctrl/mvebu/
|
||||||
|
F: drivers/rtc/rtc-armada38x.c
|
||||||
|
|
||||||
|
+ARM/Marvell PXA1908 SOC support
|
||||||
|
+M: Duje Mihanović <duje.mihanovic@skole.hr>
|
||||||
|
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||||
|
+S: Maintained
|
||||||
|
+T: git https://gitlab.com/LegoLivesMatter/linux
|
||||||
|
+F: arch/arm64/boot/dts/marvell/pxa1908*
|
||||||
|
+F: drivers/clk/mmp/clk-of-pxa1908.c
|
||||||
|
+F: include/dt-bindings/clock/marvell,pxa1908.h
|
||||||
|
+
|
||||||
|
ARM/Mediatek RTC DRIVER
|
||||||
|
M: Eddie Huang <eddie.huang@mediatek.com>
|
||||||
|
M: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
--
|
||||||
|
2.41.0
|
||||||
|
|
||||||
|
|
@ -0,0 +1,26 @@
|
||||||
|
From dd4943d63aa266bf25d5b57b5a11d629336efa93 Mon Sep 17 00:00:00 2001
|
||||||
|
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
|
||||||
|
Date: Wed, 26 Jul 2023 21:14:34 +0200
|
||||||
|
Subject: [PATCH] DONOTMERGE: Add pxa,rev-id to board dts
|
||||||
|
|
||||||
|
This won't be accepted upstream, but it's needed to boot with just
|
||||||
|
S-Boot, so add this here.
|
||||||
|
---
|
||||||
|
arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts | 1 +
|
||||||
|
1 file changed, 1 insertion(+)
|
||||||
|
|
||||||
|
diff --git a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
|
||||||
|
index 59e5d6f15dd2..4dc07fa8ae70 100644
|
||||||
|
--- a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
|
||||||
|
@@ -4,6 +4,7 @@
|
||||||
|
#include <dt-bindings/input/linux-event-codes.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
+ pxa,rev-id = <3928 2>;
|
||||||
|
model = "Samsung Galaxy Core Prime VE LTE";
|
||||||
|
compatible = "samsung,coreprimevelte", "marvell,pxa1908";
|
||||||
|
|
||||||
|
--
|
||||||
|
2.41.0
|
||||||
|
|
||||||
|
|
@ -0,0 +1,49 @@
|
||||||
|
From 171f19c6d38ba40dc49971ac0036eb7de2b40d33 Mon Sep 17 00:00:00 2001
|
||||||
|
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
|
||||||
|
Date: Sun, 4 Sep 2022 17:20:43 +0200
|
||||||
|
Subject: [PATCH] DONOTMERGE: Enable AArch64 system timer properly
|
||||||
|
|
||||||
|
With this, an initramfs can be reached.
|
||||||
|
|
||||||
|
Long-term, this will be moved someplace such as U-Boot.
|
||||||
|
---
|
||||||
|
drivers/clk/mmp/clk-of-pxa1908.c | 16 ++++++++++++++++
|
||||||
|
1 file changed, 16 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/drivers/clk/mmp/clk-of-pxa1908.c b/drivers/clk/mmp/clk-of-pxa1908.c
|
||||||
|
index 520440cb082c..b75facde3f3f 100644
|
||||||
|
--- a/drivers/clk/mmp/clk-of-pxa1908.c
|
||||||
|
+++ b/drivers/clk/mmp/clk-of-pxa1908.c
|
||||||
|
@@ -12,6 +12,7 @@
|
||||||
|
|
||||||
|
#define APMU_CLK_GATE_CTRL 0x40
|
||||||
|
#define MPMU_UART_PLL 0x14
|
||||||
|
+#define APBC_COUNTER_CLK_SEL 0x64
|
||||||
|
|
||||||
|
#define APBC_UART0 0x0
|
||||||
|
#define APBC_UART1 0x4
|
||||||
|
@@ -256,6 +257,21 @@ static void __init pxa1908_apbc_clk_init(struct device_node *np)
|
||||||
|
mmp_clk_init(np, &pxa_unit->unit, PXA1908_APBC_NR_CLKS);
|
||||||
|
|
||||||
|
pxa1908_apb_periph_clk_init(pxa_unit);
|
||||||
|
+
|
||||||
|
+ /* Assign a 26MHz clock to the ARM architected timer. */
|
||||||
|
+ int tmp = readl(pxa_unit->apbc_base + APBC_COUNTER_CLK_SEL);
|
||||||
|
+ if ((tmp >> 16) == 0x319) {
|
||||||
|
+ writel(tmp | 1, pxa_unit->apbc_base + APBC_COUNTER_CLK_SEL);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ /* Enable the ARM architected timer. */
|
||||||
|
+ void __iomem *cnt_base = ioremap(0xd4101000, 0x1000);
|
||||||
|
+ if (!cnt_base)
|
||||||
|
+ pr_err("failed to map cnt register\n");
|
||||||
|
+ else {
|
||||||
|
+ writel(BIT(0) | BIT(1), cnt_base);
|
||||||
|
+ iounmap(cnt_base);
|
||||||
|
+ }
|
||||||
|
}
|
||||||
|
CLK_OF_DECLARE(pxa1908_apbc, "marvell,pxa1908-apbc", pxa1908_apbc_clk_init);
|
||||||
|
|
||||||
|
--
|
||||||
|
2.41.0
|
||||||
|
|
||||||
|
|
@ -0,0 +1,80 @@
|
||||||
|
# Maintainer: Duje Mihanović <duje.mihanovic@skole.hr>
|
||||||
|
|
||||||
|
_flavor=samsung-coreprimevelte-mainline
|
||||||
|
pkgname=linux-$_flavor
|
||||||
|
pkgver=6.5_rc4
|
||||||
|
pkgrel=0
|
||||||
|
pkgdesc="Samsung Galaxy Core Prime VE LTE mainline kernel"
|
||||||
|
arch="aarch64"
|
||||||
|
_carch="arm64"
|
||||||
|
url="https://github.com/torvalds/linux"
|
||||||
|
license="GPL-2.0-only"
|
||||||
|
options="!strip !check !tracedeps pmb:cross-native pmb:kconfigcheck-nftables
|
||||||
|
pmb:kconfigcheck-zram"
|
||||||
|
makedepends="bash bc bison devicepkg-dev findutils flex gmp-dev mpc1-dev
|
||||||
|
mpfr-dev openssl-dev perl postmarketos-installkernel pxa-mkbootimg dtc"
|
||||||
|
|
||||||
|
# Source
|
||||||
|
_tag="${pkgver//_/-}"
|
||||||
|
_config="config-$_flavor.$arch"
|
||||||
|
source="
|
||||||
|
linux-$_tag.tar.gz::$url/archive/refs/tags/v$_tag.tar.gz
|
||||||
|
$_config
|
||||||
|
0001-tty-serial-8250-Define-earlycon-for-mrvl-mmp-uart.patch
|
||||||
|
0002-gpio-pxa-disable-pinctrl-calls-for-MMP_GPIO.patch
|
||||||
|
0003-clk-mmp-Switch-to-use-struct-u32_fract-instead-of-cu.patch
|
||||||
|
0004-dt-bindings-clock-Add-Marvell-PXA1908-clock-bindings.patch
|
||||||
|
0005-clk-mmp-Add-Marvell-PXA1908-clock-driver.patch
|
||||||
|
0006-dt-bindings-marvell-Document-PXA1908-SoC.patch
|
||||||
|
0007-arm64-Kconfig.platforms-Add-config-for-Marvell-PXA19.patch
|
||||||
|
0008-arm64-dts-Add-DTS-for-Marvell-PXA1908-and-samsung-co.patch
|
||||||
|
0009-MAINTAINERS-add-myself-as-Marvell-PXA1908-maintainer.patch
|
||||||
|
0010-DONOTMERGE-Add-pxa-rev-id-to-board-dts.patch
|
||||||
|
0011-DONOTMERGE-Enable-AArch64-system-timer-properly.patch
|
||||||
|
"
|
||||||
|
|
||||||
|
builddir="$srcdir/linux-$_tag"
|
||||||
|
|
||||||
|
prepare() {
|
||||||
|
default_prepare
|
||||||
|
cp "$srcdir/config-$_flavor.$arch" "$builddir"/.config
|
||||||
|
}
|
||||||
|
|
||||||
|
build() {
|
||||||
|
unset LDFLAGS
|
||||||
|
make ARCH="$_carch" CC="${CC:-gcc}" \
|
||||||
|
KBUILD_BUILD_VERSION="$((pkgrel + 1 ))-postmarketOS"
|
||||||
|
}
|
||||||
|
|
||||||
|
package() {
|
||||||
|
mkdir -p "$pkgdir"/boot
|
||||||
|
make zinstall modules_install dtbs_install \
|
||||||
|
ARCH="$_carch" \
|
||||||
|
INSTALL_MOD_STRIP=1 \
|
||||||
|
INSTALL_PATH="$pkgdir"/boot \
|
||||||
|
INSTALL_MOD_PATH="$pkgdir" \
|
||||||
|
INSTALL_DTBS_PATH="$pkgdir/usr/share/dtb"
|
||||||
|
|
||||||
|
install -D include/config/kernel.release \
|
||||||
|
"$pkgdir/usr/share/kernel/$_flavor/kernel.release"
|
||||||
|
|
||||||
|
# Master DTB (deviceinfo_bootimg_qcdt)
|
||||||
|
pxa1908-dtbTool -p scripts/dtc/ -o arch/$_carch/boot/dt.img arch/$_carch/boot/dts/marvell/
|
||||||
|
install -Dm644 arch/$_carch/boot/dt.img "$pkgdir"/boot/dt.img
|
||||||
|
}
|
||||||
|
|
||||||
|
sha512sums="
|
||||||
|
f30138f99c65bb4d96ed3b59e0fc741a1364601632c6dbec9ffec999d20f41b8eaa8d2636eee440ea8c61fe12d5971bbb3a1d0e540165b974c4e3f03d11f829e linux-6.5-rc4.tar.gz
|
||||||
|
67bef68d9f89c6b713e75785899d889013cf07ba648a10db1a4b613070ac0ea293520d215158e0c1dd4a27695d6072e62943ad105bc7782f853c032533b258c2 config-samsung-coreprimevelte-mainline.aarch64
|
||||||
|
0b091733e12dd68d5286751e1cc8673211adb679f05b97f276956badc199b287c0325fad9ada455e7e00bbfcd1ce1a854e669fbe2644f33de1997bfb8d2a2ce1 0001-tty-serial-8250-Define-earlycon-for-mrvl-mmp-uart.patch
|
||||||
|
e4b1519678367799022b0543449dbd2f6ebed0c6cd23cf246b27242d77201a9a728e9feb48cb35874522918236d8e6809b22ae2cb269722deea72302c6ad0b9a 0002-gpio-pxa-disable-pinctrl-calls-for-MMP_GPIO.patch
|
||||||
|
6a71af9fdfd9cdded2ef798ec1b54149acc0152014d708ea3e59b9254aeff7f9bcec4c8dcefe36f3299dcf65867bf50ac8487ccf1d4fbb6522da61406a971baa 0003-clk-mmp-Switch-to-use-struct-u32_fract-instead-of-cu.patch
|
||||||
|
8b41a273f21c2c7dfdaaebeac60d0b95ff3e3ac152d30254250cf479a8b0483ae974737e33e1e8c60a16aa0da9fb8fec450383f010dbd67b7416e1f761d97dbd 0004-dt-bindings-clock-Add-Marvell-PXA1908-clock-bindings.patch
|
||||||
|
741b27c644128b655bc9b1bc25ae9d7a7e6e6b1e26300b597eb8a787e8e23c4584eb1cacd0528c7e5b0531b794a8eab2080d4404348dfc305c99703e55bbcdb0 0005-clk-mmp-Add-Marvell-PXA1908-clock-driver.patch
|
||||||
|
cd120ad2ee70a86c6de367b446e2e2cf4bc44ccb6c660978a72e27c55237be0e7eecb61310162c44461afbf66e378beac4e6429b9aed7b9a3c47db6180122430 0006-dt-bindings-marvell-Document-PXA1908-SoC.patch
|
||||||
|
b06e721b18490512a35d22af0c266f084835b85f29fc2b84e9e3cd4ac7e30f7bcd7454295cc51c14679f6a9cd640323be6f2544541649c795ea287858dd28a48 0007-arm64-Kconfig.platforms-Add-config-for-Marvell-PXA19.patch
|
||||||
|
00fbda0b7e26bec4664fd391b8dd57fed315cd254f28287a85e6174f14a08274204f5441bdd1a32ba8a8855dd5ad139081a4e65718387d75481759276f9bd7ec 0008-arm64-dts-Add-DTS-for-Marvell-PXA1908-and-samsung-co.patch
|
||||||
|
be476ac6ea0bf11c7415ac8849ad796c51041b96c93a744015a613e561a0dcdfb65642abeee3674639387c7276fcb8b83dda1f8c20e3461c14f198c410bb96ee 0009-MAINTAINERS-add-myself-as-Marvell-PXA1908-maintainer.patch
|
||||||
|
1ba1bb05696364f3790e68c37ba75e3b83ae7f13e11ca0f52e03036da29c6e9caed93b7cbb675ff82b2e2ec337a5c416b863abe2cba7d5ae9be68ad74c798d86 0010-DONOTMERGE-Add-pxa-rev-id-to-board-dts.patch
|
||||||
|
cab9434b485c63077b22ba65c7ca160e413bc10a60e971a76c84f1df21140a2475b406a4c4c8c7e97c0292795b2a2786035663a8632e7915d2c69031d5255197 0011-DONOTMERGE-Enable-AArch64-system-timer-properly.patch
|
||||||
|
"
|
||||||
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue