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linux-samsung-coreprimevelte-mainline: upgrade to 6.6-rc7 (MR 4517)

Browse source 
Also adds patches for WiFi and backlight.

[ci:skip-build]: already built successfully in CI
This commit is contained in:
Duje Mihanović 2023-10-29 16:54:13 +01:00 committed by Oliver Smith
parent 2770d39f10
commit 057584931e
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GPG key ID: 5AE7F5513E0885CB
23 changed files with 71 additions and 7065 deletions
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35
device/testing/linux-samsung-coreprimevelte-mainline/0001-gpio-pxa-disable-pinctrl-calls-for-MMP_GPIO.patch
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@ -1,35 +0,0 @@
From b5eaf20ed25d51d8523ce83e678ff9fab740c8be Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
Date: Fri, 21 Jul 2023 22:37:45 +0200
Subject: [PATCH] gpio: pxa: disable pinctrl calls for MMP_GPIO
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Similarly to PXA3xx and MMP2, pinctrl-single isn't capable of setting
pin direction on MMP either.
Fixes: a770d946371e ("gpio: pxa: add pin control gpio direction and request")
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
drivers/gpio/gpio-pxa.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 7e9f7a32d3ee..cae9661862fe 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -237,6 +237,7 @@ static bool pxa_gpio_has_pinctrl(void)
switch (gpio_type) {
case PXA3XX_GPIO:
case MMP2_GPIO:
+ case MMP_GPIO:
return false;
default:
--
2.42.0

299
device/testing/linux-samsung-coreprimevelte-mainline/0002-clk-mmp-Switch-to-use-struct-u32_fract-instead-of-cu.patch
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@ -1,299 +0,0 @@
From 6510dc5474cbfb92f7aedf981fa3831f43886906 Mon Sep 17 00:00:00 2001
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Date: Mon, 24 Jul 2023 12:48:38 +0300
Subject: [PATCH] clk: mmp: Switch to use struct u32_fract instead of custom
one
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The struct mmp_clk_factor_tbl repeats the generic struct u32_fract.
Kill the custom one and use the generic one instead.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Duje Mihanović <duje.mihanovic@skole.hr>
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
drivers/clk/mmp/clk-frac.c | 57 ++++++++++++++++----------------
drivers/clk/mmp/clk-of-mmp2.c | 26 +++++++--------
drivers/clk/mmp/clk-of-pxa168.c | 4 +--
drivers/clk/mmp/clk-of-pxa1928.c | 6 ++--
drivers/clk/mmp/clk-of-pxa910.c | 4 +--
drivers/clk/mmp/clk.h | 10 ++----
6 files changed, 51 insertions(+), 56 deletions(-)
diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c
index 1b90867b60c4..6556f6ada2e8 100644
--- a/drivers/clk/mmp/clk-frac.c
+++ b/drivers/clk/mmp/clk-frac.c
@@ -26,14 +26,15 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
{
struct mmp_clk_factor *factor = to_clk_factor(hw);
u64 rate = 0, prev_rate;
+ struct u32_fract *d;
int i;
for (i = 0; i < factor->ftbl_cnt; i++) {
- prev_rate = rate;
- rate = *prate;
- rate *= factor->ftbl[i].den;
- do_div(rate, factor->ftbl[i].num * factor->masks->factor);
+ d = &factor->ftbl[i];
+ prev_rate = rate;
+ rate = (u64)(*prate) * d->denominator;
+ do_div(rate, d->numerator * factor->masks->factor);
if (rate > drate)
break;
}
@@ -52,23 +53,22 @@ static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
{
struct mmp_clk_factor *factor = to_clk_factor(hw);
struct mmp_clk_factor_masks *masks = factor->masks;
- unsigned int val, num, den;
+ struct u32_fract d;
+ unsigned int val;
u64 rate;
val = readl_relaxed(factor->base);
/* calculate numerator */
- num = (val >> masks->num_shift) & masks->num_mask;
+ d.numerator = (val >> masks->num_shift) & masks->num_mask;
/* calculate denominator */
- den = (val >> masks->den_shift) & masks->den_mask;
-
- if (!den)
+ d.denominator = (val >> masks->den_shift) & masks->den_mask;
+ if (!d.denominator)
return 0;
- rate = parent_rate;
- rate *= den;
- do_div(rate, num * factor->masks->factor);
+ rate = (u64)parent_rate * d.denominator;
+ do_div(rate, d.numerator * factor->masks->factor);
return rate;
}
@@ -82,18 +82,18 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
int i;
unsigned long val;
unsigned long flags = 0;
+ struct u32_fract *d;
u64 rate = 0;
for (i = 0; i < factor->ftbl_cnt; i++) {
- rate = prate;
- rate *= factor->ftbl[i].den;
- do_div(rate, factor->ftbl[i].num * factor->masks->factor);
+ d = &factor->ftbl[i];
+ rate = (u64)prate * d->denominator;
+ do_div(rate, d->numerator * factor->masks->factor);
if (rate > drate)
break;
}
- if (i > 0)
- i--;
+ d = i ? &factor->ftbl[i - 1] : &factor->ftbl[0];
if (factor->lock)
spin_lock_irqsave(factor->lock, flags);
@@ -101,10 +101,10 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
val = readl_relaxed(factor->base);
val &= ~(masks->num_mask << masks->num_shift);
- val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift;
+ val |= (d->numerator & masks->num_mask) << masks->num_shift;
val &= ~(masks->den_mask << masks->den_shift);
- val |= (factor->ftbl[i].den & masks->den_mask) << masks->den_shift;
+ val |= (d->denominator & masks->den_mask) << masks->den_shift;
writel_relaxed(val, factor->base);
@@ -118,7 +118,8 @@ static int clk_factor_init(struct clk_hw *hw)
{
struct mmp_clk_factor *factor = to_clk_factor(hw);
struct mmp_clk_factor_masks *masks = factor->masks;
- u32 val, num, den;
+ struct u32_fract d;
+ u32 val;
int i;
unsigned long flags = 0;
@@ -128,23 +129,22 @@ static int clk_factor_init(struct clk_hw *hw)
val = readl(factor->base);
/* calculate numerator */
- num = (val >> masks->num_shift) & masks->num_mask;
+ d.numerator = (val >> masks->num_shift) & masks->num_mask;
/* calculate denominator */
- den = (val >> masks->den_shift) & masks->den_mask;
+ d.denominator = (val >> masks->den_shift) & masks->den_mask;
for (i = 0; i < factor->ftbl_cnt; i++)
- if (den == factor->ftbl[i].den && num == factor->ftbl[i].num)
+ if (d.denominator == factor->ftbl[i].denominator &&
+ d.numerator == factor->ftbl[i].numerator)
break;
if (i >= factor->ftbl_cnt) {
val &= ~(masks->num_mask << masks->num_shift);
- val |= (factor->ftbl[0].num & masks->num_mask) <<
- masks->num_shift;
+ val |= (factor->ftbl[0].numerator & masks->num_mask) << masks->num_shift;
val &= ~(masks->den_mask << masks->den_shift);
- val |= (factor->ftbl[0].den & masks->den_mask) <<
- masks->den_shift;
+ val |= (factor->ftbl[0].denominator & masks->den_mask) << masks->den_shift;
}
if (!(val & masks->enable_mask) || i >= factor->ftbl_cnt) {
@@ -168,8 +168,7 @@ static const struct clk_ops clk_factor_ops = {
struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
unsigned long flags, void __iomem *base,
struct mmp_clk_factor_masks *masks,
- struct mmp_clk_factor_tbl *ftbl,
- unsigned int ftbl_cnt, spinlock_t *lock)
+ struct u32_fract *ftbl, unsigned int ftbl_cnt, spinlock_t *lock)
{
struct mmp_clk_factor *factor;
struct clk_init_data init;
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
index eaad36ee323d..a4f15cee630e 100644
--- a/drivers/clk/mmp/clk-of-mmp2.c
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -143,9 +143,9 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
.den_shift = 0,
};
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
- {.num = 8125, .den = 1536}, /*14.745MHZ */
- {.num = 3521, .den = 689}, /*19.23MHZ */
+static struct u32_fract uart_factor_tbl[] = {
+ { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */
+ { .numerator = 3521, .denominator = 689 }, /* 19.23MHZ */
};
static struct mmp_clk_factor_masks i2s_factor_masks = {
@@ -157,16 +157,16 @@ static struct mmp_clk_factor_masks i2s_factor_masks = {
.enable_mask = 0xd0000000,
};
-static struct mmp_clk_factor_tbl i2s_factor_tbl[] = {
- {.num = 24868, .den = 511}, /* 2.0480 MHz */
- {.num = 28003, .den = 793}, /* 2.8224 MHz */
- {.num = 24941, .den = 1025}, /* 4.0960 MHz */
- {.num = 28003, .den = 1586}, /* 5.6448 MHz */
- {.num = 31158, .den = 2561}, /* 8.1920 MHz */
- {.num = 16288, .den = 1845}, /* 11.2896 MHz */
- {.num = 20772, .den = 2561}, /* 12.2880 MHz */
- {.num = 8144, .den = 1845}, /* 22.5792 MHz */
- {.num = 10386, .den = 2561}, /* 24.5760 MHz */
+static struct u32_fract i2s_factor_tbl[] = {
+ { .numerator = 24868, .denominator = 511 }, /* 2.0480 MHz */
+ { .numerator = 28003, .denominator = 793 }, /* 2.8224 MHz */
+ { .numerator = 24941, .denominator = 1025 }, /* 4.0960 MHz */
+ { .numerator = 28003, .denominator = 1586 }, /* 5.6448 MHz */
+ { .numerator = 31158, .denominator = 2561 }, /* 8.1920 MHz */
+ { .numerator = 16288, .denominator = 1845 }, /* 11.2896 MHz */
+ { .numerator = 20772, .denominator = 2561 }, /* 12.2880 MHz */
+ { .numerator = 8144, .denominator = 1845 }, /* 22.5792 MHz */
+ { .numerator = 10386, .denominator = 2561 }, /* 24.5760 MHz */
};
static DEFINE_SPINLOCK(acgr_lock);
diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c
index fb0df64cf053..ab5f83e77305 100644
--- a/drivers/clk/mmp/clk-of-pxa168.c
+++ b/drivers/clk/mmp/clk-of-pxa168.c
@@ -106,8 +106,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
.den_shift = 0,
};
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
- {.num = 8125, .den = 1536}, /*14.745MHZ */
+static struct u32_fract uart_factor_tbl[] = {
+ { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */
};
static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit)
diff --git a/drivers/clk/mmp/clk-of-pxa1928.c b/drivers/clk/mmp/clk-of-pxa1928.c
index 9def4b5f10e9..ebb6e278eda3 100644
--- a/drivers/clk/mmp/clk-of-pxa1928.c
+++ b/drivers/clk/mmp/clk-of-pxa1928.c
@@ -61,9 +61,9 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
.den_shift = 0,
};
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
- {.num = 832, .den = 234}, /*58.5MHZ */
- {.num = 1, .den = 1}, /*26MHZ */
+static struct u32_fract uart_factor_tbl[] = {
+ { .numerator = 832, .denominator = 234 }, /* 58.5MHZ */
+ { .numerator = 1, .denominator = 1 }, /* 26MHZ */
};
static void pxa1928_pll_init(struct pxa1928_clk_unit *pxa_unit)
diff --git a/drivers/clk/mmp/clk-of-pxa910.c b/drivers/clk/mmp/clk-of-pxa910.c
index 7a38c424782e..fe65e7bdb411 100644
--- a/drivers/clk/mmp/clk-of-pxa910.c
+++ b/drivers/clk/mmp/clk-of-pxa910.c
@@ -86,8 +86,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
.den_shift = 0,
};
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
- {.num = 8125, .den = 1536}, /*14.745MHZ */
+static struct u32_fract uart_factor_tbl[] = {
+ { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */
};
static void pxa910_pll_init(struct pxa910_clk_unit *pxa_unit)
diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
index 55ac05379781..c83cec169ddc 100644
--- a/drivers/clk/mmp/clk.h
+++ b/drivers/clk/mmp/clk.h
@@ -3,6 +3,7 @@
#define __MACH_MMP_CLK_H
#include <linux/clk-provider.h>
+#include <linux/math.h>
#include <linux/pm_domain.h>
#include <linux/clkdev.h>
@@ -20,16 +21,11 @@ struct mmp_clk_factor_masks {
unsigned int enable_mask;
};
-struct mmp_clk_factor_tbl {
- unsigned int num;
- unsigned int den;
-};
-
struct mmp_clk_factor {
struct clk_hw hw;
void __iomem *base;
struct mmp_clk_factor_masks *masks;
- struct mmp_clk_factor_tbl *ftbl;
+ struct u32_fract *ftbl;
unsigned int ftbl_cnt;
spinlock_t *lock;
};
@@ -37,7 +33,7 @@ struct mmp_clk_factor {
extern struct clk *mmp_clk_register_factor(const char *name,
const char *parent_name, unsigned long flags,
void __iomem *base, struct mmp_clk_factor_masks *masks,
- struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
+ struct u32_fract *ftbl, unsigned int ftbl_cnt,
spinlock_t *lock);
/* Clock type "mix" */
--
2.42.0

171
device/testing/linux-samsung-coreprimevelte-mainline/0003-dt-bindings-clock-Add-Marvell-PXA1908-clock-bindings.patch
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@ -1,171 +0,0 @@
From 9495e512486a63d11baa2db46154cff4962f9f67 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
Date: Fri, 21 Jul 2023 22:37:47 +0200
Subject: [PATCH] dt-bindings: clock: Add Marvell PXA1908 clock bindings
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add dt bindings and documentation for the Marvell PXA1908 clock
controller.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
.../bindings/clock/marvell,pxa1908.yaml | 48 ++++++++++
include/dt-bindings/clock/marvell,pxa1908.h | 88 +++++++++++++++++++
2 files changed, 136 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
create mode 100644 include/dt-bindings/clock/marvell,pxa1908.h
diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
new file mode 100644
index 000000000000..4e78933232b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell PXA1908 Clock Controllers
+
+maintainers:
+ - Duje Mihanović <duje.mihanovic@skole.hr>
+
+description: |
+ The PXA1908 clock subsystem generates and supplies clock to various
+ controllers within the PXA1908 SoC. The PXA1908 contains numerous clock
+ controller blocks, with the ones currently supported being APBC, APBCP, MPMU
+ and APMU roughly corresponding to internal buses.
+
+ All these clock identifiers could be found in <include/dt-bindings/marvell,pxa1908.h>.
+
+properties:
+ compatible:
+ enum:
+ - marvell,pxa1908-apbc
+ - marvell,pxa1908-apbcp
+ - marvell,pxa1908-mpmu
+ - marvell,pxa1908-apmu
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ # APMU block:
+ - |
+ clock-controller@d4282800 {
+ compatible = "marvell,pxa1908-apmu";
+ reg = <0xd4282800 0x400>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindings/clock/marvell,pxa1908.h
new file mode 100644
index 000000000000..fb15b0d0cd4c
--- /dev/null
+++ b/include/dt-bindings/clock/marvell,pxa1908.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+#ifndef __DTS_MARVELL_PXA1908_CLOCK_H
+#define __DTS_MARVELL_PXA1908_CLOCK_H
+
+/* plls */
+#define PXA1908_CLK_CLK32 1
+#define PXA1908_CLK_VCTCXO 2
+#define PXA1908_CLK_PLL1_624 3
+#define PXA1908_CLK_PLL1_416 4
+#define PXA1908_CLK_PLL1_499 5
+#define PXA1908_CLK_PLL1_832 6
+#define PXA1908_CLK_PLL1_1248 7
+#define PXA1908_CLK_PLL1_D2 8
+#define PXA1908_CLK_PLL1_D4 9
+#define PXA1908_CLK_PLL1_D8 10
+#define PXA1908_CLK_PLL1_D16 11
+#define PXA1908_CLK_PLL1_D6 12
+#define PXA1908_CLK_PLL1_D12 13
+#define PXA1908_CLK_PLL1_D24 14
+#define PXA1908_CLK_PLL1_D48 15
+#define PXA1908_CLK_PLL1_D96 16
+#define PXA1908_CLK_PLL1_D13 17
+#define PXA1908_CLK_PLL1_32 18
+#define PXA1908_CLK_PLL1_208 19
+#define PXA1908_CLK_PLL1_117 20
+#define PXA1908_CLK_PLL1_416_GATE 21
+#define PXA1908_CLK_PLL1_624_GATE 22
+#define PXA1908_CLK_PLL1_832_GATE 23
+#define PXA1908_CLK_PLL1_1248_GATE 24
+#define PXA1908_CLK_PLL1_D2_GATE 25
+#define PXA1908_CLK_PLL1_499_EN 26
+#define PXA1908_CLK_PLL2VCO 27
+#define PXA1908_CLK_PLL2 28
+#define PXA1908_CLK_PLL2P 29
+#define PXA1908_CLK_PLL2VCODIV3 30
+#define PXA1908_CLK_PLL3VCO 31
+#define PXA1908_CLK_PLL3 32
+#define PXA1908_CLK_PLL3P 33
+#define PXA1908_CLK_PLL3VCODIV3 34
+#define PXA1908_CLK_PLL4VCO 35
+#define PXA1908_CLK_PLL4 36
+#define PXA1908_CLK_PLL4P 37
+#define PXA1908_CLK_PLL4VCODIV3 38
+
+/* apb (apbc) peripherals */
+#define PXA1908_CLK_UART0 1
+#define PXA1908_CLK_UART1 2
+#define PXA1908_CLK_GPIO 3
+#define PXA1908_CLK_PWM0 4
+#define PXA1908_CLK_PWM1 5
+#define PXA1908_CLK_PWM2 6
+#define PXA1908_CLK_PWM3 7
+#define PXA1908_CLK_SSP0 8
+#define PXA1908_CLK_SSP1 9
+#define PXA1908_CLK_IPC_RST 10
+#define PXA1908_CLK_RTC 11
+#define PXA1908_CLK_TWSI0 12
+#define PXA1908_CLK_KPC 13
+#define PXA1908_CLK_SWJTAG 14
+#define PXA1908_CLK_SSP2 15
+#define PXA1908_CLK_TWSI1 16
+#define PXA1908_CLK_THERMAL 17
+#define PXA1908_CLK_TWSI3 18
+
+/* apb (apbcp) peripherals */
+#define PXA1908_CLK_UART2 1
+#define PXA1908_CLK_TWSI2 2
+#define PXA1908_CLK_AICER 3
+
+/* axi (apmu) peripherals */
+#define PXA1908_CLK_CCIC1 1
+#define PXA1908_CLK_ISP 2
+#define PXA1908_CLK_DSI1 3
+#define PXA1908_CLK_DISP1 4
+#define PXA1908_CLK_CCIC0 5
+#define PXA1908_CLK_SDH0 6
+#define PXA1908_CLK_SDH1 7
+#define PXA1908_CLK_USB 8
+#define PXA1908_CLK_NF 9
+#define PXA1908_CLK_CORE_DEBUG 10
+#define PXA1908_CLK_VPU 11
+#define PXA1908_CLK_GC 12
+#define PXA1908_CLK_SDH2 13
+#define PXA1908_CLK_GC2D 14
+#define PXA1908_CLK_TRACE 15
+#define PXA1908_CLK_DVC_DFC_DEBUG 16
+
+#endif
--
2.42.0

366
device/testing/linux-samsung-coreprimevelte-mainline/0004-clk-mmp-Add-Marvell-PXA1908-clock-driver.patch
View file

@ -1,366 +0,0 @@
From 1117ce7ed0c45226667e5df8a74865b610e22856 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
Date: Fri, 21 Jul 2023 22:37:46 +0200
Subject: [PATCH] clk: mmp: Add Marvell PXA1908 clock driver
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add driver for Marvell PXA1908 clock controller blocks. The SoC has
numerous clock controller blocks, currently supporting APBC, APBCP, MPMU
and APMU.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
drivers/clk/mmp/Makefile | 2 +-
drivers/clk/mmp/clk-of-pxa1908.c | 328 +++++++++++++++++++++++++++++++
2 files changed, 329 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mmp/clk-of-pxa1908.c
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index 441bf83080a1..69f9c3afde83 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -11,4 +11,4 @@ obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o clk-pll.o pwr-island.o
obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) += clk-audio.o
-obj-y += clk-of-pxa1928.o
+obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o clk-of-pxa1908.o
diff --git a/drivers/clk/mmp/clk-of-pxa1908.c b/drivers/clk/mmp/clk-of-pxa1908.c
new file mode 100644
index 000000000000..753dd031b147
--- /dev/null
+++ b/drivers/clk/mmp/clk-of-pxa1908.c
@@ -0,0 +1,328 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <linux/bits.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/units.h>
+
+#include <dt-bindings/clock/marvell,pxa1908.h>
+
+#include "clk.h"
+
+#define APMU_CLK_GATE_CTRL 0x40
+#define MPMU_UART_PLL 0x14
+
+#define APBC_UART0 0x0
+#define APBC_UART1 0x4
+#define APBC_GPIO 0x8
+#define APBC_PWM0 0xc
+#define APBC_PWM1 0x10
+#define APBC_PWM2 0x14
+#define APBC_PWM3 0x18
+#define APBC_SSP0 0x1c
+#define APBC_SSP1 0x20
+#define APBC_IPC_RST 0x24
+#define APBC_RTC 0x28
+#define APBC_TWSI0 0x2c
+#define APBC_KPC 0x30
+#define APBC_SWJTAG 0x40
+#define APBC_SSP2 0x4c
+#define APBC_TWSI1 0x60
+#define APBC_THERMAL 0x6c
+#define APBC_TWSI3 0x70
+
+#define APBCP_UART2 0x1c
+#define APBCP_TWSI2 0x28
+#define APBCP_AICER 0x38
+
+#define APMU_CCIC1 0x24
+#define APMU_ISP 0x38
+#define APMU_DSI1 0x44
+#define APMU_DISP1 0x4c
+#define APMU_CCIC0 0x50
+#define APMU_SDH0 0x54
+#define APMU_SDH1 0x58
+#define APMU_USB 0x5c
+#define APMU_NF 0x60
+#define APMU_VPU 0xa4
+#define APMU_GC 0xcc
+#define APMU_SDH2 0xe0
+#define APMU_GC2D 0xf4
+#define APMU_TRACE 0x108
+#define APMU_DVC_DFC_DEBUG 0x140
+
+#define MPMU_NR_CLKS 39
+#define APBC_NR_CLKS 19
+#define APBCP_NR_CLKS 4
+#define APMU_NR_CLKS 17
+
+struct pxa1908_clk_unit {
+ struct mmp_clk_unit unit;
+ void __iomem *mpmu_base;
+ void __iomem *apmu_base;
+ void __iomem *apbc_base;
+ void __iomem *apbcp_base;
+ void __iomem *apbs_base;
+ void __iomem *ciu_base;
+};
+
+static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
+ {PXA1908_CLK_CLK32, "clk32", NULL, 0, 32768},
+ {PXA1908_CLK_VCTCXO, "vctcxo", NULL, 0, 26 * HZ_PER_MHZ},
+ {PXA1908_CLK_PLL1_624, "pll1_624", NULL, 0, 624 * HZ_PER_MHZ},
+ {PXA1908_CLK_PLL1_416, "pll1_416", NULL, 0, 416 * HZ_PER_MHZ},
+ {PXA1908_CLK_PLL1_499, "pll1_499", NULL, 0, 499 * HZ_PER_MHZ},
+ {PXA1908_CLK_PLL1_832, "pll1_832", NULL, 0, 832 * HZ_PER_MHZ},
+ {PXA1908_CLK_PLL1_1248, "pll1_1248", NULL, 0, 1248 * HZ_PER_MHZ},
+};
+
+static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
+ {PXA1908_CLK_PLL1_D2, "pll1_d2", "pll1_624", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D4, "pll1_d4", "pll1_d2", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D6, "pll1_d6", "pll1_d2", 1, 3, 0},
+ {PXA1908_CLK_PLL1_D8, "pll1_d8", "pll1_d4", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D12, "pll1_d12", "pll1_d6", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D13, "pll1_d13", "pll1_624", 1, 13, 0},
+ {PXA1908_CLK_PLL1_D16, "pll1_d16", "pll1_d8", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D24, "pll1_d24", "pll1_d12", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D48, "pll1_d48", "pll1_d24", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D96, "pll1_d96", "pll1_d48", 1, 2, 0},
+ {PXA1908_CLK_PLL1_32, "pll1_32", "pll1_d13", 2, 3, 0},
+ {PXA1908_CLK_PLL1_208, "pll1_208", "pll1_d2", 2, 3, 0},
+ {PXA1908_CLK_PLL1_117, "pll1_117", "pll1_624", 3, 16, 0},
+};
+
+static struct mmp_clk_factor_masks uart_factor_masks = {
+ .factor = 2,
+ .num_mask = GENMASK(12, 0),
+ .den_mask = GENMASK(12, 0),
+ .num_shift = 16,
+ .den_shift = 0,
+};
+
+static struct u32_fract uart_factor_tbl[] = {
+ {.numerator = 8125, .denominator = 1536}, /* 14.745MHz */
+};
+
+static DEFINE_SPINLOCK(pll1_lock);
+static struct mmp_param_general_gate_clk pll1_gate_clks[] = {
+ {PXA1908_CLK_PLL1_D2_GATE, "pll1_d2_gate", "pll1_d2", 0, APMU_CLK_GATE_CTRL, 29, 0, &pll1_lock},
+ {PXA1908_CLK_PLL1_416_GATE, "pll1_416_gate", "pll1_416", 0, APMU_CLK_GATE_CTRL, 27, 0, &pll1_lock},
+ {PXA1908_CLK_PLL1_624_GATE, "pll1_624_gate", "pll1_624", 0, APMU_CLK_GATE_CTRL, 26, 0, &pll1_lock},
+ {PXA1908_CLK_PLL1_832_GATE, "pll1_832_gate", "pll1_832", 0, APMU_CLK_GATE_CTRL, 30, 0, &pll1_lock},
+ {PXA1908_CLK_PLL1_1248_GATE, "pll1_1248_gate", "pll1_1248", 0, APMU_CLK_GATE_CTRL, 28, 0, &pll1_lock},
+};
+
+static void pxa1908_pll_init(struct pxa1908_clk_unit *pxa_unit)
+{
+ struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+ mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
+ ARRAY_SIZE(fixed_rate_clks));
+
+ mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
+ ARRAY_SIZE(fixed_factor_clks));
+
+ mmp_clk_register_factor("uart_pll", "pll1_d4",
+ CLK_SET_RATE_PARENT,
+ pxa_unit->mpmu_base + MPMU_UART_PLL,
+ &uart_factor_masks, uart_factor_tbl,
+ ARRAY_SIZE(uart_factor_tbl), NULL);
+
+}
+
+static DEFINE_SPINLOCK(pwm0_lock);
+static DEFINE_SPINLOCK(pwm2_lock);
+
+static DEFINE_SPINLOCK(uart0_lock);
+static DEFINE_SPINLOCK(uart1_lock);
+static DEFINE_SPINLOCK(uart2_lock);
+
+static const char * const uart_parent_names[] = {"pll1_117", "uart_pll"};
+static const char * const ssp_parent_names[] = {"pll1_d16", "pll1_d48", "pll1_d24", "pll1_d12"};
+
+static struct mmp_param_gate_clk apbc_gate_clks[] = {
+ {PXA1908_CLK_TWSI0, "twsi0_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 3, 0, 0, NULL},
+ {PXA1908_CLK_TWSI1, "twsi1_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 3, 0, 0, NULL},
+ {PXA1908_CLK_TWSI3, "twsi3_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 3, 0, 0, NULL},
+ {PXA1908_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 3, 0, 0, NULL},
+ {PXA1908_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 3, 0, MMP_CLK_GATE_NEED_DELAY, NULL},
+ {PXA1908_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0, MMP_CLK_GATE_NEED_DELAY, NULL},
+ {PXA1908_CLK_PWM0, "pwm0_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_PWM0, 0x2, 2, 0, 0, &pwm0_lock},
+ {PXA1908_CLK_PWM1, "pwm1_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_PWM1, 0x6, 2, 0, 0, NULL},
+ {PXA1908_CLK_PWM2, "pwm2_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_PWM2, 0x2, 2, 0, 0, NULL},
+ {PXA1908_CLK_PWM3, "pwm3_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_PWM3, 0x6, 2, 0, 0, NULL},
+ {PXA1908_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 3, 0, 0, &uart0_lock},
+ {PXA1908_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 3, 0, 0, &uart1_lock},
+};
+
+static struct mmp_param_mux_clk apbc_mux_clks[] = {
+ {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
+ {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
+ {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), 0, APBC_SSP0, 4, 3, 0, NULL},
+ {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), 0, APBC_SSP2, 4, 3, 0, NULL},
+};
+
+static void pxa1908_apb_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
+{
+ struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+ mmp_clk_register_gate(NULL, "pwm01_apb_share", "pll1_d48",
+ CLK_SET_RATE_PARENT,
+ pxa_unit->apbc_base + APBC_PWM0,
+ 0x5, 1, 0, 0, &pwm0_lock);
+ mmp_clk_register_gate(NULL, "pwm23_apb_share", "pll1_d48",
+ CLK_SET_RATE_PARENT,
+ pxa_unit->apbc_base + APBC_PWM2,
+ 0x5, 1, 0, 0, &pwm2_lock);
+ mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
+ ARRAY_SIZE(apbc_mux_clks));
+ mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
+ ARRAY_SIZE(apbc_gate_clks));
+}
+
+static struct mmp_param_gate_clk apbcp_gate_clks[] = {
+ {PXA1908_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock},
+ {PXA1908_CLK_TWSI2, "twsi2_clk", "pll1_32", CLK_SET_RATE_PARENT, APBCP_TWSI2, 0x7, 0x3, 0x0, 0, NULL},
+ {PXA1908_CLK_AICER, "ripc_clk", NULL, 0, APBCP_AICER, 0x7, 0x2, 0x0, 0, NULL},
+};
+
+static struct mmp_param_mux_clk apbcp_mux_clks[] = {
+ {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock},
+};
+
+static void pxa1908_apb_p_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
+{
+ struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+ mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->apbcp_base,
+ ARRAY_SIZE(apbcp_mux_clks));
+ mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->apbcp_base,
+ ARRAY_SIZE(apbcp_gate_clks));
+}
+
+static DEFINE_SPINLOCK(sdh0_lock);
+static DEFINE_SPINLOCK(sdh1_lock);
+static DEFINE_SPINLOCK(sdh2_lock);
+
+static const char * const sdh_parent_names[] = {"pll1_416", "pll1_624"};
+
+static struct mmp_clk_mix_config sdh_mix_config = {
+ .reg_info = DEFINE_MIX_REG_INFO(3, 8, 2, 6, 11),
+};
+
+static struct mmp_param_gate_clk apmu_gate_clks[] = {
+ {PXA1908_CLK_USB, "usb_clk", NULL, 0, APMU_USB, 0x9, 0x9, 0x1, 0, NULL},
+ {PXA1908_CLK_SDH0, "sdh0_clk", "sdh0_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH0, 0x12, 0x12, 0x0, 0, &sdh0_lock},
+ {PXA1908_CLK_SDH1, "sdh1_clk", "sdh1_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH1, 0x12, 0x12, 0x0, 0, &sdh1_lock},
+ {PXA1908_CLK_SDH2, "sdh2_clk", "sdh2_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH2, 0x12, 0x12, 0x0, 0, &sdh2_lock}
+};
+
+static void pxa1908_axi_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
+{
+ struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+ mmp_register_general_gate_clks(unit, pll1_gate_clks,
+ pxa_unit->apmu_base, ARRAY_SIZE(pll1_gate_clks));
+
+ sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0;
+ mmp_clk_register_mix(NULL, "sdh0_mix_clk", sdh_parent_names,
+ ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
+ &sdh_mix_config, &sdh0_lock);
+ sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH1;
+ mmp_clk_register_mix(NULL, "sdh1_mix_clk", sdh_parent_names,
+ ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
+ &sdh_mix_config, &sdh1_lock);
+ sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH2;
+ mmp_clk_register_mix(NULL, "sdh2_mix_clk", sdh_parent_names,
+ ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
+ &sdh_mix_config, &sdh2_lock);
+
+ mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
+ ARRAY_SIZE(apmu_gate_clks));
+}
+
+static void __init pxa1908_apbc_clk_init(struct device_node *np)
+{
+ struct pxa1908_clk_unit *pxa_unit;
+
+ pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+ if (!pxa_unit)
+ return;
+
+ pxa_unit->apbc_base = of_iomap(np, 0);
+ if (!pxa_unit->apbc_base) {
+ pr_err("failed to map apbc registers\n");
+ kfree(pxa_unit);
+ return;
+ }
+
+ mmp_clk_init(np, &pxa_unit->unit, APBC_NR_CLKS);
+
+ pxa1908_apb_periph_clk_init(pxa_unit);
+}
+CLK_OF_DECLARE(pxa1908_apbc, "marvell,pxa1908-apbc", pxa1908_apbc_clk_init);
+
+static void __init pxa1908_apbcp_clk_init(struct device_node *np)
+{
+ struct pxa1908_clk_unit *pxa_unit;
+
+ pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+ if (!pxa_unit)
+ return;
+
+ pxa_unit->apbcp_base = of_iomap(np, 0);
+ if (!pxa_unit->apbcp_base) {
+ pr_err("failed to map apbcp registers\n");
+ kfree(pxa_unit);
+ return;
+ }
+
+ mmp_clk_init(np, &pxa_unit->unit, APBCP_NR_CLKS);
+
+ pxa1908_apb_p_periph_clk_init(pxa_unit);
+}
+CLK_OF_DECLARE(pxa1908_apbcp, "marvell,pxa1908-apbcp", pxa1908_apbcp_clk_init);
+
+static void __init pxa1908_mpmu_clk_init(struct device_node *np)
+{
+ struct pxa1908_clk_unit *pxa_unit;
+
+ pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+ if (!pxa_unit)
+ return;
+
+ pxa_unit->mpmu_base = of_iomap(np, 0);
+ if (!pxa_unit->mpmu_base) {
+ pr_err("failed to map mpmu registers\n");
+ kfree(pxa_unit);
+ return;
+ }
+
+ mmp_clk_init(np, &pxa_unit->unit, MPMU_NR_CLKS);
+
+ pxa1908_pll_init(pxa_unit);
+}
+CLK_OF_DECLARE(pxa1908_mpmu, "marvell,pxa1908-mpmu", pxa1908_mpmu_clk_init);
+
+static void __init pxa1908_apmu_clk_init(struct device_node *np)
+{
+ struct pxa1908_clk_unit *pxa_unit;
+
+ pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+ if (!pxa_unit)
+ return;
+
+ pxa_unit->apmu_base = of_iomap(np, 0);
+ if (!pxa_unit->apmu_base) {
+ pr_err("failed to map apmu registers\n");
+ kfree(pxa_unit);
+ return;
+ }
+
+ mmp_clk_init(np, &pxa_unit->unit, APMU_NR_CLKS);
+
+ pxa1908_axi_periph_clk_init(pxa_unit);
+}
+CLK_OF_DECLARE(pxa1908_apmu, "marvell,pxa1908-apmu", pxa1908_apmu_clk_init);
--
2.42.0

35
device/testing/linux-samsung-coreprimevelte-mainline/0005-dt-bindings-marvell-Document-PXA1908-SoC.patch
View file

@ -1,35 +0,0 @@
From 7f084b50032c0fb5f2c6b1fdadffd1d05a27d298 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
Date: Fri, 21 Jul 2023 22:37:51 +0200
Subject: [PATCH] dt-bindings: marvell: Document PXA1908 SoC
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add dt binding for the Marvell PXA1908 SoC.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
index 4c43eaf3632e..f73bb8ec3a1a 100644
--- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
+++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
@@ -35,6 +35,11 @@ properties:
- enum:
- dell,wyse-ariel
- const: marvell,mmp3
+ - description: PXA1908 based boards
+ items:
+ - enum:
+ - samsung,coreprimevelte
+ - const: marvell,pxa1908
additionalProperties: true
--
2.42.0

41
device/testing/linux-samsung-coreprimevelte-mainline/0006-arm64-Kconfig.platforms-Add-config-for-Marvell-PXA19.patch
View file

@ -1,41 +0,0 @@
From e3fa451f2abf3ed646ebe0676c86d9c4d54af37a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
Date: Fri, 21 Jul 2023 22:37:49 +0200
Subject: [PATCH] arm64: Kconfig.platforms: Add config for Marvell PXA1908
platform
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add ARCH_MMP configuration option for Marvell PXA1908 SoC.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
arch/arm64/Kconfig.platforms | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 6069120199bb..b417cae42c84 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -89,6 +89,17 @@ config ARCH_BERLIN
help
This enables support for Marvell Berlin SoC Family
+config ARCH_MMP
+ bool "Marvell MMP SoC Family"
+ select ARM_GIC
+ select ARM_ARCH_TIMER
+ select ARM_SMMU
+ select MMP_PDMA
+ select PINCTRL_SINGLE
+ help
+ This enables support for Marvell MMP SoC family, currently
+ supporting PXA1908 aka IAP140.
+
config ARCH_BITMAIN
bool "Bitmain SoC Platforms"
help
--
2.42.0

675
device/testing/linux-samsung-coreprimevelte-mainline/0007-arm64-dts-Add-DTS-for-Marvell-PXA1908-and-samsung-co.patch
View file

@ -1,675 +0,0 @@
From ba77704a60653c40ccdbe59511cbfb6dfa8f9465 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
Date: Fri, 21 Jul 2023 22:37:50 +0200
Subject: [PATCH] arm64: dts: Add DTS for Marvell PXA1908 and
samsung,coreprimevelte
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add DTS for Marvell PXA1908 SoC and Samsung Galaxy Core Prime Value
Edition LTE, a smartphone based on said SoC.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
arch/arm64/boot/dts/marvell/Makefile | 3 +
.../pxa1908-samsung-coreprimevelte.dts | 333 ++++++++++++++++++
arch/arm64/boot/dts/marvell/pxa1908.dtsi | 295 ++++++++++++++++
3 files changed, 631 insertions(+)
create mode 100644 arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
create mode 100644 arch/arm64/boot/dts/marvell/pxa1908.dtsi
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index 79ac09b58a89..263be6ec7567 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -27,3 +27,6 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb
+
+# MMP SoC Family
+dtb-$(CONFIG_ARCH_MMP) += pxa1908-samsung-coreprimevelte.dtb
diff --git a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
new file mode 100644
index 000000000000..e3c863d517a8
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
@@ -0,0 +1,333 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include "pxa1908.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+
+/ {
+ model = "Samsung Galaxy Core Prime VE LTE";
+ compatible = "samsung,coreprimevelte", "marvell,pxa1908";
+
+ aliases {
+ mmc0 = &sdh2; /* eMMC */
+ mmc1 = &sdh0; /* SD card */
+ serial0 = &uart0;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ stdout-path = "serial0:115200n8";
+
+ fb0: framebuffer@17177000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x17177000 0 (480 * 800 * 4)>;
+ width = <480>;
+ height = <800>;
+ stride = <(480 * 4)>;
+ format = "a8r8g8b8";
+ };
+ };
+
+ /* Bootloader fills this in */
+ memory {
+ device_type = "memory";
+ reg = <0 0 0 0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer@17000000 {
+ reg = <0 0x17000000 0 0x1800000>;
+ no-map;
+ };
+
+ gpu@9000000 {
+ reg = <0 0x9000000 0 0x1000000>;
+ };
+
+ /* Communications processor, aka modem */
+ cp@3000000 {
+ reg = <0 0x3000000 0 0x5000000>;
+ };
+
+ cm3@a000000 {
+ reg = <0 0xa000000 0 0x80000>;
+ };
+
+ seclog@8000000 {
+ reg = <0 0x8000000 0 0x100000>;
+ };
+
+ ramoops@8100000 {
+ compatible = "ramoops";
+ reg = <0 0x8100000 0 0x40000>;
+ record-size = <0x8000>;
+ console-size = <0x20000>;
+ max-reason = <5>;
+ };
+ };
+
+
+ i2c-muic {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio 30 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio 29 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <3>;
+ i2c-gpio,timeout-ms = <100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_muic_pins>;
+
+ muic: extcon@14 {
+ compatible = "siliconmitus,sm5504-muic";
+ reg = <0x14>;
+ interrupt-parent = <&gpio>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pins>;
+ autorepeat;
+
+ key-home {
+ label = "Home";
+ linux,code = <KEY_HOME>;
+ gpios = <&gpio 50 GPIO_ACTIVE_LOW>;
+ };
+
+ key-volup {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+ };
+
+ key-voldown {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&smmu {
+ status = "okay";
+};
+
+&pmx {
+ pinctrl-single,gpio-range = <&range 55 55 0>,
+ <&range 110 32 0>,
+ <&range 52 1 0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&board_pins_1 &board_pins_2 &board_pins_3>;
+
+ board_pins_1: pinmux-board-1 {
+ pinctrl-single,pins = <
+ 0x160 0
+ 0x164 0
+ 0x168 0
+ 0x16c 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0x8000 0x8000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0x8000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0x288 0x388>;
+ };
+
+ board_pins_2: pinmux-board-2 {
+ pinctrl-single,pins = <
+ 0x44 1
+ 0x48 1
+ 0x20 1
+ 0x18 1
+ 0x14 1
+ 0x10 1
+ 0xc 1
+ 0x8 1
+ 0x68 1
+ 0x58 0
+ 0x54 0
+ 0x7c 0
+ 0x6c 0
+ 0x70 0
+ 0x4c 1
+ 0x50 1
+ 0xac 0
+ 0x90 0
+ 0x8c 0
+ 0x88 0
+ 0x84 0
+ 0xc8 0
+ 0x128 0
+ 0x190 0
+ 0x194 0
+ 0x1a0 0
+ 0x114 0
+ 0x118 0
+ 0x1d8 0
+ 0x1e4 0
+ 0xe8 0
+ 0x100 0
+ 0x204 0
+ 0x210 0
+ 0x218 0
+ >;
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xc000>;
+ pinctrl-single,low-power-mode = <0x288 0x388>;
+ };
+
+ board_pins_3: pinmux-board-3 {
+ pinctrl-single,pins = <
+ 0x260 0
+ 0x264 0
+ 0x268 0
+ 0x26c 0
+ 0x270 0
+ 0x274 0
+ 0x78 0
+ 0x74 0
+ 0xb0 1
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ uart0_pins: pinmux-uart0 {
+ pinctrl-single,pins = <
+ 0x198 6
+ 0x19c 6
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ gpio_keys_pins: pinmux-gpio-keys {
+ pinctrl-single,pins = <
+ 0x11c 0
+ 0x120 0
+ 0x1a4 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0xa0000 0x8000 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ i2c_muic_pins: pinmux-i2c-muic {
+ pinctrl-single,pins = <
+ 0x154 0
+ 0x150 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0x288 0x388>;
+ };
+
+ sdh0_pins_1: pinmux-sdh0-1 {
+ pinctrl-single,pins = <
+ 0x108 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ sdh0_pins_2: pinmux-sdh0-2 {
+ pinctrl-single,pins = <
+ 0x94 0
+ 0x98 0
+ 0x9c 0
+ 0xa0 0
+ 0xa4 0
+ >;
+ pinctrl-single,drive-strength = <0x800 0x1800>;
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ sdh0_pins_3: pinmux-sdh0-3 {
+ pinctrl-single,pins = <
+ 0xa8 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0x208 0x388>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+};
+
+&twsi0 {
+ status = "okay";
+};
+
+&twsi1 {
+ status = "okay";
+};
+
+&twsi2 {
+ status = "okay";
+};
+
+&twsi3 {
+ status = "okay";
+};
+
+&usb {
+ extcon = <&muic>, <&muic>;
+};
+
+&sdh2 {
+ /* Disabled for now because initialization fails with -ETIMEDOUT. */
+ status = "disabled";
+ bus-width = <8>;
+ non-removable;
+ broken-cd;
+ mmc-ddr-1_8v;
+};
+
+&sdh0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdh0_pins_1 &sdh0_pins_2 &sdh0_pins_3>;
+ cd-gpios = <&gpio 11 0>;
+ cd-inverted;
+ bus-width = <4>;
+ wp-inverted;
+};
diff --git a/arch/arm64/boot/dts/marvell/pxa1908.dtsi b/arch/arm64/boot/dts/marvell/pxa1908.dtsi
new file mode 100644
index 000000000000..cc322b9a0e9e
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/pxa1908.dtsi
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/marvell,pxa1908.h>
+
+/ {
+ model = "Marvell Armada PXA1908";
+ compatible = "marvell,pxa1908";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0 0>;
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0 1>;
+ enable-method = "psci";
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0 2>;
+ enable-method = "psci";
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0 3>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ smmu: iommu@c0010000 {
+ compatible = "arm,mmu-400";
+ reg = <0 0xc0010000 0 0x10000>;
+ #global-interrupts = <1>;
+ #iommu-cells = <1>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@d1df9000 {
+ compatible = "arm,gic-400";
+ reg = <0 0xd1df9000 0 0x1000>,
+ <0 0xd1dfa000 0 0x2000>,
+ /* The subsequent registers are guesses. */
+ <0 0xd1dfc000 0 0x2000>,
+ <0 0xd1dfe000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ apb@d4000000 {
+ compatible = "simple-bus";
+ reg = <0 0xd4000000 0 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xd4000000 0x200000>;
+
+ pdma: dma-controller@0 {
+ compatible = "marvell,pdma-1.0";
+ reg = <0 0x10000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <30>;
+ #dma-cells = <2>;
+ };
+
+ twsi1: i2c@10800 {
+ compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10800 0x64>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_TWSI1>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ twsi0: i2c@11000 {
+ compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x11000 0x64>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_TWSI0>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ twsi3: i2c@13800 {
+ compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x13800 0x64>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_TWSI3>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ apbc: clock-controller@15000 {
+ compatible = "marvell,pxa1908-apbc";
+ reg = <0x15000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@17000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
+ reg = <0x17000 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_UART0>;
+ reg-shift = <2>;
+ };
+
+ uart1: serial@18000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
+ reg = <0x18000 0x1000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_UART1>;
+ reg-shift = <2>;
+ };
+
+ gpio: gpio@19000 {
+ compatible = "marvell,mmp-gpio";
+ reg = <0x19000 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&apbc PXA1908_CLK_GPIO>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpio_mux";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ranges = <0 0x19000 0x800>;
+
+ gpio@0 {
+ reg = <0x0 0x4>;
+ };
+
+ gpio@4 {
+ reg = <0x4 0x4>;
+ };
+
+ gpio@8 {
+ reg = <0x8 0x4>;
+ };
+
+ gpio@100 {
+ reg = <0x100 0x4>;
+ };
+ };
+
+ pmx: pinmux@1e000 {
+ compatible = "pinconf-single";
+ reg = <0x1e000 0x330>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #gpio-range-cells = <3>;
+ ranges;
+
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <7>;
+
+ range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+ };
+
+ uart2: serial@36000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
+ reg = <0x36000 0x1000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbcp PXA1908_CLK_UART2>;
+ reg-shift = <2>;
+ };
+
+ twsi2: i2c@37000 {
+ compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x37000 0x64>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbcp PXA1908_CLK_TWSI2>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ apbcp: clock-controller@3b000 {
+ compatible = "marvell,pxa1908-apbcp";
+ reg = <0x3b000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mpmu: clock-controller@50000 {
+ compatible = "marvell,pxa1908-mpmu";
+ reg = <0x50000 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+
+ axi@d4200000 {
+ compatible = "simple-bus";
+ reg = <0 0xd4200000 0 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xd4200000 0x200000>;
+
+ usbphy: phy@7000 {
+ compatible = "marvell,pxa1928-usb-phy";
+ reg = <0x7000 0x200>;
+ clocks = <&apmu PXA1908_CLK_USB>;
+ #phy-cells = <0>;
+ };
+
+ usb: usb@8000 {
+ compatible = "chipidea,usb2";
+ reg = <0x8000 0x200>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apmu PXA1908_CLK_USB>;
+ phys = <&usbphy>;
+ phy-names = "usb-phy";
+ };
+
+ sdh0: mmc@80000 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0x80000 0x120>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apmu PXA1908_CLK_SDH0>;
+ clock-names = "io";
+ mrvl,clk-delay-cycles = <31>;
+ };
+
+ sdh1: mmc@80800 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0x80800 0x120>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apmu PXA1908_CLK_SDH1>;
+ clock-names = "io";
+ mrvl,clk-delay-cycles = <31>;
+ };
+
+ sdh2: mmc@81000 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0x81000 0x120>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apmu PXA1908_CLK_SDH2>;
+ clock-names = "io";
+ mrvl,clk-delay-cycles = <31>;
+ };
+
+ apmu: clock-controller@82800 {
+ compatible = "marvell,pxa1908-apmu";
+ reg = <0x82800 0x400>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+};
--
2.42.0

38
device/testing/linux-samsung-coreprimevelte-mainline/0008-MAINTAINERS-add-myself-as-Marvell-PXA1908-maintainer.patch
View file

@ -1,38 +0,0 @@
From 91114902a64ccc922cc22777576eb9e4ceaa6cd7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
Date: Fri, 21 Jul 2023 22:37:52 +0200
Subject: [PATCH] MAINTAINERS: add myself as Marvell PXA1908 maintainer
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add myself as the maintainer for Marvell PXA1908 SoC support.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b19995690904..1b0ca13c42eb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2313,6 +2313,15 @@ F: drivers/irqchip/irq-mvebu-*
F: drivers/pinctrl/mvebu/
F: drivers/rtc/rtc-armada38x.c
+ARM/Marvell PXA1908 SOC support
+M: Duje Mihanović <duje.mihanovic@skole.hr>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+T: git https://gitlab.com/LegoLivesMatter/linux
+F: arch/arm64/boot/dts/marvell/pxa1908*
+F: drivers/clk/mmp/clk-of-pxa1908.c
+F: include/dt-bindings/clock/marvell,pxa1908.h
+
ARM/Mediatek RTC DRIVER
M: Eddie Huang <eddie.huang@mediatek.com>
M: Sean Wang <sean.wang@mediatek.com>
--
2.42.0

51
device/testing/linux-samsung-coreprimevelte-mainline/0009-DONOTMERGE-Enable-AArch64-system-timer-properly.patch
View file

@ -1,51 +0,0 @@
From 8f096d8846f8ca59060d4f4427568a343e4b4a89 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
Date: Sun, 4 Sep 2022 17:20:43 +0200
Subject: [PATCH] DONOTMERGE: Enable AArch64 system timer properly
With this, an initramfs can be reached.
Long-term, this will be moved someplace such as U-Boot.
---
drivers/clk/mmp/clk-of-pxa1908.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/clk/mmp/clk-of-pxa1908.c b/drivers/clk/mmp/clk-of-pxa1908.c
index 753dd031b147..4c9580f9efa1 100644
--- a/drivers/clk/mmp/clk-of-pxa1908.c
+++ b/drivers/clk/mmp/clk-of-pxa1908.c
@@ -31,6 +31,7 @@
#define APBC_TWSI1 0x60
#define APBC_THERMAL 0x6c
#define APBC_TWSI3 0x70
+#define APBC_COUNTER_CLK_SEL 0x64
#define APBCP_UART2 0x1c
#define APBCP_TWSI2 0x28
@@ -261,6 +262,23 @@ static void __init pxa1908_apbc_clk_init(struct device_node *np)
mmp_clk_init(np, &pxa_unit->unit, APBC_NR_CLKS);
pxa1908_apb_periph_clk_init(pxa_unit);
+
+ /* Assign a 26MHz clock to the ARM architected timer. */
+ int tmp = readl(pxa_unit->apbc_base + APBC_COUNTER_CLK_SEL);
+ if ((tmp >> 16) == 0x319) {
+ writel(tmp | 1, pxa_unit->apbc_base + APBC_COUNTER_CLK_SEL);
+ }
+
+ /* Enable the ARM architected timer. */
+ void __iomem *cnt_base = ioremap(0xd4101000, 0x1000);
+ if (!cnt_base)
+ pr_err("failed to map cnt register\n");
+ else {
+ writel(BIT(0) | BIT(1), cnt_base);
+ iounmap(cnt_base);
+ }
+
+ pr_notice("apbc ready\n");
}
CLK_OF_DECLARE(pxa1908_apbc, "marvell,pxa1908-apbc", pxa1908_apbc_clk_init);
--
2.42.0

26
device/testing/linux-samsung-coreprimevelte-mainline/0010-DONOTMERGE-Add-pxa-rev-id-to-board-dts.patch
View file

@ -1,26 +0,0 @@
From dc03f0fbb400bad5c4748eb969f4a85c68e3bc0c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
Date: Wed, 26 Jul 2023 21:14:34 +0200
Subject: [PATCH] DONOTMERGE: Add pxa,rev-id to board dts
This won't be accepted upstream, but it's needed to boot with just
S-Boot, so add this here.
---
arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
index e3c863d517a8..04fb0566ed2b 100644
--- a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
+++ b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
@@ -4,6 +4,7 @@
#include <dt-bindings/input/linux-event-codes.h>
/ {
+ pxa,rev-id = <3928 2>;
model = "Samsung Galaxy Core Prime VE LTE";
compatible = "samsung,coreprimevelte", "marvell,pxa1908";
--
2.42.0

99
device/testing/linux-samsung-coreprimevelte-mainline/0011-input-generalize-the-Imagis-touchscreen-driver.patch
View file

@ -1,99 +0,0 @@
From 7dded3d2412f6f1d1668034b3b2acc8ffa663ac3 Mon Sep 17 00:00:00 2001
From: Karel Balej <balejk@matfyz.cz>
Date: Mon, 25 Sep 2023 22:30:27 +0200
Subject: [PATCH] input: generalize the Imagis touchscreen driver
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This driver works with other Imagis ICs of the IST30**C series. Make
that apparent.
Signed-off-by: Karel Balej <balejk@matfyz.cz>
Co-developed-by: Duje Mihanović <duje.mihanovic@skole.hr>
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
drivers/input/touchscreen/imagis.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/input/touchscreen/imagis.c b/drivers/input/touchscreen/imagis.c
index 07111ca24455..d61fbbe61bc8 100644
--- a/drivers/input/touchscreen/imagis.c
+++ b/drivers/input/touchscreen/imagis.c
@@ -18,7 +18,6 @@
#define IST3038C_REG_TOUCH_STATUS (IST3038C_REG_HIB_BASE | IST3038C_HIB_ACCESS)
#define IST3038C_REG_TOUCH_COORD (IST3038C_REG_HIB_BASE | IST3038C_HIB_ACCESS | 0x8)
#define IST3038C_REG_INTR_MESSAGE (IST3038C_REG_HIB_BASE | IST3038C_HIB_ACCESS | 0x4)
-#define IST3038C_WHOAMI 0x38c
#define IST3038C_CHIP_ON_DELAY_MS 60
#define IST3038C_I2C_RETRY_COUNT 3
#define IST3038C_MAX_FINGER_NUM 10
@@ -31,6 +30,8 @@
#define IST3038C_FINGER_COUNT_SHIFT 12
#define IST3038C_FINGER_STATUS_MASK GENMASK(9, 0)
+#define IST3038C_WHOAMI 0x38c
+
struct imagis_ts {
struct i2c_client *client;
struct input_dev *input_dev;
@@ -253,7 +254,7 @@ static int imagis_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct imagis_ts *ts;
- int chip_id, error;
+ int chip_id, dt_chip_id, error;
ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL);
if (!ts)
@@ -261,6 +262,8 @@ static int imagis_probe(struct i2c_client *i2c)
ts->client = i2c;
+ dt_chip_id = (int)(uintptr_t) device_get_match_data(&i2c->dev);
+
error = imagis_init_regulators(ts);
if (error) {
dev_err(dev, "regulator init error: %d\n", error);
@@ -287,8 +290,8 @@ static int imagis_probe(struct i2c_client *i2c)
return error;
}
- if (chip_id != IST3038C_WHOAMI) {
- dev_err(dev, "unknown chip ID: 0x%x\n", chip_id);
+ if (chip_id != dt_chip_id) {
+ dev_err(dev, "unknown or misconfigured chip ID: 0x%x\n", chip_id);
return -EINVAL;
}
@@ -345,12 +348,18 @@ static DEFINE_SIMPLE_DEV_PM_OPS(imagis_pm_ops, imagis_suspend, imagis_resume);
#ifdef CONFIG_OF
static const struct of_device_id imagis_of_match[] = {
- { .compatible = "imagis,ist3038c", },
+ { .compatible = "imagis,ist3038c", .data = (void *) IST3038C_WHOAMI, },
{ },
};
MODULE_DEVICE_TABLE(of, imagis_of_match);
#endif
+static const struct i2c_device_id imagis_ts_i2c_id[] = {
+ { "ist3038c", IST3038C_WHOAMI, },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, imagis_ts_i2c_id);
+
static struct i2c_driver imagis_ts_driver = {
.driver = {
.name = "imagis-touchscreen",
@@ -358,6 +367,7 @@ static struct i2c_driver imagis_ts_driver = {
.of_match_table = of_match_ptr(imagis_of_match),
},
.probe = imagis_probe,
+ .id_table = imagis_ts_i2c_id,
};
module_i2c_driver(imagis_ts_driver);
--
2.42.0

31
device/testing/linux-samsung-coreprimevelte-mainline/0012-Documentation-imagis-document-IST3032C-support.patch
View file

@ -1,31 +0,0 @@
From 0485f6ddd33a4ca4105e18628e74318f5893c7ec Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
Date: Thu, 28 Sep 2023 18:49:25 +0200
Subject: [PATCH] Documentation: imagis: document IST3032C support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The imagis driver supports the IST3032C. Add this to the driver
documentation.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
.../devicetree/bindings/input/touchscreen/imagis,ist3038c.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/input/touchscreen/imagis,ist3038c.yaml b/Documentation/devicetree/bindings/input/touchscreen/imagis,ist3038c.yaml
index 0d6b033fd5fb..f364ffb05c8d 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/imagis,ist3038c.yaml
+++ b/Documentation/devicetree/bindings/input/touchscreen/imagis,ist3038c.yaml
@@ -18,6 +18,7 @@ properties:
compatible:
enum:
+ - imagis,ist3032c
- imagis,ist3038c
reg:
--
2.42.0

49
device/testing/linux-samsung-coreprimevelte-mainline/0013-input-Imagis-add-support-for-IST3032C-touchscreen.patch
View file

@ -1,49 +0,0 @@
From 7d16c4619210af0f8793f74452b412a9711c8e9e Mon Sep 17 00:00:00 2001
From: Karel Balej <balejk@matfyz.cz>
Date: Mon, 25 Sep 2023 22:36:21 +0200
Subject: [PATCH] input: Imagis: add support for IST3032C touchscreen
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add the Imagis IST3032C to the imagis driver. The only functional
difference is in the WHOAMI identifier.
Signed-off-by: Karel Balej <balejk@matfyz.cz>
Co-developed-by: Duje Mihanović <duje.mihanovic@skole.hr>
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
drivers/input/touchscreen/imagis.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/input/touchscreen/imagis.c b/drivers/input/touchscreen/imagis.c
index d61fbbe61bc8..5367b8d96e66 100644
--- a/drivers/input/touchscreen/imagis.c
+++ b/drivers/input/touchscreen/imagis.c
@@ -30,6 +30,7 @@
#define IST3038C_FINGER_COUNT_SHIFT 12
#define IST3038C_FINGER_STATUS_MASK GENMASK(9, 0)
+#define IST3032C_WHOAMI 0x32c
#define IST3038C_WHOAMI 0x38c
struct imagis_ts {
@@ -348,6 +349,7 @@ static DEFINE_SIMPLE_DEV_PM_OPS(imagis_pm_ops, imagis_suspend, imagis_resume);
#ifdef CONFIG_OF
static const struct of_device_id imagis_of_match[] = {
+ { .compatible = "imagis,ist3032c", .data = (void *) IST3032C_WHOAMI, },
{ .compatible = "imagis,ist3038c", .data = (void *) IST3038C_WHOAMI, },
{ },
};
@@ -355,6 +357,7 @@ MODULE_DEVICE_TABLE(of, imagis_of_match);
#endif
static const struct i2c_device_id imagis_ts_i2c_id[] = {
+ { "ist3032c", IST3032C_WHOAMI, },
{ "ist3038c", IST3038C_WHOAMI, },
{ }
};
--
2.42.0

35
device/testing/linux-samsung-coreprimevelte-mainline/0014-arm64-dts-add-touchscreen-bindings-for-samsung-corep.patch
View file

@ -1,35 +0,0 @@
From bdb5e1cd9435a942465d4e195a70b3b475eda6aa Mon Sep 17 00:00:00 2001
From: Karel Balej <balejk@matfyz.cz>
Date: Mon, 25 Sep 2023 22:41:24 +0200
Subject: [PATCH] arm64: dts: add touchscreen bindings for
samsung,coreprimevelte
Signed-off-by: Karel Balej <balejk@matfyz.cz>
---
.../dts/marvell/pxa1908-samsung-coreprimevelte.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
index 04fb0566ed2b..bd69358fd069 100644
--- a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
+++ b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
@@ -309,6 +309,16 @@ &twsi2 {
&twsi3 {
status = "okay";
+
+ touchscreen@50 {
+ compatible = "imagis,ist3032c";
+ reg = <0x50>;
+ interrupt-parent = <&gpio>;
+ interrupts = <72 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&ldo2>;
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <800>;
+ };
};
&usb {
--
2.42.0

56
device/testing/linux-samsung-coreprimevelte-mainline/0015-mfd-add-Marvell-88pm88x-description.patch
View file

@ -1,56 +0,0 @@
From 15786525bbad9763a1ddff188d75e5a4c534fa9e Mon Sep 17 00:00:00 2001
From: Yi Zhang <yizhang@marvell.com>
Date: Fri, 12 Jun 2015 16:43:20 +0800
Subject: [PATCH] mfd: add Marvell 88pm88x description
88pm880 and 88pm886 are two combo PMIC chips, most of the function and the
register mapping are the same
Signed-off-by: Yi Zhang <yizhang@marvell.com>
---
.../devicetree/bindings/mfd/88pm88x.txt | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/88pm88x.txt
diff --git a/Documentation/devicetree/bindings/mfd/88pm88x.txt b/Documentation/devicetree/bindings/mfd/88pm88x.txt
new file mode 100644
index 000000000000..72e741cf3ebf
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/88pm88x.txt
@@ -0,0 +1,33 @@
+Marvell 88pm88x combo PMIC chip
+
+This series of chip integrates regulator, rtc, onkey, switch charger,
+fuelgauge, gpadc and a range of I/O pins.
+
+88pm886 and 88pm880 are two very similar chips, most of the registers mapping
+and functions are the same, the main difference is the latter has a separate
+i2c slave address to cover BUCK related setting
+
+Required properties:
+- compatible: one of the strings for a specific chip:
+ "marvell,88pm886"
+ "marvell,88pm880"
+- reg: the i2c address
+- interrupt-controller: it works as an interrupt controller managing its irqs
+- interrupt-cells: this value is 1
+
+Optional properties:
+- marvell,88pm88x-irq-write-clear: the interrupt ack method
+
+
+Example:
+
+ pmic: 88pm886@30 {
+ compatible = "marvell,88pm886";
+ reg = <0x30>;
+ interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ marvell,88pm88x-irq-write-clear;
+ };
--
2.42.0

2063
device/testing/linux-samsung-coreprimevelte-mainline/0016-mfd-88pm88x-initialize-88pm886-88pm880-base-support.patch
View file

File diff suppressed because it is too large Load diff

220
device/testing/linux-samsung-coreprimevelte-mainline/0017-DONOTMERGE-fix-88pm88x-build.patch
View file

@ -1,220 +0,0 @@
From db98663bffbf33a89cc3286abb4f5c7844e78f79 Mon Sep 17 00:00:00 2001
From: Karel Balej <balejk@matfyz.cz>
Date: Mon, 14 Aug 2023 18:02:03 +0200
Subject: [PATCH] DONOTMERGE: fix 88pm88x build
---
drivers/mfd/88pm880-table.c | 26 +++++++++++++-------------
drivers/mfd/88pm886-table.c | 34 +++++++++++++++++-----------------
drivers/mfd/88pm88x-core.c | 10 +++++-----
drivers/mfd/88pm88x-i2c.c | 6 ++----
drivers/mfd/88pm88x-irq.c | 3 +--
include/linux/mfd/88pm88x.h | 1 +
6 files changed, 39 insertions(+), 41 deletions(-)
diff --git a/drivers/mfd/88pm880-table.c b/drivers/mfd/88pm880-table.c
index 28ca86028905..03a19eb63632 100644
--- a/drivers/mfd/88pm880-table.c
+++ b/drivers/mfd/88pm880-table.c
@@ -96,28 +96,28 @@ struct pmic_cell_info pm880_cell_info = {
.cell_nr = ARRAY_SIZE(pm880_cell_devs),
};
-static const struct reg_default pm880_base_patch[] = {
- {PM88X_WDOG, 0x1}, /* disable watchdog */
- {PM88X_AON_CTRL2, 0x2a}, /* output 32kHZ from XO */
- {PM88X_BK_OSC_CTRL1, 0x0f}, /* OSC_FREERUN = 1, to lock FLL */
- {PM88X_LOWPOWER2, 0x20}, /* XO_LJ = 1, enable low jitter for 32kHZ */
+static const struct reg_sequence pm880_base_patch[] = {
+ REG_SEQ0(PM88X_WDOG, 0x1), /* disable watchdog */
+ REG_SEQ0(PM88X_AON_CTRL2, 0x2a), /* output 32kHZ from XO */
+ REG_SEQ0(PM88X_BK_OSC_CTRL1, 0x0f), /* OSC_FREERUN = 1, to lock FLL */
+ REG_SEQ0(PM88X_LOWPOWER2, 0x20), /* XO_LJ = 1, enable low jitter for 32kHZ */
/* enable LPM for internal reference group in sleep */
- {PM88X_LOWPOWER4, 0xc0},
- {PM88X_BK_OSC_CTRL3, 0xc0}, /* set the duty cycle of charger DC/DC to max */
+ REG_SEQ0(PM88X_LOWPOWER4, 0xc0),
+ REG_SEQ0(PM88X_BK_OSC_CTRL3, 0xc0), /* set the duty cycle of charger DC/DC to max */
};
-static const struct reg_default pm880_power_patch[] = {
+static const struct reg_sequence pm880_power_patch[] = {
};
-static const struct reg_default pm880_gpadc_patch[] = {
- {PM88X_GPADC_CONFIG6, 0x03}, /* enable non-stop mode */
+static const struct reg_sequence pm880_gpadc_patch[] = {
+ REG_SEQ0(PM88X_GPADC_CONFIG6, 0x03), /* enable non-stop mode */
};
-static const struct reg_default pm880_battery_patch[] = {
- {PM88X_CHGBK_CONFIG6, 0xe1},
+static const struct reg_sequence pm880_battery_patch[] = {
+ REG_SEQ0(PM88X_CHGBK_CONFIG6, 0xe1),
};
-static const struct reg_default pm880_test_patch[] = {
+static const struct reg_sequence pm880_test_patch[] = {
};
/* 88pm880 chip itself related */
diff --git a/drivers/mfd/88pm886-table.c b/drivers/mfd/88pm886-table.c
index 897ee82a30c7..7558420ff3c5 100644
--- a/drivers/mfd/88pm886-table.c
+++ b/drivers/mfd/88pm886-table.c
@@ -92,32 +92,32 @@ struct pmic_cell_info pm886_cell_info = {
.cell_nr = ARRAY_SIZE(pm886_cell_devs),
};
-static const struct reg_default pm886_base_patch[] = {
- {PM88X_WDOG, 0x1}, /* disable watchdog */
- {PM88X_GPIO_CTRL1, 0x40}, /* gpio1: dvc , gpio0: input */
- {PM88X_GPIO_CTRL2, 0x00}, /* , gpio2: input */
- {PM88X_GPIO_CTRL3, 0x44}, /* dvc2 , dvc1 */
- {PM88X_GPIO_CTRL4, 0x00}, /* gpio5v_1:input, gpio5v_2: input*/
- {PM88X_AON_CTRL2, 0x2a}, /* output 32kHZ from XO */
- {PM88X_BK_OSC_CTRL1, 0x0f}, /* OSC_FREERUN = 1, to lock FLL */
- {PM88X_LOWPOWER2, 0x20}, /* XO_LJ = 1, enable low jitter for 32kHZ */
+static const struct reg_sequence pm886_base_patch[] = {
+ REG_SEQ0(PM88X_WDOG, 0x1), /* disable watchdog */
+ REG_SEQ0(PM88X_GPIO_CTRL1, 0x40), /* gpio1: dvc , gpio0: input */
+ REG_SEQ0(PM88X_GPIO_CTRL2, 0x00), /* , gpio2: input */
+ REG_SEQ0(PM88X_GPIO_CTRL3, 0x44), /* dvc2 , dvc1 */
+ REG_SEQ0(PM88X_GPIO_CTRL4, 0x00), /* gpio5v_1:input, gpio5v_2: input*/
+ REG_SEQ0(PM88X_AON_CTRL2, 0x2a), /* output 32kHZ from XO */
+ REG_SEQ0(PM88X_BK_OSC_CTRL1, 0x0f), /* OSC_FREERUN = 1, to lock FLL */
+ REG_SEQ0(PM88X_LOWPOWER2, 0x20), /* XO_LJ = 1, enable low jitter for 32kHZ */
/* enable LPM for internal reference group in sleep */
- {PM88X_LOWPOWER4, 0xc0},
- {PM88X_BK_OSC_CTRL3, 0xc0}, /* set the duty cycle of charger DC/DC to max */
+ REG_SEQ0(PM88X_LOWPOWER4, 0xc0),
+ REG_SEQ0(PM88X_BK_OSC_CTRL3, 0xc0), /* set the duty cycle of charger DC/DC to max */
};
-static const struct reg_default pm886_power_patch[] = {
+static const struct reg_sequence pm886_power_patch[] = {
};
-static const struct reg_default pm886_gpadc_patch[] = {
- {PM88X_GPADC_CONFIG6, 0x03}, /* enable non-stop mode */
+static const struct reg_sequence pm886_gpadc_patch[] = {
+ REG_SEQ0(PM88X_GPADC_CONFIG6, 0x03), /* enable non-stop mode */
};
-static const struct reg_default pm886_battery_patch[] = {
- {PM88X_CHGBK_CONFIG6, 0xe1},
+static const struct reg_sequence pm886_battery_patch[] = {
+ REG_SEQ0(PM88X_CHGBK_CONFIG6, 0xe1),
};
-static const struct reg_default pm886_test_patch[] = {
+static const struct reg_sequence pm886_test_patch[] = {
};
/* 88pm886 chip itself related */
diff --git a/drivers/mfd/88pm88x-core.c b/drivers/mfd/88pm88x-core.c
index 343e0a0f3f8b..04409a2b0356 100644
--- a/drivers/mfd/88pm88x-core.c
+++ b/drivers/mfd/88pm88x-core.c
@@ -342,7 +342,7 @@ int pm88x_init_pages(struct pm88x_chip *chip)
}
/* power page */
- chip->power_page = i2c_new_dummy(client->adapter, chip->power_page_addr);
+ chip->power_page = i2c_new_dummy_device(client->adapter, chip->power_page_addr);
if (!chip->power_page) {
dev_err(chip->dev, "Failed to new power_page: %d\n", ret);
ret = -ENODEV;
@@ -357,7 +357,7 @@ int pm88x_init_pages(struct pm88x_chip *chip)
}
/* gpadc page */
- chip->gpadc_page = i2c_new_dummy(client->adapter, chip->gpadc_page_addr);
+ chip->gpadc_page = i2c_new_dummy_device(client->adapter, chip->gpadc_page_addr);
if (!chip->gpadc_page) {
dev_err(chip->dev, "Failed to new gpadc_page: %d\n", ret);
ret = -ENODEV;
@@ -372,7 +372,7 @@ int pm88x_init_pages(struct pm88x_chip *chip)
}
/* battery page */
- chip->battery_page = i2c_new_dummy(client->adapter, chip->battery_page_addr);
+ chip->battery_page = i2c_new_dummy_device(client->adapter, chip->battery_page_addr);
if (!chip->battery_page) {
dev_err(chip->dev, "Failed to new gpadc_page: %d\n", ret);
ret = -ENODEV;
@@ -387,7 +387,7 @@ int pm88x_init_pages(struct pm88x_chip *chip)
}
/* test page */
- chip->test_page = i2c_new_dummy(client->adapter, chip->test_page_addr);
+ chip->test_page = i2c_new_dummy_device(client->adapter, chip->test_page_addr);
if (!chip->test_page) {
dev_err(chip->dev, "Failed to new test_page: %d\n", ret);
ret = -ENODEV;
@@ -416,7 +416,7 @@ int pm88x_init_pages(struct pm88x_chip *chip)
chip->ldo_regmap = chip->power_regmap;
/* buck page */
- chip->buck_page = i2c_new_dummy(client->adapter,
+ chip->buck_page = i2c_new_dummy_device(client->adapter,
chip->buck_page_addr);
if (!chip->buck_page) {
dev_err(chip->dev, "Failed to new buck_page: %d\n", ret);
diff --git a/drivers/mfd/88pm88x-i2c.c b/drivers/mfd/88pm88x-i2c.c
index 36842ed02e9a..7650014d9c90 100644
--- a/drivers/mfd/88pm88x-i2c.c
+++ b/drivers/mfd/88pm88x-i2c.c
@@ -22,8 +22,7 @@
#include <linux/mfd/88pm880.h>
#include <linux/mfd/88pm88x.h>
-static int pm88x_i2c_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
+static int pm88x_i2c_probe(struct i2c_client *client)
{
struct pm88x_chip *chip;
struct device_node *node = client->dev.of_node;
@@ -104,11 +103,10 @@ static int pm88x_i2c_probe(struct i2c_client *client,
return ret;
}
-static int pm88x_i2c_remove(struct i2c_client *i2c)
+static void pm88x_i2c_remove(struct i2c_client *i2c)
{
struct pm88x_chip *chip = dev_get_drvdata(&i2c->dev);
pm88x_dev_exit(chip);
- return 0;
}
static const struct i2c_device_id pm88x_i2c_id[] = {
diff --git a/drivers/mfd/88pm88x-irq.c b/drivers/mfd/88pm88x-irq.c
index 0126df0231b8..ea9f6636e700 100644
--- a/drivers/mfd/88pm88x-irq.c
+++ b/drivers/mfd/88pm88x-irq.c
@@ -131,9 +131,8 @@ struct regmap_irq_chip pm88x_irq_chip = {
.num_regs = 4,
.status_base = PM88X_INT_STATUS1,
- .mask_base = PM88X_INT_ENA_1,
+ .unmask_base = PM88X_INT_ENA_1,
.ack_base = PM88X_INT_STATUS1,
- .mask_invert = 1,
};
int pm88x_irq_init(struct pm88x_chip *chip)
diff --git a/include/linux/mfd/88pm88x.h b/include/linux/mfd/88pm88x.h
index efa2fe621ccd..91a84b551d15 100644
--- a/include/linux/mfd/88pm88x.h
+++ b/include/linux/mfd/88pm88x.h
@@ -20,6 +20,7 @@
#include <linux/regmap.h>
#include <linux/atomic.h>
#include <linux/reboot.h>
+#include <linux/mod_devicetable.h>
#include "88pm88x-reg.h"
#include "88pm886-reg.h"
--
2.42.0

2176
device/testing/linux-samsung-coreprimevelte-mainline/0018-DONOTMERGE-add-downstream-regulator-driver.patch
View file

File diff suppressed because it is too large Load diff

208
device/testing/linux-samsung-coreprimevelte-mainline/0019-DONOTMERGE-fix-build-for-the-88pm88x-regulator-drive.patch
View file

@ -1,208 +0,0 @@
From f613c321a4e37bce1603f1b2e8ffac01c7c0fb25 Mon Sep 17 00:00:00 2001
From: Karel Balej <balejk@matfyz.cz>
Date: Sun, 24 Sep 2023 13:01:20 +0200
Subject: [PATCH] DONOTMERGE: fix build for the 88pm88x regulator driver
---
drivers/regulator/88pm88x-buck.c | 10 +++++-----
drivers/regulator/88pm88x-ldo.c | 2 +-
drivers/regulator/88pm88x-vr.c | 12 ++++++------
include/linux/mfd/88pm880.h | 10 ++++++++++
include/linux/mfd/88pm886.h | 4 ++++
include/linux/mfd/88pm88x.h | 20 +++++++++++++-------
6 files changed, 39 insertions(+), 19 deletions(-)
diff --git a/drivers/regulator/88pm88x-buck.c b/drivers/regulator/88pm88x-buck.c
index 7546e0fb9d87..1e0c29bfdce1 100644
--- a/drivers/regulator/88pm88x-buck.c
+++ b/drivers/regulator/88pm88x-buck.c
@@ -119,7 +119,7 @@
* from 0x00 to 0x4F: step is 12.5mV, range is from 0.6V to 1.6V
* from 0x50 to 0x3F step is 50mV, range is from 1.6V to 1.8V
*/
-static const struct regulator_linear_range buck_volt_range1[] = {
+static const struct linear_range buck_volt_range1[] = {
REGULATOR_LINEAR_RANGE(600000, 0, 0x4f, 12500),
REGULATOR_LINEAR_RANGE(1600000, 0x50, 0x54, 50000),
};
@@ -129,7 +129,7 @@ static const struct regulator_linear_range buck_volt_range1[] = {
* from 0x00 to 0x4F VOUT step is 12.5mV, range is from 0.6V to 1.6V
* from 0x50 to 0x72 step is 50mV, range is from 1.6V to 3.3V
*/
-static const struct regulator_linear_range buck_volt_range2[] = {
+static const struct linear_range buck_volt_range2[] = {
REGULATOR_LINEAR_RANGE(600000, 0, 0x4f, 12500),
REGULATOR_LINEAR_RANGE(1600000, 0x50, 0x72, 50000),
};
@@ -394,7 +394,7 @@ static const struct of_device_id pm88x_bucks_of_match[] = {
*/
static int pm88x_get_vbuck_vol(unsigned int val, struct pm88x_buck_info *info)
{
- const struct regulator_linear_range *range;
+ const struct linear_range *range;
int i, volt = -EINVAL;
/* get the voltage via the register value */
@@ -404,7 +404,7 @@ static int pm88x_get_vbuck_vol(unsigned int val, struct pm88x_buck_info *info)
return -EINVAL;
if (val >= range->min_sel && val <= range->max_sel) {
- volt = (val - range->min_sel) * range->uV_step + range->min_uV;
+ volt = (val - range->min_sel) * range->step + range->min;
break;
}
}
@@ -634,7 +634,7 @@ static int pm88x_buck_probe(struct platform_device *pdev)
if (match) {
const_info = match->data;
init_data = of_get_regulator_init_data(&pdev->dev,
- pdev->dev.of_node);
+ pdev->dev.of_node, &const_info->desc);
} else {
dev_err(&pdev->dev, "parse dts fails!\n");
return -EINVAL;
diff --git a/drivers/regulator/88pm88x-ldo.c b/drivers/regulator/88pm88x-ldo.c
index d2bf731e2dcc..2d3d14f4f78f 100644
--- a/drivers/regulator/88pm88x-ldo.c
+++ b/drivers/regulator/88pm88x-ldo.c
@@ -646,7 +646,7 @@ static int pm88x_ldo_probe(struct platform_device *pdev)
if (match) {
const_info = match->data;
init_data = of_get_regulator_init_data(&pdev->dev,
- pdev->dev.of_node);
+ pdev->dev.of_node, &const_info->desc);
} else {
dev_err(&pdev->dev, "parse dts fails!\n");
return -EINVAL;
diff --git a/drivers/regulator/88pm88x-vr.c b/drivers/regulator/88pm88x-vr.c
index 2175859b8727..dacac878eaa2 100644
--- a/drivers/regulator/88pm88x-vr.c
+++ b/drivers/regulator/88pm88x-vr.c
@@ -128,12 +128,12 @@
#define PM880_BUCK_AUDIO_OF_MATCH(comp, label) \
PM88X_BUCK_AUDIO_OF_MATCH(pm880, PM880_ID, comp, label)
-static const struct regulator_linear_range buck_slp_volt_range1[] = {
+static const struct linear_range buck_slp_volt_range1[] = {
REGULATOR_LINEAR_RANGE(600000, 0, 0x4f, 12500),
REGULATOR_LINEAR_RANGE(1600000, 0x50, 0x54, 50000),
};
-static const struct regulator_linear_range buck_audio_volt_range1[] = {
+static const struct linear_range buck_audio_volt_range1[] = {
REGULATOR_LINEAR_RANGE(600000, 0, 0x54, 12500),
};
@@ -364,9 +364,9 @@ static int of_get_legacy_init_data(struct device *dev,
* to a real voltage value (in uV) according to the voltage table.
*/
static int pm88x_get_vvr_vol(unsigned int val, unsigned int n_linear_ranges,
- const struct regulator_linear_range *ranges)
+ const struct linear_range *ranges)
{
- const struct regulator_linear_range *range;
+ const struct linear_range *range;
int i, volt = -EINVAL;
/* get the voltage via the register value */
@@ -376,7 +376,7 @@ static int pm88x_get_vvr_vol(unsigned int val, unsigned int n_linear_ranges,
return -EINVAL;
if (val >= range->min_sel && val <= range->max_sel) {
- volt = (val - range->min_sel) * range->uV_step + range->min_uV;
+ volt = (val - range->min_sel) * range->step + range->min;
break;
}
}
@@ -584,7 +584,7 @@ static int pm88x_virtual_regulator_probe(struct platform_device *pdev)
if (match) {
const_info = match->data;
init_data = of_get_regulator_init_data(&pdev->dev,
- pdev->dev.of_node);
+ pdev->dev.of_node, &const_info->desc);
ret = of_get_legacy_init_data(&pdev->dev, &init_data);
if (ret < 0)
return ret;
diff --git a/include/linux/mfd/88pm880.h b/include/linux/mfd/88pm880.h
index 94b9e063918a..3952f8d29c32 100644
--- a/include/linux/mfd/88pm880.h
+++ b/include/linux/mfd/88pm880.h
@@ -33,6 +33,16 @@ enum {
PM880_ID_BUCK_MAX = 7,
};
+enum {
+ PM880_ID_BUCK1A_SLP = 0,
+ PM880_ID_BUCK1B_SLP,
+};
+
+enum {
+ PM880_ID_BUCK1A_AUDIO = 0,
+ PM880_ID_BUCK1B_AUDIO,
+};
+
enum {
PM880_ID_LDO1 = 0,
PM880_ID_LDO2,
diff --git a/include/linux/mfd/88pm886.h b/include/linux/mfd/88pm886.h
index 939040647702..9db077be1f79 100644
--- a/include/linux/mfd/88pm886.h
+++ b/include/linux/mfd/88pm886.h
@@ -52,4 +52,8 @@ enum {
PM886_ID_LDO_MAX = 16,
};
+enum {
+ PM886_ID_BUCK1_SLP = 0,
+};
+
#endif /* __LINUX_MFD_88PM886_H */
diff --git a/include/linux/mfd/88pm88x.h b/include/linux/mfd/88pm88x.h
index 91a84b551d15..ceffd976d3b7 100644
--- a/include/linux/mfd/88pm88x.h
+++ b/include/linux/mfd/88pm88x.h
@@ -32,14 +32,27 @@
#define PM88X_VBUS_NAME "88pm88x-vbus"
#define PM88X_CFD_NAME "88pm88x-leds"
#define PM88X_RGB_NAME "88pm88x-rgb"
+#define PM88X_DEBUGFS_NAME "88pm88x-debugfs"
#define PM88X_GPADC_NAME "88pm88x-gpadc"
+#define PM88X_HWMON_NAME "88pm88x-hwmon"
#define PM88X_DVC_NAME "88pm88x-dvc"
+#define PM88X_VIRTUAL_REGULATOR_NAME "88pm88x-vr"
enum pm88x_type {
PM886 = 1,
PM880 = 2,
};
+enum {
+ PM88X_ID_VOTG = 0,
+};
+
+enum {
+ PM88X_RGB_LED0,
+ PM88X_RGB_LED1,
+ PM88X_RGB_LED2,
+};
+
enum pm88x_pages {
PM88X_BASE_PAGE = 0,
PM88X_LDO_PAGE,
@@ -95,13 +108,6 @@ enum pm88x_irq_number {
PM88X_MAX_IRQ, /* 28 */
};
-/* 3 rgb led indicators */
-enum {
- PM88X_RGB_LED0,
- PM88X_RGB_LED1,
- PM88X_RGB_LED2,
-};
-
/* camera flash/torch */
enum {
PM88X_NO_LED = -1,
--
2.42.0

306
device/testing/linux-samsung-coreprimevelte-mainline/0020-DONOTMERGE-add-88pm88x-DT-bindings.patch
View file

@ -1,306 +0,0 @@
From 8cde8feee2afae8f509b52ec14474a51a72a8991 Mon Sep 17 00:00:00 2001
From: Karel Balej <balejk@matfyz.cz>
Date: Mon, 14 Aug 2023 18:58:13 +0200
Subject: [PATCH] DONOTMERGE: add 88pm88x DT bindings
---
arch/arm64/boot/dts/marvell/88pm886.dtsi | 151 ++++++++++++++++++
arch/arm64/boot/dts/marvell/88pm88x.dtsi | 66 ++++++++
.../pxa1908-samsung-coreprimevelte.dts | 39 +++++
3 files changed, 256 insertions(+)
create mode 100644 arch/arm64/boot/dts/marvell/88pm886.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/88pm88x.dtsi
diff --git a/arch/arm64/boot/dts/marvell/88pm886.dtsi b/arch/arm64/boot/dts/marvell/88pm886.dtsi
new file mode 100644
index 000000000000..084e922f4e4c
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/88pm886.dtsi
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2014 Marvell
+ * Yi Zhang <yizhang@marvell.com>
+ */
+
+/*
+ * Integrated Power Management Chip
+ * header file for Marvell PMIC: 88pm886
+ */
+
+&pmic0 {
+ compatible = "marvell,88pm886";
+ /* ---buck--- */
+ vccmain: regulator-buck1 {
+ compatible = "marvell,88pm886-buck1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ buck2: regulator-buck2 {
+ compatible = "marvell,88pm886-buck2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ vddr: regulator-buck3 {
+ compatible = "marvell,88pm886-buck3";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ buck4: regulator-buck4 {
+ compatible = "marvell,88pm886-buck4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ buck5: regulator-buck5 {
+ compatible = "marvell,88pm886-buck5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* ---ldo--- */
+ /*
+ ldo1: regulator-ldo1 {
+ compatible = "marvell,88pm886-ldo1";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ */
+ ldo2: regulator-ldo2 {
+ compatible = "marvell,88pm886-ldo2";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ /*
+ ldo3: regulator-ldo3 {
+ compatible = "marvell,88pm886-ldo3";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo4: regulator-ldo4 {
+ compatible = "marvell,88pm886-ldo4";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo5: regulator-ldo5 {
+ compatible = "marvell,88pm886-ldo5";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo6: regulator-ldo6 {
+ compatible = "marvell,88pm886-ldo6";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo7: regulator-ldo7 {
+ compatible = "marvell,88pm886-ldo7";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo8: regulator-ldo8 {
+ compatible = "marvell,88pm886-ldo8";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo9: regulator-ldo9 {
+ compatible = "marvell,88pm886-ldo9";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo10: regulator-ldo10 {
+ compatible = "marvell,88pm886-ldo10";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo11: regulator-ldo11 {
+ compatible = "marvell,88pm886-ldo11";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo12: regulator-ldo12 {
+ compatible = "marvell,88pm886-ldo12";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo13: regulator-ldo13 {
+ compatible = "marvell,88pm886-ldo13";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo14: regulator-ldo14 {
+ compatible = "marvell,88pm886-ldo14";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo15: regulator-ldo15 {
+ compatible = "marvell,88pm886-ldo15";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo16: regulator-ldo16 {
+ compatible = "marvell,88pm886-ldo16";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <2800000>;
+ };
+ */
+
+ /* virtual regulator */
+ buck1slp: regulator-buck1-slp {
+ compatible = "marvell,88pm886-buck1-slp";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ marvell,consumer-supplies = "buck1slp", "nameless";
+ };
+
+ gpadc: gpadc{
+ compatible = "marvell,88pm886-gpadc";
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ };
+};
diff --git a/arch/arm64/boot/dts/marvell/88pm88x.dtsi b/arch/arm64/boot/dts/marvell/88pm88x.dtsi
new file mode 100644
index 000000000000..39f3943b9f6c
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/88pm88x.dtsi
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2014 Marvell
+ * Yi Zhang <yizhang@marvell.com>
+ */
+
+/*
+ * Integrated Power Management Chip
+ * common header file for Marvell PMIC: 88pm88x
+ */
+
+&pmic0 {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ marvell,88pm88x-irq-write-clear;
+
+ onkey {
+ compatible = "marvell,88pm88x-onkey";
+ /* marvell,pm886-onkey-gpio-number = <1>; */
+ };
+
+ vbus {
+ compatible = "marvell,88pm88x-vbus";
+ };
+
+ rtc {
+ compatible = "marvell,88pm88x-rtc";
+ };
+
+ charger {
+ compatible = "marvell,88pm88x-charger";
+ };
+
+ battery {
+ compatible = "marvell,88pm88x-battery";
+ };
+
+ dvc {
+ compatible = "marvell,88pm88x-dvc";
+ };
+
+ headset {
+ compatible = "marvell,88pm88x-headset";
+ status = "disabled";
+ };
+
+ led {
+ compatible = "marvell,88pm88x-leds";
+ };
+
+ red: led-rgb0 {
+ compatible = "marvell,88pm88x-rgb0";
+ };
+ green: led-rgb1 {
+ compatible = "marvell,88pm88x-rgb1";
+ };
+ blue: led-rgb2 {
+ compatible = "marvell,88pm88x-rgb2";
+ };
+
+ gpadc: gpadc{
+ compatible = "marvell,88pm88x-gpadc";
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ };
+};
diff --git a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
index bd69358fd069..b1ae358c5778 100644
--- a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
+++ b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
@@ -2,6 +2,8 @@
#include "pxa1908.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
+// FIXME
+#define IRQF_TRIGGER_HIGH 0x00000004
/ {
pxa,rev-id = <3928 2>;
@@ -305,6 +307,41 @@ &twsi1 {
&twsi2 {
status = "okay";
+ pmic0: 88pm886@30 {
+ compatible = "marvell,88pm886";
+ reg = <0x30>;
+ interrupts = <0 4 IRQF_TRIGGER_HIGH>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ marvell,88pm88x-irq-write-clear;
+
+ onkey {
+ marvell,pm88x-onkey-gpio-number = <0>;
+ };
+
+ vbus {
+ gpadc-number = <1>;
+ };
+
+ battery {
+ bat-software-battery-detection;
+ /* bat-ntc-support; */
+ bat-ntc-support;
+ gpadc-det-no = <2>;
+ gpadc-temp-no = <3>;
+ };
+ };
+ pmic2: 88pm860@38 {
+ compatible = "marvell,88pm860";
+ reg = <0x38>;
+ marvell,pmic-type = <1>;
+ pm860_codec: pm860_codec {
+ compatible = "marvell,88pm860-codec";
+ #dailink-cells = <1>;
+ };
+ };
};
&twsi3 {
@@ -342,3 +379,5 @@ &sdh0 {
bus-width = <4>;
wp-inverted;
};
+#include "88pm886.dtsi"
+#include "88pm88x.dtsi"
--
2.42.0

25
device/testing/linux-samsung-coreprimevelte-mainline/0021-set-touchscreen-VDD-regulator-to-3.1V.patch
View file

@ -1,25 +0,0 @@
From cd329af16a6e443bc0c43628dfe7949758c5191e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
Date: Thu, 28 Sep 2023 18:33:07 +0200
Subject: [PATCH] set touchscreen VDD regulator to 3.1V
---
arch/arm64/boot/dts/marvell/88pm886.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/88pm886.dtsi b/arch/arm64/boot/dts/marvell/88pm886.dtsi
index 084e922f4e4c..f5c6084673e4 100644
--- a/arch/arm64/boot/dts/marvell/88pm886.dtsi
+++ b/arch/arm64/boot/dts/marvell/88pm886.dtsi
@@ -57,7 +57,7 @@ ldo1: regulator-ldo1 {
*/
ldo2: regulator-ldo2 {
compatible = "marvell,88pm886-ldo2";
- regulator-min-microvolt = <1700000>;
+ regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3300000>;
};
/*
--
2.42.0

57
device/testing/linux-samsung-coreprimevelte-mainline/APKBUILD
View file

@ -2,12 +2,13 @@
_flavor=samsung-coreprimevelte-mainline
pkgname=linux-$_flavor
pkgver=6.6_rc3
pkgver=6.6_rc7
pkgrel=0
pkgdesc="Samsung Galaxy Core Prime VE LTE mainline kernel"
arch="aarch64"
_carch="arm64"
url="https://github.com/torvalds/linux"
url="https://gitlab.com/LegoLivesMatter/linux"
_commit="176815956535335881bcc0f880355b12683d5560"
license="GPL-2.0-only"
options="!strip !check !tracedeps pmb:cross-native pmb:kconfigcheck-nftables
pmb:kconfigcheck-zram"
@ -15,35 +16,12 @@ makedepends="bash bc bison devicepkg-dev findutils flex gmp-dev mpc1-dev
mpfr-dev openssl-dev perl postmarketos-installkernel pxa-mkbootimg dtc"
# Source
_tag="${pkgver//_/-}"
_config="config-$_flavor.$arch"
source="
linux-$_tag.tar.gz::$url/archive/refs/tags/v$_tag.tar.gz
$pkgname-$_commit.tar.gz::$url/-/archive/$_commit/linux-$_commit.tar.gz
$_config
0001-gpio-pxa-disable-pinctrl-calls-for-MMP_GPIO.patch
0002-clk-mmp-Switch-to-use-struct-u32_fract-instead-of-cu.patch
0003-dt-bindings-clock-Add-Marvell-PXA1908-clock-bindings.patch
0004-clk-mmp-Add-Marvell-PXA1908-clock-driver.patch
0005-dt-bindings-marvell-Document-PXA1908-SoC.patch
0006-arm64-Kconfig.platforms-Add-config-for-Marvell-PXA19.patch
0007-arm64-dts-Add-DTS-for-Marvell-PXA1908-and-samsung-co.patch
0008-MAINTAINERS-add-myself-as-Marvell-PXA1908-maintainer.patch
0009-DONOTMERGE-Enable-AArch64-system-timer-properly.patch
0010-DONOTMERGE-Add-pxa-rev-id-to-board-dts.patch
0011-input-generalize-the-Imagis-touchscreen-driver.patch
0012-Documentation-imagis-document-IST3032C-support.patch
0013-input-Imagis-add-support-for-IST3032C-touchscreen.patch
0014-arm64-dts-add-touchscreen-bindings-for-samsung-corep.patch
0015-mfd-add-Marvell-88pm88x-description.patch
0016-mfd-88pm88x-initialize-88pm886-88pm880-base-support.patch
0017-DONOTMERGE-fix-88pm88x-build.patch
0018-DONOTMERGE-add-downstream-regulator-driver.patch
0019-DONOTMERGE-fix-build-for-the-88pm88x-regulator-drive.patch
0020-DONOTMERGE-add-88pm88x-DT-bindings.patch
0021-set-touchscreen-VDD-regulator-to-3.1V.patch
"
builddir="$srcdir/linux-$_tag"
builddir="$srcdir/linux-$_commit"
prepare() {
default_prepare
@ -74,27 +52,6 @@ package() {
}
sha512sums="
59dfaf0d49d898c0f00019364845271f58ad4401f7f2a6fe3e2b3718a29a5e183a356b5400f4936967bc215471dbe87278ec5c3ab6e9e52643d7e869233b3833 linux-6.6-rc3.tar.gz
e2b61e3c9de6f15db3cf6ea116f9466755c783d40c7085ab01fb4f6ae02e813524b137ad6f0fd2c0624457559778c32f8b22031238ab4353702cd15c33bf4a16 config-samsung-coreprimevelte-mainline.aarch64
0069e76bf9695da6a944e43aff6b21c928d3816765eee483135cc523b19668fa8a3da547565a55b39adcd9f01e125b48e22f1eafb78cbb4d97b39f8c3bd8f80a 0001-gpio-pxa-disable-pinctrl-calls-for-MMP_GPIO.patch
2ef0a47ba941202c3ed61063c781ae73dcb2b05ab229c4863c610f809716bd9159cae58468fcd1559913fcba6f2de4f940df58104687cfebb631fe2ee5cd7e33 0002-clk-mmp-Switch-to-use-struct-u32_fract-instead-of-cu.patch
841d1df7e18e58893c82f5a0a48e06d82954721b1392b9c36ef555150ef3d82fa7d3b33c1b30ebf7b1cf55a6fcc9e3f032667bc30f664176e046d6f9756da238 0003-dt-bindings-clock-Add-Marvell-PXA1908-clock-bindings.patch
b0e5e538ab7837351a8c2feb32a6c6f81cb8f37edafd4ea68ed3a74c6d6b27745a54b4bd1b8839bb4f84daa5635cbbf62453cc1f17c59216e562442bc1833eb2 0004-clk-mmp-Add-Marvell-PXA1908-clock-driver.patch
22472dfd020364bf32e7e9d350f91ea07761e4f8c291cfde37e5c8d334a88290565320b167264d1a5f51a257702d7c41cafb6d0ae15baf37a32defee21170fe8 0005-dt-bindings-marvell-Document-PXA1908-SoC.patch
84ab5f554ae9d8a41d1baa9743c9f066e0ac7c3183d9ab53ab8225c381ff5e19cce73f4ec1a567f6a8b9ba962318bd323f1f117bb553cf3ef628b572bb7fd585 0006-arm64-Kconfig.platforms-Add-config-for-Marvell-PXA19.patch
7305a9275ba74718932f5bb409d0d1b3eb029ecc620c3878b58091994f6da400203c58ce535f877bd4d06f86d9cdc1e8512cef073e4d1118fa8ccb54f254129c 0007-arm64-dts-Add-DTS-for-Marvell-PXA1908-and-samsung-co.patch
16588e84d9650d405b2cf23edc0648de29b4b74869648e29c84a83ebda776a5ba2c6b97039a9d73c1c5683040ad77b470ea73fd9fe151a2d333a47b54bac34b6 0008-MAINTAINERS-add-myself-as-Marvell-PXA1908-maintainer.patch
fc5cd8a5de0c4c7e177673535de98377059ac2a905492c095bb1b292447a97acc0df681970cdfd327a0e39ff9c95955d258095965513555cd310a0d58fa0b272 0009-DONOTMERGE-Enable-AArch64-system-timer-properly.patch
d73005b5581d5e0b5a7c73b5f67be209a0032f605955775e83737c0250aeb13157e97bfe93f7a9ec77c49f040478b15bde9ca715b4c5fa2f3f900f5c1c83ec0c 0010-DONOTMERGE-Add-pxa-rev-id-to-board-dts.patch
39ceaf8cada08dcc5e43b97dfc56e4370308c78faa01ce8f8ccaf955c26717ea783014f5b6e3263d07d5f1bb8997206209cd97ca67918d6f8747f27d35feeaf5 0011-input-generalize-the-Imagis-touchscreen-driver.patch
7a2c2b5251a9cc0687c6e9cde4079532d75ae9dc76bad96acae95879b031560fe63568b359948fe08a6a224c1c0a3c8a96766f89bb9aabce5fc4c3b531449930 0012-Documentation-imagis-document-IST3032C-support.patch
0bd27a665556a329dc8c009ba37cc10395c570a150380317ad103984da9d53240b3221c0f471113783d56863e0afa6e1dc2ed9f152f9c9be339f9d75763d106b 0013-input-Imagis-add-support-for-IST3032C-touchscreen.patch
631682ed29640028cb8de8278578140a9538a954e5bcf22614fd513caebfe33bc280e06b08f784bb8c9414c4e2b0ac5672a8df19ef1526af58f9d0d25070668a 0014-arm64-dts-add-touchscreen-bindings-for-samsung-corep.patch
b70b301d33b3703543e097aecfd4dc2c428039d58ed99b5977927bb2857cb9d8038d9bfe16effc857aa2a8a520498b13e5ebfbf0340b0f1140f97815bbf6adcd 0015-mfd-add-Marvell-88pm88x-description.patch
b4bbc5f90f10335129e1e6ff23895a5bce05fa7d7e943d0f57ec5889e56572847e756a4d44b0a0c4fc18e78fbb0a4b0f8b6ffa58421f6147d75d069741d7175e 0016-mfd-88pm88x-initialize-88pm886-88pm880-base-support.patch
e2a1c8dbbe96b5c4df48273c82f7974d06d009e39c0602e4daafb3b920cb825ad65f8378ecaac53f0730eb0a3aaf303ffd0edd20a5d19806e605b651a94a8549 0017-DONOTMERGE-fix-88pm88x-build.patch
0db0c7c0919470cc8e3ea13a6eb9b992562a023b67ffb1445a203bcf65f8658ae4771b23af27b8e21c4da133a863db80186a7cd382027c56c89024947bcb6a9a 0018-DONOTMERGE-add-downstream-regulator-driver.patch
c65a7ab9e3dd5bf44358ef9963d31224abe5d1d47d74c796fe30b478d13bbef78db54b3ede9875751399d12667b8ea7c6392d7e5a3ee2ffc35f8c223db8565e1 0019-DONOTMERGE-fix-build-for-the-88pm88x-regulator-drive.patch
0db204bc989a0db2f2da1fd6f7a8190219abda36da7d8e45363cdf1563816b3036306a36e563661774279a7fd2976808df149320e19c377a05ec8ff65442de79 0020-DONOTMERGE-add-88pm88x-DT-bindings.patch
68badc34bf07c63785f9a34bbf9e2cf02c419fafae299d7ab3b0eb17cb1dd5da703308720ba987b6cc7cb8db17f893f59fc6710daec1a3e0dba96d36aa5756bb 0021-set-touchscreen-VDD-regulator-to-3.1V.patch
d1ad86165230b9a21d5744af169f353c00028172b57758da58d00130e2ca58befe68f08e86ff23f4355bad104439b4d37d6a042bb504154f0671f106f469c6e7 linux-samsung-coreprimevelte-mainline-176815956535335881bcc0f880355b12683d5560.tar.gz
cd5331fe6fde288c029a46bb87c971dc0d12a9f82b639c2946dc202488a79c645fdb601aa8694aa48b57c34362d9dbceca9d1b952c794b5d5f613a489f637a8b config-samsung-coreprimevelte-mainline.aarch64
"

74
device/testing/linux-samsung-coreprimevelte-mainline/config-samsung-coreprimevelte-mainline.aarch64
View file

@ -1,6 +1,6 @@
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 6.6.0-rc3 Kernel Configuration
# Linux/arm64 6.6.0-rc7 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-alpine-linux-musl-gcc (Alpine 13.1.1_git20230722) 13.1.1 20230722"
CONFIG_CC_IS_GCC=y
@ -250,6 +250,7 @@ CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters
CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
#
@ -374,6 +375,7 @@ CONFIG_ARM64_ERRATUM_2067961=y
CONFIG_ARM64_ERRATUM_2441009=y
CONFIG_ARM64_ERRATUM_2457168=y
CONFIG_ARM64_ERRATUM_2645198=y
CONFIG_ARM64_ERRATUM_2966298=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23144=y
CONFIG_CAVIUM_ERRATUM_23154=y
@ -1266,11 +1268,16 @@ CONFIG_NET_FLOW_LIMIT=y
# CONFIG_AF_KCM is not set
# CONFIG_MCTP is not set
CONFIG_WIRELESS=y
# CONFIG_CFG80211 is not set
#
# CFG80211 needs to be enabled for MAC80211
#
CONFIG_CFG80211=m
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
# CONFIG_CFG80211_WEXT is not set
# CONFIG_MAC80211 is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
@ -1559,7 +1566,32 @@ CONFIG_NET_CORE=y
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_USB_NET_DRIVERS is not set
# CONFIG_WLAN is not set
CONFIG_WLAN=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
# CONFIG_WLAN_VENDOR_ATMEL is not set
# CONFIG_WLAN_VENDOR_BROADCOM is not set
# CONFIG_WLAN_VENDOR_CISCO is not set
# CONFIG_WLAN_VENDOR_INTEL is not set
# CONFIG_WLAN_VENDOR_INTERSIL is not set
CONFIG_WLAN_VENDOR_MARVELL=y
# CONFIG_LIBERTAS is not set
CONFIG_MWIFIEX=m
CONFIG_MWIFIEX_SDIO=m
# CONFIG_MWIFIEX_USB is not set
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
# CONFIG_WLAN_VENDOR_MICROCHIP is not set
# CONFIG_WLAN_VENDOR_PURELIFI is not set
# CONFIG_WLAN_VENDOR_RALINK is not set
# CONFIG_WLAN_VENDOR_REALTEK is not set
# CONFIG_WLAN_VENDOR_RSI is not set
# CONFIG_WLAN_VENDOR_SILABS is not set
# CONFIG_WLAN_VENDOR_ST is not set
# CONFIG_WLAN_VENDOR_TI is not set
# CONFIG_WLAN_VENDOR_ZYDAS is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
# CONFIG_USB_NET_RNDIS_WLAN is not set
# CONFIG_VIRT_WIFI is not set
# CONFIG_WAN is not set
#
@ -2409,6 +2441,7 @@ CONFIG_REGULATOR_88PM800=y
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
# CONFIG_REGULATOR_RAA215300 is not set
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
# CONFIG_REGULATOR_RT4801 is not set
# CONFIG_REGULATOR_RT4803 is not set
# CONFIG_REGULATOR_RT5190A is not set
@ -2491,8 +2524,16 @@ CONFIG_DRM_PANEL=y
# Display Panels
#
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
# CONFIG_DRM_PANEL_LVDS is not set
# CONFIG_DRM_PANEL_SIMPLE is not set
# CONFIG_DRM_PANEL_EDP is not set
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
# end of Display Panels
@ -2592,7 +2633,19 @@ CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
# Backlight & LCD device support
#
# CONFIG_LCD_CLASS_DEVICE is not set
# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=m
# CONFIG_BACKLIGHT_KTD253 is not set
CONFIG_BACKLIGHT_KTD2801=m
# CONFIG_BACKLIGHT_KTZ8866 is not set
# CONFIG_BACKLIGHT_QCOM_WLED is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_GPIO is not set
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
# CONFIG_BACKLIGHT_LED is not set
# end of Backlight & LCD device support
CONFIG_HDMI=y
@ -2943,6 +2996,7 @@ CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
# CONFIG_PWRSEQ_SD8787 is not set
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=8
@ -3508,8 +3562,6 @@ CONFIG_PHY_PXA_USB=y
# CONFIG_PHY_OCELOT_SERDES is not set
# CONFIG_PHY_QCOM_USB_HS is not set
# CONFIG_PHY_QCOM_USB_HSIC is not set
# CONFIG_PHY_RTK_RTD_USB2PHY is not set
# CONFIG_PHY_RTK_RTD_USB3PHY is not set
# CONFIG_PHY_TUSB1210 is not set
# end of PHY Subsystem
@ -4074,6 +4126,8 @@ CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_PKCS7_TEST_KEY is not set
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
# CONFIG_FIPS_SIGNATURE_SELFTEST is not set
#