62 lines
1.8 KiB
Diff
62 lines
1.8 KiB
Diff
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From ef740fff300fd9eb8285fb5611f6205705ee54ec Mon Sep 17 00:00:00 2001
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From: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
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Date: Fri, 23 Jun 2023 15:27:17 +0530
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Subject: [PATCH 35/35] Fix ICE observed in PR110280.
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gcc/ChangeLog:
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PR tree-optimization/110280
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* match.pd (vec_perm_expr(v, v, mask) -> v): Explicitly build vector
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using build_vector_from_val with the element of input operand, and
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mask's type if operand and mask's types don't match.
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gcc/testsuite/ChangeLog:
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PR tree-optimization/110280
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* gcc.target/aarch64/sve/pr110280.c: New test.
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---
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gcc/match.pd | 9 ++++++++-
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gcc/testsuite/gcc.target/aarch64/sve/pr110280.c | 12 ++++++++++++
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2 files changed, 20 insertions(+), 1 deletion(-)
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create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
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diff --git a/gcc/match.pd b/gcc/match.pd
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index 91182448250..c3bb4fbc0a7 100644
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--- a/gcc/match.pd
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+++ b/gcc/match.pd
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@@ -8292,7 +8292,14 @@ and,
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(simplify
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(vec_perm vec_same_elem_p@0 @0 @1)
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- @0)
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+ (if (types_match (type, TREE_TYPE (@0)))
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+ @0
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+ (with
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+ {
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+ tree elem = uniform_vector_p (@0);
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+ }
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+ (if (elem)
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+ { build_vector_from_val (type, elem); }))))
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/* Push VEC_PERM earlier if that may help FMA perception (PR101895). */
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(simplify
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diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
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new file mode 100644
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index 00000000000..d3279f38362
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
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@@ -0,0 +1,12 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O3 -fdump-tree-optimized" } */
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+
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+#include "arm_sve.h"
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+
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+svuint32_t l()
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+{
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+ _Alignas(16) const unsigned int lanes[4] = {0, 0, 0, 0};
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+ return svld1rq_u32(svptrue_b8(), lanes);
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+}
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+
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+/* { dg-final { scan-tree-dump-not "VEC_PERM_EXPR" "optimized" } } */
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--
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2.41.0
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