60 lines
2.4 KiB
Diff
60 lines
2.4 KiB
Diff
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commit 611c7138d2812827c3a62940576bf62c61cd8515
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Author: Henrik Grimler <henrik@grimler.se>
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Date: Fri Nov 27 18:01:34 2020 +0100
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Fix so that FIMC IS can be disabled
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* mach-exynos: don't set EXYNOS5_{DEV,SETUP}_FIMC_IS for universal5420
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* board-universal5420-media: add ifdef guard to fix compilation error
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* pm_domains: always init exynos54xx_pd_isp to prevent null pointer dereference
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diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
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index 2aed1a4dfbac..9667d665363d 100644
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--- a/arch/arm/mach-exynos/Kconfig
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+++ b/arch/arm/mach-exynos/Kconfig
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@@ -883,8 +883,6 @@ config MACH_UNIVERSAL5420
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select EXYNOS5_SETUP_HSI2C4
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select EXYNOS5_SETUP_HSI2C5
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select EXYNOS5_SETUP_HSI2C6
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- select EXYNOS5_DEV_FIMC_IS
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- select EXYNOS5_SETUP_FIMC_IS
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help
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Machine support for Universal board based on EXYNOS5420
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endif
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diff --git a/arch/arm/mach-exynos/board-universal5420-media.c b/arch/arm/mach-exynos/board-universal5420-media.c
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index 91677b04f9e8..4e461819fa68 100644
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--- a/arch/arm/mach-exynos/board-universal5420-media.c
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+++ b/arch/arm/mach-exynos/board-universal5420-media.c
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@@ -1166,6 +1166,7 @@ void __init exynos5_universal5420_media_init(void)
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sizeof(s5p_mipi_csis1_default_data), &s5p_device_mipi_csis1);
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#endif
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+#ifdef CONFIG_VISION_MODE
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#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
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#if !defined(CONFIG_V1A) && !defined(CONFIG_V2A)
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s3c_i2c1_set_platdata(NULL);
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@@ -1178,6 +1179,7 @@ void __init exynos5_universal5420_media_init(void)
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s3c_set_platdata(&exynos_flite2_default_data,
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sizeof(exynos_flite2_default_data), &exynos_device_flite2);
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#endif
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+#endif /* CONFIG_VISION_MODE */
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/* camera */
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#ifdef CONFIG_VIDEO_EXYNOS5_FIMC_IS
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diff --git a/arch/arm/mach-exynos/pm_domains5.c b/arch/arm/mach-exynos/pm_domains5.c
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index 3220333bed94..2599bb756958 100644
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--- a/arch/arm/mach-exynos/pm_domains5.c
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+++ b/arch/arm/mach-exynos/pm_domains5.c
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@@ -1224,8 +1224,8 @@ static int exynos5420_pm_domain_init(void)
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exynos_pm_add_clk(&exynos5420_spd_mscl1, NULL, "mscl");
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exynos_pm_add_clk(&exynos5420_spd_mscl2, NULL, "mscl");
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#endif
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-#ifdef CONFIG_EXYNOS5_DEV_FIMC_IS
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exynos_pm_powerdomain_init(&exynos54xx_pd_isp);
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+#ifdef CONFIG_EXYNOS5_DEV_FIMC_IS
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exynos_pm_add_platdev(&exynos54xx_pd_isp, &exynos5_device_fimc_is);
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exynos_pm_add_platdev(&exynos54xx_pd_isp, &s3c64xx_device_spi3);
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exynos_pm_add_clk(&exynos54xx_pd_isp, &exynos5_device_fimc_is.dev, "gscl_wrap0");
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