35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
|
From 2a6027178ae40c1d3baa965fe21b19cbf09493ce Mon Sep 17 00:00:00 2001
|
||
|
|
From: =?UTF-8?q?Arve=20Hj=C3=B8nnev=C3=A5g?= <arve@android.com>
|
||
|
|
Date: Fri, 30 Nov 2012 17:05:40 -0800
|
||
|
|
Subject: [PATCH] ARM: decompressor: Flush tlb before swiching domain 0 to
|
||
|
|
client mode
|
||
|
|
MIME-Version: 1.0
|
||
|
|
Content-Type: text/plain; charset=UTF-8
|
||
|
|
Content-Transfer-Encoding: 8bit
|
||
|
|
|
||
|
|
If the bootloader used a page table that is incompatible with domain 0
|
||
|
|
in client mode, and boots with the mmu on, then swithing domain 0 to
|
||
|
|
client mode causes a fault if we don't flush the tlb after updating
|
||
|
|
the page table pointer.
|
||
|
|
|
||
|
|
v2: Add ISB before loading dacr.
|
||
|
|
|
||
|
|
Signed-off-by: Arve Hjønnevåg <arve@android.com>
|
||
|
|
---
|
||
|
|
arch/arm/boot/compressed/head.S | 2 ++
|
||
|
|
1 file changed, 2 insertions(+)
|
||
|
|
|
||
|
|
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
|
||
|
|
index 434a16982e344..d6f6a58ba931b 100644
|
||
|
|
--- a/arch/arm/boot/compressed/head.S
|
||
|
|
+++ b/arch/arm/boot/compressed/head.S
|
||
|
|
@@ -883,6 +883,8 @@ __armv7_mmu_cache_on:
|
||
|
|
bic r6, r6, #1 << 31 @ 32-bit translation system
|
||
|
|
bic r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0
|
||
|
|
mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
|
||
|
|
+ mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
|
||
|
|
+ mcr p15, 0, r0, c7, c5, 4 @ ISB
|
||
|
|
mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
|
||
|
|
mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
|
||
|
|
#endif
|